JPH0353843U - - Google Patents
Info
- Publication number
- JPH0353843U JPH0353843U JP1989115548U JP11554889U JPH0353843U JP H0353843 U JPH0353843 U JP H0353843U JP 1989115548 U JP1989115548 U JP 1989115548U JP 11554889 U JP11554889 U JP 11554889U JP H0353843 U JPH0353843 U JP H0353843U
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- dummy electrode
- electrode
- semiconductor device
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000008188 pellet Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
第１図は、本考案の一実施例に係る半導体装置
の部分縦断面図、第２図は、同じくペレツト上の
ダミー電極とパツド電極の配置を示す部分平面図
、第３図は、同じくペレツト上のダミー電極とパ
ツド電極の配置の他の例を示す平面図、第４図は
、同じくペレツト上のダミー電極とパツド電極の
配置のさらに他の例を示す部分平面図、第５図は
、従来例を示す半導体装置の部分縦断面図である
。
１……ペレツト、３……パツド電極、４……ダ
ミー電極、５……絶縁膜、５ｂ……開口部。
FIG. 1 is a partial vertical sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a partial plan view showing the arrangement of dummy electrodes and pad electrodes on a pellet, and FIG. FIG. 4 is a plan view showing another example of the arrangement of the above dummy electrodes and pad electrodes, FIG. 4 is a partial plan view showing still another example of the arrangement of the dummy electrodes and pad electrodes on the pellet, and FIG. FIG. 2 is a partial longitudinal cross-sectional view of a semiconductor device showing a conventional example. 1... Pellet, 3... Pad electrode, 4... Dummy electrode, 5... Insulating film, 5b... Opening.
Claims (1)
ダミー電極が設けられ、かつ、ペレツト上を覆う
絶縁膜にダミー電極に通じる開口部が設けられて
いることを特徴とする半導体装置。 A semiconductor device characterized in that a dummy electrode is provided at least on the outer edge side of a pad electrode on a pellet, and an opening communicating with the dummy electrode is provided in an insulating film covering the pellet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989115548U JPH0353843U (en) | 1989-09-29 | 1989-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989115548U JPH0353843U (en) | 1989-09-29 | 1989-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0353843U true JPH0353843U (en) | 1991-05-24 |
Family
ID=31663875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989115548U Pending JPH0353843U (en) | 1989-09-29 | 1989-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0353843U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015170778A (en) * | 2014-03-07 | 2015-09-28 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of the same |
| CN106328626A (en) * | 2015-06-30 | 2017-01-11 | 精工半导体有限公司 | Semiconductor device |
-
1989
- 1989-09-29 JP JP1989115548U patent/JPH0353843U/ja active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015170778A (en) * | 2014-03-07 | 2015-09-28 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of the same |
| CN106328626A (en) * | 2015-06-30 | 2017-01-11 | 精工半导体有限公司 | Semiconductor device |
| JP2017017152A (en) * | 2015-06-30 | 2017-01-19 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device |
| CN106328626B (en) * | 2015-06-30 | 2020-03-17 | 艾普凌科有限公司 | Semiconductor device with a plurality of semiconductor chips |