JPH0350770A - Mos type semiconductor integrated circuit device - Google Patents
Mos type semiconductor integrated circuit deviceInfo
- Publication number
- JPH0350770A JPH0350770A JP18536389A JP18536389A JPH0350770A JP H0350770 A JPH0350770 A JP H0350770A JP 18536389 A JP18536389 A JP 18536389A JP 18536389 A JP18536389 A JP 18536389A JP H0350770 A JPH0350770 A JP H0350770A
- Authority
- JP
- Japan
- Prior art keywords
- high melting
- layer
- polycrystalline silicon
- silicon layer
- point metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 150000004767 nitrides Chemical class 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000002844 melting Methods 0.000 claims description 21
- 230000008018 melting Effects 0.000 claims description 16
- 239000003870 refractory metal Substances 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 abstract description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 10
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 239000013078 crystal Substances 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000006263 metalation reaction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 10
- 230000002411 adverse Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明はＭＯＳ型半導体集積回路装置の電極構造に関し
、電極に高融点金属を用いた電極構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrode structure for a MOS type semiconductor integrated circuit device, and more particularly to an electrode structure using a high melting point metal for the electrode.
［従来の技術］
従来より、半導体装置の電極配線にはＡＬや多結晶シリ
コン、それに多結晶シリコン層とシリサイド層の二層を
用いたポリサイド配線が広（用いられている。ＡＪ、は
比抵抗が小さ（、シリコン基板とのコンタクトも良好で
あるため多用されているが融点が低いために高温処理工
程が全て終了した後でなげれば用いられないという制約
がある。[Prior Art] Conventionally, AL, polycrystalline silicon, and polycide wiring using two layers of a polycrystalline silicon layer and a silicide layer have been widely used for electrode wiring of semiconductor devices. AJ is the specific resistance. It is often used because it has a small surface area (and good contact with the silicon substrate), but its low melting point means that it cannot be used unless it is removed after all high-temperature treatment steps are completed.
従って、ＭＯＳデバイスを自己整合法で作る場合や多１
ツ配線構造の集積回路を作る場合には多結晶シリコン配
線やポリサイド配線が良（用いられる微線化が進むにつ
れて、配線の抵抗が問題になり、多結晶シリコン配線か
らポリサイ４、ド配線に変わり、２μｍプロセス、１．
２μｍプロセス、０．８μｍプロセスでは、おもにポリ
サイド配線が使用されている。しかし、微細化が進むに
したがってポリサイド配線でも抵抗が問題になり、高融
点金属配線の実用化が要求されている。Therefore, when making MOS devices using the self-alignment method,
Polycrystalline silicon interconnects and polycide interconnects are preferable when making integrated circuits with a two-wire structure (as the wires used become finer, the resistance of the interconnects becomes a problem, and polycrystalline silicon interconnects are replaced by polycrystalline silicon interconnects and polycide interconnects. , 2 μm process, 1.
In the 2 μm process and the 0.8 μm process, polycide wiring is mainly used. However, as miniaturization progresses, resistance becomes a problem even with polycide wiring, and there is a demand for practical use of refractory metal wiring.
しかし、高融点金属配線の実用化にはい（つかの問題点
が残っており、いまだ実用化にいたっていない。However, there are still some problems with the practical application of high-melting point metal wiring, and it has not yet been put into practical use.
第２図（α）〜第２図（ｄ）に例を挙げ以下に従来の方
法について説明する。The conventional method will be described below with examples shown in FIGS. 2(α) to 2(d).
第２図（ＩＺ）に示すように、Ｐ型Ｓ１１結晶基板１１
上に、フィールド酸化膜１２とゲート絶縁膜１３を形成
する。As shown in FIG. 2 (IZ), a P-type S11 crystal substrate 11
A field oxide film 12 and a gate insulating film 13 are formed thereon.
第２図（ｂ）に示すように、多結晶シリコン層１４を形
成した後、Ｎ＋拡散を熱拡散でおこなった後、その上に
高融点金属層１５を形成した後、電極及び配線となる部
分を残して、他をホトエツチングで除去する。As shown in FIG. 2(b), after a polycrystalline silicon layer 14 is formed, N+ diffusion is performed by thermal diffusion, and a high melting point metal layer 15 is formed thereon. The remaining parts are removed by photo-etching.
第２図（Ｃ）に示すように、イオン打込みによってＮ＋
拡散をおこない、ソース及びドレイン１６を形成する。As shown in Figure 2 (C), N+
Diffusion is performed to form the source and drain 16.
その上に、０ＶＤＳｉＯ，膜１７を形成する。A 0VDSiO film 17 is formed thereon.
第２図（ｄ）に示すように、窒素雰囲気中で高温の熱処
理をおこなって、ソース及びドレイン１６の不純物の活
性化とＯ’ＶＤＳｉＯ，膜１７のアニールをおこなう。As shown in FIG. 2(d), high temperature heat treatment is performed in a nitrogen atmosphere to activate impurities in the source and drain 16 and anneal the O'VDSiO film 17.
熱アニール工程が入ると、多結晶シリコン層１４と高融
点金属層１５が反応してシリサイド層１８が形成される
。When the thermal annealing step is performed, the polycrystalline silicon layer 14 and the high melting point metal layer 15 react to form a silicide layer 18.
多結晶シリコンの厚みによるが、熱処理の温度と時間に
よって、反応が進行し、場合によっては下地となる多結
晶シリコン層がなくなってしまうほど反応が進行する。Although it depends on the thickness of the polycrystalline silicon, the reaction progresses depending on the temperature and time of the heat treatment, and in some cases, the reaction progresses to such an extent that the underlying polycrystalline silicon layer disappears.
この反応の進行具合によって、シリサイドの結晶粒が多
結晶シリコンを突き抜けたり、シリサイド膜及び高融点
金属膜のヒズミが直接、ゲート絶縁膜につたわり、ゲー
ト絶縁膜に悪影響をおよぼし、ゲート絶縁膜の絶縁耐圧
をいちじるしく降下させると同時に、絶縁が破壊される
にいたる。この現象によって、歩留りが低下すると同時
に信頼性がいちじるしく悪（、高融点金属のゲート電極
及び配線に使用されえなかつた。Depending on the progress of this reaction, silicide crystal grains may penetrate the polycrystalline silicon, or distortions in the silicide film and high-melting point metal film may be directly transmitted to the gate insulating film, adversely affecting the gate insulating film. At the same time, the dielectric strength drops significantly and the insulation is destroyed. Due to this phenomenon, the yield was reduced and the reliability was so bad that it could not be used for gate electrodes and wiring made of high melting point metals.
［発明が解決しようとする課題］
本発明の方法は、熱処理によっておこる高融点金属層の
下地多結晶シリコン層との反応、それによって発生する
多結晶シリコン層の薄膜化、シリサイド粒の多結晶シリ
コン層の突き抜け、及びシリサイド膜及び高融点金属膜
のヒズミの影響を防止し、ゲート絶縁膜への悪影響（耐
圧降下、絶縁リーク等）を防止し、素子の歩留向上及び
信頼性を向上する事を目的とする。[Problems to be Solved by the Invention] The method of the present invention deals with the reaction of the high-melting point metal layer with the base polycrystalline silicon layer caused by heat treatment, the thinning of the polycrystalline silicon layer generated thereby, and the thinning of the polycrystalline silicon layer of silicide grains. Preventing layer penetration and the effects of distortion on silicide films and high-melting point metal films, preventing adverse effects on gate insulating films (voltage drop, insulation leakage, etc.), and improving device yield and reliability. With the goal.
［課題を解決するための手段］
不純物をドープした多結晶シリコン層上に安定で導電性
のある高融点金属の窒化膜を形成し、その上に高融点金
属層を形成する事によって高融点金属が多結晶シリコン
層の中に侵入し、反応してシリサイドを形成してい（の
を防止する。[Means for solving the problem] A stable and conductive high melting point metal nitride film is formed on a polycrystalline silicon layer doped with impurities, and a high melting point metal layer is formed on top of the high melting point metal nitride film. (prevents) from penetrating into the polycrystalline silicon layer and reacting to form silicide.
［実施例］
第１図（α）〜第１図（ｄ）に例を挙げて本発明の方法
について説明する。[Example] The method of the present invention will be described with reference to FIGS. 1(α) to 1(d) as examples.
第１図（α）に示すように、Ｐ型Ｓ１単結晶基板１上に
、フィールド酸化膜２及びゲート絶縁膜３を形成する。As shown in FIG. 1(α), a field oxide film 2 and a gate insulating film 3 are formed on a P-type S1 single crystal substrate 1.
第１図（ｈ）に示すように、その上に、多結晶シリコン
層４を５００＾程度形成したのち、Ｎ＋拡散を熱拡散で
おこなう。その上にチタンナイトライド層８を４ｏｏＸ
Ｈ度形成し、その上に、高融点金属層５を３０００Ｘ程
度形成し、必要な電極及び配線領域を残して、他をエツ
チング除去する。As shown in FIG. 1(h), a polycrystalline silicon layer 4 having a thickness of about 500^ is formed thereon, and then N+ diffusion is performed by thermal diffusion. 4ooX titanium nitride layer 8 on top of it
A high melting point metal layer 5 is formed thereon to a thickness of about 3000X, and the necessary electrode and wiring areas are left and the rest are removed by etching.
第１図＜ｃ＞に示すように、イオン打込みによってＮ
拡散をおこない、ソース及びドレイン６を形成する。そ
の上に、ｏｖｐｓｔｏ、ｇ７を形成する。As shown in Figure 1 <c>, N
Diffusion is performed to form the source and drain 6. On top of that, form ovpsto, g7.
第１図（ｄ）に示すように、窒素雰囲気中で高温の熱処
理をおこなって、ソース及びドレイン乙の不純物の活性
化と０ＶＤＳｉ０２膜７のアニールをおこなう。熱アニ
ール工程が入っても多結晶シリコン層と高融点金属層と
の間にチタンナイトライド膜があるので、両者の反応は
おこらない。As shown in FIG. 1(d), high temperature heat treatment is performed in a nitrogen atmosphere to activate impurities in the source and drain and anneal the 0VDSi02 film 7. Even if a thermal annealing process is performed, since there is a titanium nitride film between the polycrystalline silicon layer and the high melting point metal layer, no reaction between the two will occur.
［発明の効果コ
本発明の方法によると、多結晶シリコン層と高融点金属
層の間に安定な、導電性のある高融点金属窒化物層をも
うける事によって、上層の高融点金属層と多結晶シリコ
ン層と反応するのを防止し、反応によって発生するシリ
サイドの結晶粒が多結晶シリコン層を突き抜けて、ゲー
ト膜に悪影響を与えたり、シリサイド膜及び高融点金属
膜のヒズミが直接ゲート絶縁膜につたわって、絶縁耐圧
をいちじるしく降下させたり、絶縁が破壊されるといっ
た事もな（なる。[Effects of the Invention] According to the method of the present invention, by providing a stable and conductive high melting point metal nitride layer between the polycrystalline silicon layer and the high melting point metal layer, the upper high melting point metal layer and the polycrystalline silicon layer are bonded. It prevents silicide crystal grains generated by the reaction from penetrating the polycrystalline silicon layer and adversely affecting the gate film, or distortions in the silicide film and high-melting point metal film directly damage the gate insulating film. There is no possibility that the dielectric strength will drop significantly or the insulation will be destroyed.
又、そのために下地の多結晶シリコン層を薄（する事が
でき、電極及び配線を薄（でき、段差形状を改善する事
ができる。Moreover, for this reason, the underlying polycrystalline silicon layer can be made thinner, the electrodes and wiring can be made thinner, and the step shape can be improved.
又、必要に応じて、段差形状をそのままにして高融点金
属層を厚くする事ができ、配線抵抗を小さ（する事がで
きる。Furthermore, if necessary, the high melting point metal layer can be made thicker while leaving the stepped shape unchanged, and the wiring resistance can be reduced.
第１図（α）〜第１図（ｄ）は本発明の方法による、工
程順の断面略図である。
第２図（α）〜第２図（ｄ）は従来の方法による、工程
順の断面略図である。
以上FIG. 1(α) to FIG. 1(d) are schematic cross-sectional views of the process steps according to the method of the present invention. FIG. 2(α) to FIG. 2(d) are schematic cross-sectional views of the steps in the conventional method. that's all
Claims (3)
基板と逆導電型不純物もしくは同じ導電型不純物がドー
プされた多結晶シリコン層、高融点金属窒化物層及び高
融点金属層からなりたっているゲート電極を有する事を
特徴とするＭＯＳ型半導体集積回路装置。(1) On the gate insulating film formed on the surface of the semiconductor substrate,
A MOS type semiconductor integrated circuit device characterized by having a gate electrode made of a polycrystalline silicon layer doped with an impurity of conductivity type opposite to that of the substrate or an impurity of the same conductivity type as the substrate, a refractory metal nitride layer, and a refractory metal layer. .
ある事を特徴とする請求項１記載のＭＯＳ型半導体集積
回路装置。(2) The MOS type semiconductor integrated circuit device according to claim 1, wherein the high melting point metal nitride layer is a titanium nitride film.
Å、該高融点金属窒化物層の厚みが１００Å〜１５００
Åである事を特徴とする請求項１記載のＭＯＳ型半導体
集積回路装置。(3) The thickness of the polycrystalline silicon layer is 200 Å to 2500 Å.
Å, the thickness of the high melting point metal nitride layer is 100 Å to 1500 Å
2. The MOS type semiconductor integrated circuit device according to claim 1, wherein the MOS semiconductor integrated circuit device is Å.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18536389A JPH0350770A (en) | 1989-07-18 | 1989-07-18 | Mos type semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18536389A JPH0350770A (en) | 1989-07-18 | 1989-07-18 | Mos type semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0350770A true JPH0350770A (en) | 1991-03-05 |
Family
ID=16169491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18536389A Pending JPH0350770A (en) | 1989-07-18 | 1989-07-18 | Mos type semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0350770A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5668394A (en) * | 1993-06-24 | 1997-09-16 | United Microelectronics Corporation | Prevention of fluorine-induced gate oxide degradation in WSi polycide structure |
| WO1998059372A1 (en) * | 1997-06-20 | 1998-12-30 | Hitachi, Ltd. | Semiconductor integrated circuit and method of fabricating the same |
-
1989
- 1989-07-18 JP JP18536389A patent/JPH0350770A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5668394A (en) * | 1993-06-24 | 1997-09-16 | United Microelectronics Corporation | Prevention of fluorine-induced gate oxide degradation in WSi polycide structure |
| WO1998059372A1 (en) * | 1997-06-20 | 1998-12-30 | Hitachi, Ltd. | Semiconductor integrated circuit and method of fabricating the same |
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