JPH034538A - Bipolar transistor - Google Patents
Bipolar transistorInfo
- Publication number
- JPH034538A JPH034538A JP1139983A JP13998389A JPH034538A JP H034538 A JPH034538 A JP H034538A JP 1139983 A JP1139983 A JP 1139983A JP 13998389 A JP13998389 A JP 13998389A JP H034538 A JPH034538 A JP H034538A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- collector
- region
- mesa
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000011810 insulating material Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 16
- 230000003071 parasitic effect Effects 0.000 abstract description 11
- 239000012535 impurity Substances 0.000 abstract description 9
- 230000010354 integration Effects 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 239000002655 kraft paper Substances 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明はバイポーラ型半導体装置に関し、特に、高速論
理動作回路または、高周波領域におけるアナログ動作回
路に好適するものである。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a bipolar semiconductor device, and is particularly suitable for high-speed logic operation circuits or analog operation circuits in a high frequency region.
（従来の技術）
近年、微細加工技術の進歩によってバイポーラ型半導体
装置の高集積化が進むと共に、寄生素子の低減により高
速化がもたらされている。即ち。(Prior Art) In recent years, advances in microfabrication technology have led to higher integration of bipolar semiconductor devices, and a reduction in parasitic elements has led to higher speeds. That is.
トレンチアイソレイション（Ｔｒｅｎｃｈ ｌ５ｏｌａ
ｔｉｏｎ）により形成した素子分離領域と２層の多結晶
シリコン膜を利用した自己整合型構造が知られている。Trench isolation (Trench l5ola
A self-aligned structure is known that utilizes an element isolation region formed by ion and two layers of polycrystalline silicon film.
この構造では、ベース、エミッタ領域の縮小化によるペ
ースコレクタ間寄生容量とベース抵抗の低減更に、コレ
クタと基板間の寄生容量の低減による高速化と高集積化
が達成されている。In this structure, the base and emitter regions are reduced to reduce the parasitic capacitance between the pace collector and the base resistance, and the parasitic capacitance between the collector and the substrate is reduced, thereby achieving higher speed and higher integration.
この構造を第２図と第３図により説明する。This structure will be explained with reference to FIGS. 2 and 3.
第２図断面図に示したバイポーラ型トランジスタは、半
導体基板５０表面付近に形成してＬＯＣＯ５酸化膜５１
・・・により分離されたエピタキシャルＲ５２にトラン
ジスタ構造が、他のエピタキシャル層５３にコレクタ取
出電極５４が設置されている。The bipolar transistor shown in the cross-sectional view of FIG. 2 is formed near the surface of the semiconductor substrate 50 and
A transistor structure is provided in the epitaxial layer R52 separated by . . . , and a collector lead-out electrode 54 is provided in the other epitaxial layer 53.
Ｐ型シリコン半導体基板５０には、常法により埋込領域
５５を形成後Ｎ型エピタキシャル成長層５２゜５３を堆
積するが、埋込領域５５を構成するために導入した１０
”／ｅ１１３のｓｂは、この堆積工程時にＰ型シリコン
半導体基板５０内に拡散すると共にエピタキシャル成長
Ｎ５２．５３にオートドーピング（Ａｕｔ。After forming a buried region 55 by a conventional method, N-type epitaxial growth layers 52 and 53 are deposited on a P-type silicon semiconductor substrate 50.
sb of ``/e113 is diffused into the P-type silicon semiconductor substrate 50 during this deposition process, and auto-doped (Aut) into the epitaxially grown N52.53.
Ｄｏρｉｎｇ） シて埋込領域５５が形成される。Then, a buried region 55 is formed.
エピタキシャル成長層５２には、表面濃度（以後の不純
物濃度は全て表面濃度を意味する）が１０１＠／ｄのベ
ース領域５６を、その内部に１０”／ａＪの不純物濃度
のエミッタ領域５７が形成される。このベース領域５６
とエミッタ領域５７にまたがって設置されているのは絶
縁物層５８である。なお、ＬＯＣＯ５酸化膜５１底部に
はいわゆるチャンネルストッパ５９が設置されている。In the epitaxial growth layer 52, a base region 56 with a surface concentration (all impurity concentrations hereinafter mean surface concentration) of 101@/d is formed, and an emitter region 57 with an impurity concentration of 10''/aJ is formed inside the base region 56. .This base area 56
An insulator layer 58 is disposed across the emitter region 57 and the emitter region 57 . Note that a so-called channel stopper 59 is provided at the bottom of the LOCO5 oxide film 51.
また、第３図には、トレンチアイソレイション層を備え
たバイポーラトランジスタを示した。Further, FIG. 3 shows a bipolar transistor including a trench isolation layer.
このバイポーラトランジスタは、自己整合法を利用する
ためにドープド多結晶シリコン層６０を利用している。This bipolar transistor utilizes a doped polycrystalline silicon layer 60 to utilize a self-alignment method.
即ち、Ｐ型シリコン半導体基板６１には、Ｎ型の埋込領
域６２が上記のように形成され、更にＮ型エピタキシャ
ル成長Ｎ６３を堆積する。That is, the N-type buried region 62 is formed in the P-type silicon semiconductor substrate 61 as described above, and the N-type epitaxial growth N63 is further deposited.
この積層構造体にいわゆる島領域を形成するために、そ
の所定位置にトレンチ溝６４をＰ型シリコン半導体基板
６Ｉまで達するように設け、その内部には、多結晶シリ
コンＭ６０を埋込んでトレンチアイソレイション層６４
（トレンチ溝と便宜的に同じ番号とする）を形成する。In order to form a so-called island region in this laminated structure, a trench groove 64 is provided at a predetermined position so as to reach the P-type silicon semiconductor substrate 6I, and polycrystalline silicon M60 is buried inside the trench groove for trench isolation. layer 64
(same number as the trench groove for convenience) is formed.
図に明らかなように、トレンチアイソレイションＪ’１
６４底部には、チャンネルストッパー（Ｃｈａｎ−ｎｅ
ｌ ５ｔｏｐｐｅｒ） ６５を設置する。As shown in the figure, trench isolation J'1
At the bottom of 64, there is a channel stopper (Chan-ne
l 5topper) 65 is installed.
Ｎ型エピタキシャル成長層６３の表面には、いわゆる選
択酸化膜６６・・・を窒化珪素層を利用する常法により
エミッタ、ベース及びコレクタ引出領域形成予定位置以
外に形成後、自己整合法を利用するために、ドープド多
結晶シリコン層６７、６８を堆積する。On the surface of the N-type epitaxial growth layer 63, a so-called selective oxide film 66 is formed by a conventional method using a silicon nitride layer at locations other than the planned formation positions of the emitter, base and collector extraction regions, and then a self-alignment method is used to form the selective oxide film 66. Then, doped polycrystalline silicon layers 67 and 68 are deposited.
従って、ベース及びコレクタ形成予定位置以外に堆積し
たドープド多結晶シリコン層は例えばＲＩＥ （Ｒｅａ
ｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ）法によりパター
ニング（Ｐａｔｔｅｒｎｉｎｇ） シてから、加熱して
Ｎ型とＰ型の含有不純物をＮ型エピタキシャル成長層６
３内に拡散する。Therefore, the doped polycrystalline silicon layer deposited at locations other than where the base and collector are planned to be formed may be removed by RIE (Rea), for example.
After patterning using the active ion etching method, the N-type and P-type impurities are removed by heating to form the N-type epitaxial growth layer 6.
Diffusion within 3.
この結果、第２図のバイポーラ型トランジスタと同じ不
純物濃度のＰ型ベース６９及びＮ型コレクタ引出領域７
０が得られ、更にエミッタ７１を形成するために眉間絶
縁膜としてアンドープＣＶＤ （Ｃｈｅｍｉ−ｃａｌ
Ｖａｐｏｕｒ Ｄｅｐｏｓｉｔｉｏｎ）膜７２を堆積後
、ＲＩＥ法で形成予定位置をパターニングする。そして
、新たにドープド多結晶シリコンＨ７３も堆積、パター
ニングしてＮ型不純物をＮ型エピタキシャル成！％暦６
３内に導入してエミッタ７１を形成する。As a result, the P-type base 69 and the N-type collector lead-out region 7 have the same impurity concentration as the bipolar transistor shown in FIG.
0 was obtained, and in order to further form an emitter 71, an undoped CVD (Chemical
After depositing the (Vapour Deposition) film 72, the intended formation position is patterned by RIE method. Then, newly doped polycrystalline silicon H73 is also deposited and patterned to form N-type epitaxial layer with N-type impurities! % calendar 6
3 to form an emitter 71.
更に、エミッタ７１．ベース６９及びコレクタ引出領域
７０に電気的に接続した電極７４．７５及び７６を設置
して、バイポーラ型トランジスタを完成する。Furthermore, emitter 71. Electrodes 74, 75 and 76 electrically connected to the base 69 and the collector lead-out region 70 are provided to complete the bipolar transistor.
（発明が解決しようとする課題）
このように横型バイポーラトランジスタでは、コレクタ
の引出掃造は、いずれも真性トランジスタ領域、埋込領
域及びコレクタ引出領域を経て即ち、半導体基板の長手
方向を利用しているので、素子の縮小化を阻害している
。(Problem to be Solved by the Invention) In this way, in the lateral bipolar transistor, the collector is swept out through the intrinsic transistor region, the buried region, and the collector extraction region, that is, by using the longitudinal direction of the semiconductor substrate. This hinders device miniaturization.
本発明は、このような事情により成されたもので、横型
バイポーラ型半導体素子を微細化することにより、寄生
素子や寄生容量を低減して、高速化と高集積化を図るこ
とを目的とする。The present invention was made under these circumstances, and aims to reduce parasitic elements and parasitic capacitance by miniaturizing horizontal bipolar semiconductor elements, thereby achieving higher speed and higher integration. .
（課題を解決するための手段）
シリコン半導体基板に形成するメサ状部と、このメサ状
部を囲み半導体基板に積層して形成する＃！縁物溜及び
多結晶層と、メサ状部の頂面及び一方の側壁に形成する
クラフトベース領域と真正ベース領域と、この真正ベー
ス領域に形成し多結晶層に接続するエミッタ領域と、メ
サ状部の他方の側壁に形成され多結晶層に接続するコレ
クタ領域と、前記エミッタ領域に接続する多結晶シリコ
ン層に形成するエミッタ電極と、コレクタ領域に接続す
る多結晶シリコン層に形成するコレクタ電極と、前記ベ
ース領域に接続して形成するベース電極が、本発明に係
わるバイポーラ型半導体装置の特徴である。(Means for Solving the Problem) A mesa-shaped portion is formed on a silicon semiconductor substrate, and #! The edge material reservoir and the polycrystalline layer, the craft base region and true base region formed on the top surface and one side wall of the mesa-shaped part, the emitter region formed in this true base region and connected to the polycrystalline layer, and the mesa-shaped part a collector region formed on the other side wall of the section and connected to the polycrystalline layer; an emitter electrode formed in the polycrystalline silicon layer connected to the emitter region; and a collector electrode formed in the polycrystalline silicon layer connected to the collector region. , a base electrode formed in connection with the base region is a feature of the bipolar semiconductor device according to the present invention.
（作 用）
このように本発明では、半導体基板をいわゆるメサ状に
加工して、得られる向合った側壁にエミッタ領域とコレ
クタ領域を、頂面にグラフトベース領域を夫々形成し、
各領域には、導電性金属層からなる電極を設置する。(Function) As described above, in the present invention, a semiconductor substrate is processed into a so-called mesa shape, and an emitter region and a collector region are formed on the resulting opposing side walls, and a graft base region is formed on the top surface.
Each area is provided with an electrode made of a conductive metal layer.
この結果、バイポーラ型半導体装置の高集積化と、半導
体基板の長手方向に直行する即ち縦方向であるメサ状部
分の側壁を利用しているので、トランジスタに必要な特
性を、エミッタ領域とコレクタ領域の対向面積即ちメサ
状部の高さを調整することにより得られる他に、コレク
タ領域も横方向に引出さずに形成できるので、微細化及
び高集積化、更に高速化が達成された。As a result, bipolar semiconductor devices have become highly integrated, and since the sidewalls of the mesa-shaped portions, which are perpendicular to the longitudinal direction of the semiconductor substrate, are used, the characteristics necessary for transistors can be improved in the emitter region and collector region. In addition to adjusting the facing area of the mesa, that is, the height of the mesa-shaped portion, the collector region can also be formed without being drawn out in the lateral direction, resulting in miniaturization, high integration, and higher speed.
（実施例）
第１図ａ −ｉの断面図を参照して本発明に係わる一実
施例としてＮＰＮ トランジスタを説明する。(Embodiment) An NPN transistor will be described as an embodiment of the present invention with reference to the cross-sectional view of FIG. 1 a-i.
Ｐ型シリコン半導体基板１表面にＰを１０１５〜／ｄ程
度含有したＮ型エピタキシャル層２を成長後。After growing an N-type epitaxial layer 2 containing about 10 15 -/d of P on the surface of a P-type silicon semiconductor substrate 1 .
公知の熱酸化法により第１酸化シリコン層３を厚さＳＯ
Ｏλ〜１０００人被覆する。更に化学的気相成長法によ
り窒化シリコン層４を厚さ１０００人〜２０００人。The first silicon oxide layer 3 is reduced to a thickness of SO by a known thermal oxidation method.
Cover Oλ~1000 people. Furthermore, a silicon nitride layer 4 is formed to a thickness of 1,000 to 2,000 layers by chemical vapor deposition.
厚さ５００人〜１ｏｏｏ人の第２酸化シリコン層５を順
次堆積する。A second silicon oxide layer 5 having a thickness of 500 to 100 mm is sequentially deposited.
次に通常のりソグラフイ（Ｌｉｔｈｏｇｒａｐｈｙ）法
と反応性イオンエツチング工程により第１図ａにあるよ
うなメサ状部を形成する。勿論、これには第１酸化シリ
コン層３、窒化シリコン層４及び第２酸化シリコン層５
がこの順に形成されている。Next, a mesa-like portion as shown in FIG. 1a is formed by a conventional lithography method and a reactive ion etching process. Of course, this includes the first silicon oxide layer 3, the silicon nitride layer 4, and the second silicon oxide layer 5.
are formed in this order.
続いて、第２酸化シリコンＮ５をマスクとして５ｉＣＱ
４． ＳＦ、などの気体を用いる反応性イオンエツチン
グ工程によりＰ型シリコン半導体基板１とＮ型エピタキ
シャル層２の境界付近までを異方性エツチングして、メ
サ状部６を形成する。Next, using the second silicon oxide N5 as a mask, 5iCQ
4. A mesa-shaped portion 6 is formed by anisotropically etching up to the vicinity of the boundary between the P-type silicon semiconductor substrate 1 and the N-type epitaxial layer 2 by a reactive ion etching process using a gas such as SF.
このメサ状部６を構成する第２酸化シリコン層５をフッ
酸などにより溶除してから、減圧下における化学的気相
成長法を施し、更に、メサ状部６に堆積した窒化シリコ
ン層４をバターニングして側壁８及び頂面９だけに残し
て第１図すの断面図が得られる。After dissolving the second silicon oxide layer 5 constituting the mesa-shaped portion 6 with hydrofluoric acid or the like, a chemical vapor deposition method under reduced pressure is applied, and then a silicon nitride layer 4 deposited on the mesa-shaped portion 6 is applied. The sectional view shown in FIG. 1 is obtained by patterning and leaving only the side wall 8 and top surface 9.
更に、第１図Ｃに明らかなように窒化シリコン層４をマ
スクとした選択酸化法によりフィールド酸化物層７を形
成する。Further, as shown in FIG. 1C, field oxide layer 7 is formed by selective oxidation using silicon nitride layer 4 as a mask.
次に、第１図ｄに示すように、通常のりソゲラフイエ程
によりメサ状部６に形成した第１酸化シリコンＭ３以外
を除去後、メサ状部６の一方の側壁８と頂面１０の一部
に形成したレジスト層１０をマスクとし第１酸化シリコ
ン層３を通してイオン注入工程を行う。Next, as shown in FIG. 1d, after removing the parts other than the first silicon oxide M3 formed in the mesa-like part 6 by a normal glue-sogelation process, one side wall 8 and a part of the top surface 10 of the mesa-like part 6 are removed. An ion implantation process is performed through the first silicon oxide layer 3 using the resist layer 10 formed in the above as a mask.
５°及至１０°程度の入射角によりほう素（Ｂ）をイオ
ン注入して頂面８付近の上部が高濃度約１０１９／ｃＪ
、側面８付近は低濃度層１０”／ｃｄ程度に形成してグ
ラフトベース領域１１．低濃度層を真性ベース領域１２
とする。Boron (B) ions are implanted at an incident angle of about 5° to 10°, and the upper part near the top surface 8 has a high concentration of about 1019/cJ.
, a low concentration layer is formed in the vicinity of the side surface 8 to a thickness of about 10"/cd to form a graft base region 11. The low concentration layer is formed as an intrinsic base region 12.
shall be.
ここでフィールド酸化物層７表面にＮ型不純物例えばヒ
素を含んだ多結晶シリコン層１３をイオン注入法により
注入するかまたは、Ａｓ）１．などを混入させた化学的
気相成長法により堆積してから、エッチバック（Ｅｔｃ
ｈ Ｂａｃｋ）法により第１図ｅの形状に加工する。こ
の結果、第１酸化シリコンＲ３で覆われたメサ状部６側
壁８，９即ち真性ベース領域１２と、フィールド酸化層
７に対向してＮ型不純物例えばヒ素を含んだ多結晶シリ
コン層１３が配置される０次いで、第１酸化シリコン層
３をフッ酸などによるエツチングにより溶除してメサ状
部６の側壁８，９に隙間を形成後、ここにＮ型不純物例
えばヒ素を含んだ多結晶シリコン層１４を充填する。と
ころで、ドープド多結晶膜と単結晶シリコン膜に対する
選択性エツチング液であるフッ酸、硝酸及び酢酸の混合
液により、この多結晶シリコン層１３にエッチバック処
理を施して第１図ｆの断面構造とする。Here, a polycrystalline silicon layer 13 containing an N-type impurity such as arsenic is implanted into the surface of the field oxide layer 7 by ion implantation, or As)1. It is deposited by chemical vapor deposition method mixed with etc., and then etchback (Etc.
h Back) method to form the shape shown in Figure 1e. As a result, a polycrystalline silicon layer 13 containing an N-type impurity such as arsenic is disposed opposite to the side walls 8 and 9 of the mesa-shaped portion 6 covered with the first silicon oxide R3, that is, the intrinsic base region 12, and the field oxide layer 7. Next, after the first silicon oxide layer 3 is removed by etching with hydrofluoric acid or the like to form a gap between the side walls 8 and 9 of the mesa-shaped portion 6, polycrystalline silicon containing an N-type impurity such as arsenic is formed in the gap. Fill layer 14. By the way, this polycrystalline silicon layer 13 is etched back using a mixed solution of hydrofluoric acid, nitric acid, and acetic acid, which is a selective etching solution for the doped polycrystalline film and the single-crystalline silicon film, resulting in the cross-sectional structure shown in FIG. do.
次に、この積層構造体全表面には、化学的気相成長法に
より第２シリコン酸化物暦１６を堆積し、不活性雰囲気
で約１０００℃の熱処理工程を行って、多結晶シリコン
層１４からヒ素を拡散させて厚さ０．３μｍ程度のコレ
クタ引出部１７とエミッタ領域１８を第１図ｇにあるよ
うに形成する。夫々の濃度は、共に約１０″’／ｃｄで
ある。Next, a second silicon oxide layer 16 is deposited on the entire surface of this laminated structure by chemical vapor deposition, and a heat treatment process is performed at about 1000° C. in an inert atmosphere to form the polycrystalline silicon layer 14. By diffusing arsenic, a collector lead-out portion 17 and an emitter region 18 having a thickness of about 0.3 μm are formed as shown in FIG. 1g. The respective concentrations are both about 10''/cd.
クラフトベース領域１１、エミッタ領域１８及びコレク
タ引出部１７には導電性金属層例えばＡΩ、ＡＱ−５ｉ
またはＡρ−５ｉ−Ｃｕを蒸着もしくはスパッタリング
（Ｓｐａｔｔｅｒｉｎｇ）法により堆積して電極１９．
２０．２１を形成する（第１図り参照）。The craft base region 11, the emitter region 18 and the collector lead-out portion 17 are provided with a conductive metal layer such as AΩ, AQ-5i.
Alternatively, Aρ-5i-Cu is deposited by vapor deposition or sputtering to form the electrode 19.
20.21 (see first diagram).
この形成に当たっては、通常のリンクラフイエ程とエツ
チング工程により形成しても良いが、第１図ｉのように
反応性イオンエツチング工程により側壁８．９と多結晶
シリコン層１３間に第２シリコン酸化物層１６の一部を
残し、タングステンＷ層２２などの選択成長により電極
を形成しても差つかえない。This formation may be performed by a normal link rough etch process and an etching process, but as shown in FIG. It is also possible to leave a part of the oxide layer 16 and form the electrode by selectively growing a tungsten W layer 22 or the like.
このようにしてバイポーラ型半導体装置を完成する。な
お、最終のパッシベイション（Ｐａｓｓｉｖａ−ｔｉｏ
ｎ）層として全面にＰＳＧまたは窒化シリコン層を被覆
しても良い。In this way, a bipolar semiconductor device is completed. In addition, the final passivation (Passiva-tio
n) The entire surface may be covered with a PSG or silicon nitride layer.
本発明に係わるバイポーラ型半導体装置は、従来のよう
に半導体基板の横方向に延長した経路を持った複雑なコ
レクタ引出部が必要でないので、高集積化が可能になる
と共に、コレクタと半導体基板間の寄生容量とコレクタ
シリーズ（Ｓｅｒｉｅｓ）抵抗などの寄生素子が大幅に
減少するので、バイポーラ型半導体装置の高速動作が可
能になる。The bipolar semiconductor device according to the present invention does not require a complicated collector lead-out portion with a path extending in the lateral direction of the semiconductor substrate as in the past, so it is possible to achieve high integration, and there is Since parasitic elements such as parasitic capacitance and collector series resistance are significantly reduced, high-speed operation of the bipolar semiconductor device becomes possible.
第１図ａ−１は本発明に係わる一実施例の各工程を示す
断面図、第２図及び第３図は従来のバイポーラ型半導体
装置の断面図である。
に半導体基板、２：エピタキシャル層。
３．５．１６：酸化シリコン層、
４：窒化シリコン層、６：メタ状部、７：側壁、８：頂
面、９：フィールド酸化層。
１０ニレジスト層、１１ニゲラフトベース領域、１２：
真性ベース領域、
１３．１５：多結晶シリコン層、１４；隙間、１７：コ
レクタ引出部、１８：エミッタ領域、１９〜２１：電極
。FIG. 1a-1 is a sectional view showing each step of an embodiment of the present invention, and FIGS. 2 and 3 are sectional views of a conventional bipolar semiconductor device. 2: semiconductor substrate; 2: epitaxial layer; 3.5.16: silicon oxide layer, 4: silicon nitride layer, 6: meta-shaped part, 7: side wall, 8: top surface, 9: field oxide layer. 10 resist layers, 11 raft base regions, 12:
Intrinsic base region, 13.15: Polycrystalline silicon layer, 14: Gap, 17: Collector lead-out portion, 18: Emitter region, 19-21: Electrode.
Claims (1)
半導体基板に積層して形成する絶縁物層及び多結晶層と
、メサ状部の頂面及び一方の側壁に形成するグラフトベ
ース領域と真正ベース領域と、この真正ベース領域に形
成し多結晶層に接続するエミッタ領域と、メサ状部の他
方の側壁に形成され多結晶層に接続するコレクタ領域と
、エミッタ領域に接続する多結晶層に形成するエミッタ
電極と、コレクタ領域に接続する多結晶層に形成するコ
レクタ電極と、ベース領域に接続して形成するベース電
極を具備することを特徴とするバイポーラ型半導体装置A mesa-shaped part formed on a semiconductor substrate, an insulating material layer and a polycrystalline layer surrounding this mesa-shaped part and laminated on the semiconductor substrate, and a graft base region formed on the top surface and one sidewall of the mesa-shaped part. A true base region, an emitter region formed in this true base region and connected to the polycrystalline layer, a collector region formed on the other sidewall of the mesa-shaped portion and connected to the polycrystalline layer, and a polycrystalline layer connected to the emitter region. A bipolar semiconductor device comprising an emitter electrode formed on a polycrystalline layer, a collector electrode formed on a polycrystalline layer connected to a collector region, and a base electrode formed connected to a base region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1139983A JPH034538A (en) | 1989-06-01 | 1989-06-01 | Bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1139983A JPH034538A (en) | 1989-06-01 | 1989-06-01 | Bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH034538A true JPH034538A (en) | 1991-01-10 |
Family
ID=15258211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1139983A Pending JPH034538A (en) | 1989-06-01 | 1989-06-01 | Bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH034538A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2756974A1 (en) * | 1996-12-10 | 1998-06-12 | Sgs Thomson Microelectronics | BIPOLAR TRANSISTOR WITH INSULATION BY BOX |
| KR100251107B1 (en) * | 1997-04-29 | 2000-05-01 | 전주범 | Thin film type light-path controlling device and its fabrication method |
| US6156594A (en) * | 1996-11-19 | 2000-12-05 | Sgs-Thomson Microelectronics S.A. | Fabrication of bipolar/CMOS integrated circuits and of a capacitor |
| US6180442B1 (en) | 1996-11-19 | 2001-01-30 | Sgs-Thomson Microelectronics S.A. | Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method |
| WO2009081867A1 (en) * | 2007-12-20 | 2009-07-02 | Asahi Kasei Emd Corporation | Semiconductor device and method for manufacturing semiconductor devicedispositif à semi-conducteurrs et procédé de fabrication d'un dispositif à semi-conducteurs |
-
1989
- 1989-06-01 JP JP1139983A patent/JPH034538A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6156594A (en) * | 1996-11-19 | 2000-12-05 | Sgs-Thomson Microelectronics S.A. | Fabrication of bipolar/CMOS integrated circuits and of a capacitor |
| US6180442B1 (en) | 1996-11-19 | 2001-01-30 | Sgs-Thomson Microelectronics S.A. | Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method |
| FR2756974A1 (en) * | 1996-12-10 | 1998-06-12 | Sgs Thomson Microelectronics | BIPOLAR TRANSISTOR WITH INSULATION BY BOX |
| EP0848429A1 (en) * | 1996-12-10 | 1998-06-17 | STMicroelectronics S.A. | Bipolar transistor with pocket isolation |
| US6114743A (en) * | 1996-12-10 | 2000-09-05 | Sgs-Thomson Microelectronics S.A. | Well isolation bipolar transistor |
| US6184102B1 (en) | 1996-12-10 | 2001-02-06 | Sgs-Thomson Microelectronics S.A. | Method for manufacturing a well isolation bipolar transistor |
| US6432789B2 (en) | 1996-12-10 | 2002-08-13 | Sgs-Thomson Microelectronics S.A | Method of forming a well isolation bipolar transistor |
| KR100251107B1 (en) * | 1997-04-29 | 2000-05-01 | 전주범 | Thin film type light-path controlling device and its fabrication method |
| WO2009081867A1 (en) * | 2007-12-20 | 2009-07-02 | Asahi Kasei Emd Corporation | Semiconductor device and method for manufacturing semiconductor devicedispositif à semi-conducteurrs et procédé de fabrication d'un dispositif à semi-conducteurs |
| JP5140092B2 (en) * | 2007-12-20 | 2013-02-06 | 旭化成エレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP2013038445A (en) * | 2007-12-20 | 2013-02-21 | Asahi Kasei Electronics Co Ltd | Semiconductor device and semiconductor device manufacturing method |
| US8569866B2 (en) | 2007-12-20 | 2013-10-29 | Asahi Kasei Microdevices Corporation | Hybrid-integrated lateral bipolar transistor and CMOS transistor and method for manufacturing the same |
| US8772837B2 (en) | 2007-12-20 | 2014-07-08 | Asahi Kasei Microdevices Corporation | Semiconductor device comprising a lateral bipolar transistor |
| EP2784823A3 (en) * | 2007-12-20 | 2015-02-25 | Asahi Kasei EMD Corporation | Semiconductor device and method for manufacturing the same |
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| EP3032588A1 (en) * | 2007-12-20 | 2016-06-15 | Asahi Kasei EMD Corporation | Method for manufacturing semiconductor device |
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