JPH0342731A - Processor with verifying means - Google Patents
Processor with verifying meansInfo
- Publication number
- JPH0342731A JPH0342731A JP1178652A JP17865289A JPH0342731A JP H0342731 A JPH0342731 A JP H0342731A JP 1178652 A JP1178652 A JP 1178652A JP 17865289 A JP17865289 A JP 17865289A JP H0342731 A JPH0342731 A JP H0342731A
- Authority
- JP
- Japan
- Prior art keywords
- processing
- alus
- outputs
- alu
- discordance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012795 verification Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000010365 information processing Effects 0.000 description 1
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- Hardware Redundancy (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は処理装置の処理結果が正しいかを検証する検
証手段付き処理装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a processing device with a verification means for verifying whether the processing results of the processing device are correct.
以下に処理装置としてアリスマテツクロジックユニット
（以下ＡＬＵという）を例にして説明する。In the following, an explanation will be given of an example of an arithmetic logic unit (hereinafter referred to as ALU) as a processing device.
第２図は従来の２つのＡＬＵの出力結果を比較すること
によって、演算結果を検証する機構を持つＡＬＵ及びそ
の制御部を示すブロック図である。FIG. 2 is a block diagram showing a conventional ALU and its control unit having a mechanism for verifying calculation results by comparing the output results of two ALUs.
（１）、 （２１は、同一の機能を持つＡ Ｌ Ｕ 、
＋３１は２つのＡＬＵの出力を比較する比較装置、（
４）は２つのＡＬＵの制御装置である。(1), (21 is ALU with the same function,
+31 is a comparison device that compares the outputs of two ALUs, (
4) is a control device for two ALUs.
次に動作について説明する。ＡＬＵ（１）ｉ２１の入力
値レジスタに同一の入力値がセントされる。セットされ
た入力値を用いて、制御装置（３）によって。Next, the operation will be explained. The same input value is sent to the input value register of ALU (1) i21. by the control device (3) with the input values set.
２つのＡＬＵが同一の演算を行う。演算完了時に２つの
ＡＬＵの出力を出力ｆ直用レジスタにセットし、それぞ
れの値を比較装置（４）で比較を行い、不一致ならば、
障害発生が報告される。Two ALUs perform the same operation. When the calculation is completed, the outputs of the two ALUs are set in the output f direct register, and the respective values are compared by the comparator (4). If they do not match,
A failure is reported.
従来のＡＬＵは以上のように構成されているので、障害
発生の原因が、ＡＬＵ内の遅延によるものか、ＡＬＵ内
又は制御装置の論理的な障害が発生したのかの判別が不
可能であり、演算結果の不一致発生時には、障害発生を
報告する動作のみ行っていた。Since the conventional ALU is configured as described above, it is impossible to determine whether the cause of the failure is due to a delay within the ALU or a logical failure within the ALU or the control device. When a discrepancy occurs in the calculation results, only the operation to report the occurrence of a failure is performed.
この発明は、上記のような問題点を解消するためになさ
れたもので、処理結果の不一致発生の原因の判別を可能
とし、処理装置内の遅延がその原因ならば、一定時間の
後に正し−処理結果を得ることが可能となる検証手段付
き処理装置を得ることを目的とする。This invention was made to solve the above-mentioned problems, and it is possible to determine the cause of discrepancies in processing results, and if the cause is a delay within the processing device, it can be corrected after a certain period of time. - The object is to obtain a processing device with a verification means that makes it possible to obtain processing results.
この発明に係る検証手段付き処理装置の出力が不一致の
場合、一定時間の後、再び出力の比較を行うことしたも
のである。If the outputs of the processing device with verification means according to the present invention do not match, the outputs are compared again after a certain period of time.
この発明について、２つの処理装置の出力が不一致とな
った原因が一方の処理装置内の処理遅延によるならば、
一定時間後玉しい処理結果を得ることが可能となシ、障
害発生の原因も判別可能となる。Regarding this invention, if the cause of the mismatch between the outputs of two processing devices is a processing delay within one processing device, then
It is possible to obtain a satisfactory processing result after a certain period of time, and it is also possible to determine the cause of the failure.
以下、この発明の一実姑例をＡＬＵの場合について説明
する。Hereinafter, a practical example of the present invention will be described in the case of an ALU.
第１図にかいて、、（１１，＋２１は、同一の機能を持
つＡＬＵ、＋３＋は２つのＡＬＵＯ出力を比較する比較
装置、（４）は２つのＡＬＵの１ｉｊｌＪ御装置、（５
）は障害発生時にその原因金利別する為の判別装置であ
る。In Fig. 1, (11 and +21 are ALUs with the same function, +3+ is a comparison device that compares the two ALUO outputs, (4) is the 1ijlJ control device of the two ALUs, (5
) is a discrimination device for classifying the cause of a failure when it occurs.
Ａ Ｌ Ｕ （１） 、 ＋２１の入力値レジスタに同
一の入力値がセットされる。七ッ：・さ几た入力値を用
いて。The same input value is set in the input value registers of ALU (1) and +21. 7:・Using the input values.
制御装置（３）によって２つのＡ Ｌ Ｕが、同一の演
算を行う。演算完了時に２つのｋ Ｌ Ｕの出力を出力
値用レジスタにセットし、それぞれの値を比較装置（４
）で比較を行い、不一致ならば判別装置（５）によって
、制御装置がホールドされ９次の演算を停止される。そ
して、一定時間経過後、再び２つのＡ Ｌ ｔＪの出力
を比較する。The two ALUs perform the same calculation by the control device (3). When the calculation is completed, the outputs of the two kL U are set in the output value register, and each value is transferred to the comparator (4
), and if they do not match, the control device is held by the discriminating device (5) and the ninth-order calculation is stopped. Then, after a certain period of time has elapsed, the outputs of the two A L tJs are compared again.
その結果、２つのＡＬＵの出刃が一致していたならば、
一方のＡＬＵ内の遅延が、前回演算結果不一致の原因で
あると判定１−１その報告を行う。As a result, if the blades of the two ALUs match,
Determination 1-1 that the delay in one ALU is the cause of the mismatch in the previous calculation result is reported.
以上のように、この実施例は、入カ値金共有する２つの
独立したＡＬＵの出力を比較し、演算結果を検証する手
段を持つＡＬＵにかいて、２つの演算結果が不一致の場
合には、ＡＬＵの制御手段を一定時間ホールドさせた後
、再び演算結果を比較することによって、ＡＬＵ内の遅
延によって発生した不一致かを判別することを可能とし
、遅延による障害発生時には２度目の比較の結果、正し
い演算結果が得られることを可能としたものである。As described above, this embodiment compares the outputs of two independent ALUs that share an input value, and uses an ALU that has a means to verify the calculation results, and when the two calculation results do not match, By holding the ALU control means for a certain period of time and then comparing the calculation results again, it is possible to determine whether the discrepancy is caused by a delay within the ALU, and if a failure occurs due to the delay, the results of the second comparison can be compared. , it is possible to obtain correct calculation results.
なお、上記実施例では、障害発生の原因を判別するのみ
であるが、一定時間の制御装置のホールドの後、正しい
値を得たならば、その後、正常動作を続行することも可
能である。In the above embodiment, only the cause of the failure is determined, but if a correct value is obtained after holding the control device for a certain period of time, normal operation can be continued.
また、上記実施例では、処理装置がＡＬＵの場合を示し
たが、加算器、減算器１乗算器、除算器。Further, in the above embodiment, the processing device is an ALU, but an adder, a subtracter, a multiplier, and a divider.
カウンタなどの処理装置でもよい。また、制御装置、計
算機、情報処理装置などの処理装置であってもよい。さ
らに、同一処理を同一時期に行ない。It may be a processing device such as a counter. Further, it may be a processing device such as a control device, a computer, or an information processing device. Furthermore, the same processing is performed at the same time.
処理結果が比較できるような処理装置であれば。As long as it is a processing device whose processing results can be compared.
どのような処理装置でもよい。Any processing device may be used.
以上のように、この発明によれば障害発生の原因が判別
出来、その後、正しい処理結果を得て。As described above, according to the present invention, the cause of the failure can be determined and correct processing results can then be obtained.
処理を続行できるという効果がある。This has the effect of allowing processing to continue.
第１図は１本発明の一実施例を示すブロック図第２図は
、従来のＡＬＵを示すブロック図（１１・・・ＡＬＵ
（２）・・・ＡＬＵ
（３）・・・比較装置
（４）・・・制御装置
（５）・・・判別装置FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing a conventional ALU (11...ALU (2)...ALU (3)...comparison device (4). )...Control device (5)...Discrimination device
Claims (1)
時期に行なわせる制御手段。 （ｃ）以下の要素を有する検証手段。 （ｃ１）上記（ｂ）の制御手段により同一処理を同一時
期に行なつた複数の処理装置の処理結果を比較する比較
手段。 （ｃ２）上記（ｃ１）の比較手段により複数の処理装置
の処理結果が異なるとき、所定 の時間後に処理結果を再比較する判別 手段。[Scope of Claims] A processing device with verification means having the following elements: (a) a plurality of processing means that independently perform processing; (b) Control means for causing the plurality of processing means in (a) above to perform the same processing at the same time. (c) Verification means having the following elements: (c1) Comparison means for comparing the processing results of a plurality of processing apparatuses performing the same processing at the same time using the control means of (b) above. (c2) Discrimination means for re-comparing the processing results after a predetermined period of time when the processing results of the plurality of processing devices differ according to the comparison means (c1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1178652A JPH0342731A (en) | 1989-07-11 | 1989-07-11 | Processor with verifying means |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1178652A JPH0342731A (en) | 1989-07-11 | 1989-07-11 | Processor with verifying means |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0342731A true JPH0342731A (en) | 1991-02-22 |
Family
ID=16052210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1178652A Pending JPH0342731A (en) | 1989-07-11 | 1989-07-11 | Processor with verifying means |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0342731A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003096722A (en) * | 2001-09-26 | 2003-04-03 | Fde:Kk | Road sign cover |
-
1989
- 1989-07-11 JP JP1178652A patent/JPH0342731A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003096722A (en) * | 2001-09-26 | 2003-04-03 | Fde:Kk | Road sign cover |
| JP4693312B2 (en) * | 2001-09-26 | 2011-06-01 | 西日本高速道路エンジニアリング九州株式会社 | Road sign cover |
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