JPH0341748A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0341748A JPH0341748A JP17555489A JP17555489A JPH0341748A JP H0341748 A JPH0341748 A JP H0341748A JP 17555489 A JP17555489 A JP 17555489A JP 17555489 A JP17555489 A JP 17555489A JP H0341748 A JPH0341748 A JP H0341748A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- element region
- groove
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 11
- 238000005530 etching Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000007788 liquid Substances 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） この発明は、誘電体分離構造の半導体装置に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a semiconductor device having a dielectric isolation structure.
（従来の技術）
従来の誘電体分離構造の半導体装置としては、例えば第
４図に示すようなものがある（ＩＥＤＭＴｅｃｈｎｉｃ
ａｌ Ｄｌ、ｇｅｓｔ 、 ｐ、 ７２８〜７３
１（１９８５）） 。(Prior Art) As an example of a conventional semiconductor device having a dielectric isolation structure, there is a device as shown in FIG.
al Dl, gest, p, 728-73
1 (1985)).
同図中、２１は基体領域となる多結晶Ｓｉであり、多結
晶５ｉ２１上には、５ｉ０２膜２２で誘電体分離された
ｎ−形の素子領域２３が形成されている。素子領域２３
には、５ｉ０２膜２２に沿ってｎ＋埋込層２４が形成さ
れている。また、素子領域２３には、そのｎ−形の素子
領域２３をコレクタ領域として、ｐ形ベース領域２５、
ｎ＋エミッタ領域２６及びｎ１コレクタコンタクト領域
２７等によりｎｐｎ形のバイポーラトランジスタが形成
されている。前記のｎ＋埋込層２４により、バイポーラ
トランジスタのコレクタ抵抗が低減されている。２８は
５ｉ０２膜、２つはＡｕ電極である。In the figure, 21 is a polycrystalline Si serving as a base region, and an n-type element region 23 dielectrically isolated by a 5i02 film 22 is formed on the polycrystalline 5i21. Element area 23
An n+ buried layer 24 is formed along the 5i02 film 22. The element region 23 also includes a p-type base region 25, with the n-type element region 23 as a collector region.
An npn type bipolar transistor is formed by the n+ emitter region 26, the n1 collector contact region 27, and the like. The collector resistance of the bipolar transistor is reduced by the n+ buried layer 24. 28 is a 5i02 film, and two are Au electrodes.
上述の半導体装置の製造方法としては、まず、単結晶の
Ｓｔ基板をＶ形エツチングして満を作り、ｎ＋埋込層２
４形戊のためのｎ＋拡散及び誘電体分離用の５ｉ０２膜
２２の形成が行われる。次いで、５ｉ０２膜２２上に多
結晶５ｉ２１が厚く堆積される。その後、他の基板等に
接着されてＳｉ基板が裏面から削られ、多結晶５ｉ２１
上に、ｎ＋埋込層２４を有する単結晶Ｓｔの素子領域２
３が残される。このあと、素子領域２３内に素子形成の
ための各領域が作り込まれる。As a method for manufacturing the above-mentioned semiconductor device, first, a V-shaped etching is performed on a single crystal St substrate, and an n+ buried layer 2 is formed.
Formation of a 5i02 film 22 for n+ diffusion and dielectric isolation for the 4-type film is performed. Next, polycrystalline 5i21 is deposited thickly on the 5i02 film 22. After that, the Si substrate is bonded to another substrate, etc., and the back surface of the Si substrate is shaved, and the polycrystalline 5i21
Above, a single crystal St element region 2 having an n+ buried layer 24
3 is left. After this, each region for forming elements is created in the element region 23.
（発明が解決しようとする課題）
従来の誘電体分離構造の半導体装置は、Ｓｔ基板を裏面
から削って多結晶ＳＬ上に単結晶Ｓｉの素子領域を残す
ような工程を必要とするため、そのＳｔ基板のラッピン
グ工程には大変な時間がかかり、また全般的に工程が複
雑でプロセスコストが高くなり、ひいてはチップコスト
が高くなるという問題があった。(Problems to be Solved by the Invention) Conventional semiconductor devices with a dielectric isolation structure require a step of scraping the back surface of the St substrate to leave a single-crystal Si element region on the polycrystalline SL. The lapping process of the St substrate takes a lot of time, and the overall process is complicated, resulting in high process costs and, in turn, high chip costs.
そこで、この発明は、製造が比較的容易で、チップコス
トを低減することのできる半導体装置を提供することを
目的とする。Therefore, an object of the present invention is to provide a semiconductor device that is relatively easy to manufacture and can reduce chip cost.
［発明の構成］
（課題を解決するための手段）
この発明は上記課題を解決するために、半導体基板の主
面に当該半導体基板から切離して形成され素子が作り込
まれる素子領域と、該素子領域を取囲むように形成され
内面に絶縁膜が形成された満と、該溝に埋込まれ前記素
子領域と同−導電形で且つ当該素子領域よりも高不純物
濃度の多結晶又は非晶質の半導体からなる埋込領域とを
有することを要旨とする。[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention provides an element region that is formed on the main surface of a semiconductor substrate by being separated from the semiconductor substrate and in which elements are built in, and A polycrystalline or amorphous material is formed to surround the region and has an insulating film formed on the inner surface, and a polycrystalline or amorphous material is buried in the trench and has the same conductivity type as the element region and has a higher impurity concentration than the element region. The gist is that the buried region is made of a semiconductor.
（作用）
半導体装置は次のようにして形成することができる。即
ち、半導体基板の主面に溝が掘られて当該半導体基板か
ら切離された素子領域が形成される。その溝には、内面
に絶縁膜が形成された後、素子領域と同−導電形で且つ
高不純物濃度の多結晶又は非晶質の半導体が埋込まれ、
埋込領域が形成される。したがって、基板裏面からのラ
ッピング工程等を用いずに、溝の内面に形成された絶縁
膜により誘電体分離構造が実現される。そして素子領域
を取囲むように形成された埋込領域は、低抵抗埋込領域
として機能する。(Operation) A semiconductor device can be formed as follows. That is, a groove is dug in the main surface of the semiconductor substrate to form an element region separated from the semiconductor substrate. After an insulating film is formed on the inner surface of the groove, a polycrystalline or amorphous semiconductor having the same conductivity type as the element region and having a high impurity concentration is buried.
A buried region is formed. Therefore, a dielectric isolation structure is realized by the insulating film formed on the inner surface of the groove without using a lapping process from the back surface of the substrate. The buried region formed to surround the element region functions as a low-resistance buried region.
（実施例）
以下、この発明の実施例を第１図ないし第３図に基づい
て説明する。この実施例は、素子領域にバイポーラトラ
ンジスタが形成された半導体装置を示している。(Example) Hereinafter, an example of the present invention will be described based on FIGS. 1 to 3. This embodiment shows a semiconductor device in which a bipolar transistor is formed in an element region.
まず、半導体装置の構成を説明すると、第１図中、１は
半導体基板としてのｐ形Ｓｔ基板であり、その主面には
、当該Ｓｔ基板１から切離して形成されるとともに、ｎ
−形にドープされた素子領域２が形成されている。素子
領域２は、断面が逆三角形に形成され、これを取囲むよ
うに、断面が菱形を２個連ねたような形状の溝が形成さ
れている。First, to explain the structure of the semiconductor device, in FIG. 1, reference numeral 1 is a p-type St substrate as a semiconductor substrate.
A --shaped doped component region 2 is formed. The element region 2 has an inverted triangular cross section, and a groove having a cross section shaped like two rhomboids connected in a row is formed so as to surround this.
溝の内面には、誘電体分離用の絶縁膜としてのＳ ｉ
０２膜３が形成され、さらにその溝内にはｎ＋形にドー
プされた多結晶Ｓｉ又は非晶質Ｓｔが埋込まれて埋込領
域４が形成されている。The inner surface of the groove is coated with Si as an insulating film for dielectric isolation.
02 film 3 is formed, and further, n+ type doped polycrystalline Si or amorphous St is buried in the trench to form a buried region 4.
素子領域２には、そのｎ−形の素子領域２をコレクタ領
域として、ｐ形ベース領域５及びｎ＋エミッタ領域６等
によりｎｐｎ形のバイポーラトランジスタが形成されて
いる。７は５ｉ０２膜、８ａはエミッタ電極、８ｂはベ
ース電極であり、コレクタ電極８ｃは埋込領域４の部分
からとられている。In the element region 2, an npn type bipolar transistor is formed using the n- type element region 2 as a collector region, a p-type base region 5, an n+ emitter region 6, and the like. 7 is a 5i02 film, 8a is an emitter electrode, 8b is a base electrode, and the collector electrode 8c is taken from the buried region 4.
半導体装置は上述のように構成されているので、後述す
る製造方法でさらに明らかなように基板裏面からのラッ
ピング工程等を用いずに、溝の内面に形成された５ｉ０
２膜３により誘電体分離構造の実現が可能となる。また
、ｎ＋形の埋込領域４により、バイポーラトランジスタ
のコレクタ抵抗が低減される。Since the semiconductor device is configured as described above, the 5i0 is formed on the inner surface of the groove without using a lapping process from the back side of the substrate, as will be clear from the manufacturing method described later.
The two films 3 make it possible to realize a dielectric isolation structure. Furthermore, the collector resistance of the bipolar transistor is reduced by the n+ type buried region 4.
次に、第２図及び第３図を用いて、この実施例に係る半
導体装置の製造方法の一例を説明する。Next, an example of a method for manufacturing a semiconductor device according to this embodiment will be explained using FIGS. 2 and 3.
なお、以下の説明において、（ａ）〜（Ｃ）の各項目記
号は、第２図の（ａ）〜（Ｃ）のそれぞれに対応する。In the following description, each item symbol (a) to (C) corresponds to (a) to (C) in FIG. 2, respectively.
（ａ） （１００）面のｐ形Ｓｔ基板１の主面に選択
拡散により、素子領域となるｎ−領域、ｐ形ベース領域
５及びｎ１エミツタ領域６を形成する。(a) An n- region, a p-type base region 5, and an n1 emitter region 6, which will become an element region, are formed on the main surface of a p-type St substrate 1 having a (100) plane by selective diffusion.
（ｂ） 素子領域となる部分の両側に、反応性イオン
エツチングにより縦溝１１を掘る。(b) Vertical grooves 11 are dug by reactive ion etching on both sides of the portion that will become the element region.
（Ｃ） 縦溝１１の内壁をヒドラジンやエチレンジア
ミン等のアルカリ系異方性エツチング液を用いてエツチ
ングする。アルカリ系異方性エツチング液でＳＬを、エ
ツチングすると（１１１）面で著しくエッチレートが遅
くなるので、（１１１）面が露出したところでエツチン
グが止り、三角柱状で両持梁構造の素子領域となる部分
が形成され、これとともに断面が菱形を２個連ねたよう
な形状の溝１２が形成される。次いでｐ形Ｓｉ基板１を
正にバイアスして溝１２の内面を陽極酸化し、誘電体分
離用の５ｉ０２膜３を形成する。ここで両持梁の付は根
の部分は、第３図に示すように、予めｐ／ｎ−／ｐ／ｎ
−の構造にしておき、素子領域となる部分には正のバイ
アスがかからないようにして、その底面は酸化されない
ようにする。(C) The inner wall of the vertical groove 11 is etched using an alkaline anisotropic etching solution such as hydrazine or ethylenediamine. When the SL is etched with an alkaline anisotropic etching solution, the etch rate is significantly slow on the (111) plane, so etching stops when the (111) plane is exposed, resulting in a triangular prism-shaped element region with a double-supported beam structure. A groove 12 having a cross section shaped like two rhomboids connected in a row is also formed. Next, the p-type Si substrate 1 is positively biased and the inner surface of the groove 12 is anodized to form a 5i02 film 3 for dielectric isolation. Here, the root part of the support beam is set in advance as p/n-/p/n, as shown in Figure 3.
- structure, so that no positive bias is applied to the part that will become the element region, and the bottom surface is not oxidized.
この後、溝１２にｎ＋形にドープされた多結晶Ｓｉ又は
非晶質Ｓｉを充填して埋込領域４を形成する。次いで、
両持梁の付は根の部分を反応性イオンエツチングでエツ
チングして５ｉ０２等の誘電体で埋め、素子領域２をＳ
ｉ基板１から完全に誘電体分離する。最後に、コンタク
ト孔の孔開は及びＡｉＪＩＩによる各電極８ａｓ ８ｂ
ｓ ８Ｃ（７）形成等を行なって半導体装置を完成する
。Thereafter, the buried region 4 is formed by filling the groove 12 with n+ type doped polycrystalline Si or amorphous Si. Then,
At the base of the support beam, the roots are etched using reactive ion etching and filled with a dielectric material such as 5i02, and the element area 2 is etched with S.
Completely dielectrically separated from the i-substrate 1. Finally, the contact hole is opened and each electrode 8as 8b by AiJII.
A semiconductor device is completed by performing s8C(7) formation and the like.
［発明の効果］
以上説明したように、この発明によれば、半導体基板の
主面に素子領域を取囲むように満を形成し、この満の内
面に絶縁膜を形成した後、素子領域と同−導電形で且つ
高不純物濃度の多結晶又は非晶質の半導体を埋込んで埋
込領域を形成するような構成としたため、基板裏面から
のラッピング工程等を用いずに溝の内面に形成した絶縁
膜により誘電体分離構造を実現することができる。した
がって製造が比較的容易になってチップコストを低減す
ることができる。[Effects of the Invention] As explained above, according to the present invention, a hole is formed on the main surface of a semiconductor substrate so as to surround an element region, and after an insulating film is formed on the inner surface of this hole, the element region and Since the structure is such that the buried region is formed by burying a polycrystalline or amorphous semiconductor of the same conductivity type and high impurity concentration, it can be formed on the inner surface of the groove without using a lapping process from the back side of the substrate. A dielectric isolation structure can be realized using the insulating film. Therefore, manufacturing becomes relatively easy and chip cost can be reduced.
第１図はこの発明に係る半導体装置の実施例を示す縦断
面図、第２図及び第３図は同上実施例の製造方法の一例
を示す工程図、第４図は従来の半導体装置を示す縦断面
図である。
１ ；Ｓｉ基板（半導体基板）、 ２；素子領域、３：
５ｉ０２膜（絶縁膜）、 ４：埋込領域、１２：溝。FIG. 1 is a vertical cross-sectional view showing an embodiment of a semiconductor device according to the present invention, FIGS. 2 and 3 are process diagrams showing an example of a manufacturing method of the same embodiment, and FIG. 4 shows a conventional semiconductor device. FIG. 1; Si substrate (semiconductor substrate), 2; element region, 3:
5i02 film (insulating film), 4: buried region, 12: groove.
Claims (1)
れ素子が作り込まれる素子領域と、該素子領域を取囲む
ように形成され内面に絶縁膜が形成された溝と、該溝に
埋込まれ前記素子領域と同一導電形で且つ当該素子領域
よりも高不純物濃度の多結晶又は非晶質の半導体からな
る埋込領域とを有することを特徴とする半導体装置。An element region formed on the main surface of a semiconductor substrate separately from the semiconductor substrate and in which an element is built, a groove formed to surround the element area and having an insulating film formed on the inner surface, and a groove embedded in the groove. A semiconductor device comprising a buried region made of a polycrystalline or amorphous semiconductor having the same conductivity type as the element region and having a higher impurity concentration than the element region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1175554A JP2803187B2 (en) | 1989-07-10 | 1989-07-10 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1175554A JP2803187B2 (en) | 1989-07-10 | 1989-07-10 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0341748A true JPH0341748A (en) | 1991-02-22 |
| JP2803187B2 JP2803187B2 (en) | 1998-09-24 |
Family
ID=15998114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1175554A Expired - Fee Related JP2803187B2 (en) | 1989-07-10 | 1989-07-10 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2803187B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5405454A (en) * | 1992-03-19 | 1995-04-11 | Matsushita Electric Industrial Co., Ltd. | Electrically insulated silicon structure and producing method therefor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6325247A (en) * | 1986-07-17 | 1988-02-02 | Matsushita Electric Ind Co Ltd | Glass for sealing |
| JPS63147367A (en) * | 1986-12-11 | 1988-06-20 | Toshiba Corp | Semiconductor device |
| JPH01187855A (en) * | 1988-01-22 | 1989-07-27 | Hitachi Ltd | Semiconductor device |
-
1989
- 1989-07-10 JP JP1175554A patent/JP2803187B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6325247A (en) * | 1986-07-17 | 1988-02-02 | Matsushita Electric Ind Co Ltd | Glass for sealing |
| JPS63147367A (en) * | 1986-12-11 | 1988-06-20 | Toshiba Corp | Semiconductor device |
| JPH01187855A (en) * | 1988-01-22 | 1989-07-27 | Hitachi Ltd | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5405454A (en) * | 1992-03-19 | 1995-04-11 | Matsushita Electric Industrial Co., Ltd. | Electrically insulated silicon structure and producing method therefor |
| US5543351A (en) * | 1992-03-19 | 1996-08-06 | Matsushita Electric Industrial Co., Ltd. | Method of producing electrically insulated silicon structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2803187B2 (en) | 1998-09-24 |
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| JPH04159719A (en) | Manufacture of semiconductor device | |
| JPH0236584A (en) | Optoelectronic integrated circuit and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |