JPH0334358A - Manufacture of resin sealed semiconductor device - Google Patents
Manufacture of resin sealed semiconductor deviceInfo
- Publication number
- JPH0334358A JPH0334358A JP1169501A JP16950189A JPH0334358A JP H0334358 A JPH0334358 A JP H0334358A JP 1169501 A JP1169501 A JP 1169501A JP 16950189 A JP16950189 A JP 16950189A JP H0334358 A JPH0334358 A JP H0334358A
- Authority
- JP
- Japan
- Prior art keywords
- outer leads
- heat resistant
- leads
- resin
- cut
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229920005989 resin Polymers 0.000 title claims abstract description 13
- 239000011347 resin Substances 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000012360 testing method Methods 0.000 claims abstract description 12
- 229920006015 heat resistant resin Polymers 0.000 claims abstract description 6
- 238000000465 moulding Methods 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 230000002950 deficient Effects 0.000 abstract description 4
- 238000005452 bending Methods 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 230000003442 weekly effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a resin-sealed semiconductor device.
一般に、ＱＥＰやＳＯＰと呼ばれるガルウィング状の外
部リードを有する樹脂封止型のＴＣの組立工程において
は、第７図に示すように、リードフレームｊ上にマウン
ト、ポンディングされた半導体チップを樹脂封止した後
、樹脂ダム部７及びダイパ一部６を切断除去し、外部リ
ード３に半田メツキを施している。Generally, in the assembly process of a resin-sealed TC with gull-wing external leads called QEP or SOP, a semiconductor chip mounted and bonded on a lead frame is resin-sealed, as shown in Figure 7. After stopping, the resin dam part 7 and the dieper part 6 are cut and removed, and the external leads 3 are soldered.
従来、その後工程としては、第８図に示すように、外部
リード３の先端部を切断し、外部リード３をガルウィン
グ状に成形後、封止パッケージ２をリードフレーム１に
連結支持している吊りリード５の切断を行なって、第９
図に示すようなガルウィング状の外部リード３を有する
個片のパッケージに分離した状態にて電気特性試験を行
なっている。Conventionally, subsequent steps include cutting the tips of the external leads 3, forming the external leads 3 into a gullwing shape, and then forming a suspension that connects and supports the sealed package 2 to the lead frame 1, as shown in FIG. After cutting lead 5,
Electrical property tests were conducted on the package separated into individual pieces having gull-wing external leads 3 as shown in the figure.
上述した従来のＩＣの組立方法では、外部リードを切断
、成形した後電気特性試験を行なうため、試験時に外部
リードに何回か直接接触するコンタクト端子により外部
リードが変形することがあり、更にＩＣはリードフレー
ムより分離されて個片状態にて選別工程を流れるため、
ハンドリング時に外部リードの変形が発生し易く、外部
リードの横曲がりや先端の浮きが生じＱＥＰやＳＯＰの
ような表面実装型ＩＣに重要な外部リードの平坦性（以
下コブラナリティと記す）が損なわれるという欠点があ
る。In the conventional IC assembly method described above, an electrical property test is performed after cutting and molding the external leads, so the external leads may be deformed due to contact terminals that come into direct contact with the external leads several times during the test, and furthermore, the IC is separated from the lead frame and goes through the sorting process as individual pieces.
External leads are easily deformed during handling, causing sideways bending and lifting of the tips, which impairs the flatness of external leads (hereinafter referred to as coplanarity), which is important for surface mount ICs such as QEP and SOP. There is a drawback.
特に、近年、高密度実装の要求により更に多ピン化、小
型化をはかるため、外部リードのファインピッチ化が進
み、リード間ピッチが０．６５ｍｍ以下のＩＣが増加す
る傾向にあり、ブリット基板上にスクリーン印刷する際
の半田ペースト厚は半田ブリッジを防止するため薄くせ
ざるを得す、半田付は性を向上するためにコブラナリテ
ィは０６１ｍｍ以下が必要であり、ファインピッチ化に
より更に小さな値に押えていく必要がある。In particular, in recent years, in order to increase the number of pins and reduce the size due to the demand for high-density packaging, the pitch of external leads has become finer, and the number of ICs with a lead-to-lead pitch of 0.65 mm or less is increasing. The thickness of the solder paste when screen printing must be made thinner to prevent solder bridges, and the coplanarity must be less than 0.61mm to improve soldering properties, and finer pitch will reduce this value even further. I need to hold it down.
又、外部リードの強度もファインピッチ化に伴ない、リ
ード幅が小さくなるため従来に比較して弱くなる傾向に
あり、外部からの接触に対して容易にリード変形を起こ
し易く、益々外部リードの横曲がりやコプラナリティ悪
化を招き、電気特性試験後の外部りの横曲がりやコプラ
ナリティの検査及び修正に多大な工数を費やすという問
題がある。In addition, the strength of the external leads tends to be weaker than before because the lead width becomes smaller as the pitch becomes finer, and the leads easily deform due to contact from the outside, making the external leads increasingly weaker. There is a problem in that it causes lateral bending and deterioration of coplanarity, and a large amount of man-hours are required to inspect and correct the lateral bending and coplanarity on the outside after the electrical property test.
本発明の樹脂封止型半導体装置の製造方法は、リードフ
レームに半導体チップを固着し、結線し、樹脂封止した
後のリードフレームの外部リードに絶縁性を有する耐熱
薄板を耐熱樹脂にて接着して連結した状態にて外部リー
ドの先端を切断し、リードフレーム状にて電気的特性試
験を行なった後、外部ｆノードの成形及び前記耐熱薄板
を含む外部リードを切断、除去することを特徴とする。The method for manufacturing a resin-sealed semiconductor device of the present invention involves bonding an insulating heat-resistant thin plate to the external leads of the lead frame using a heat-resistant resin after fixing a semiconductor chip to a lead frame, connecting wires, and sealing with resin. The tip of the external lead is cut in the connected state, and after conducting an electrical characteristic test in the form of a lead frame, the external f-node is formed and the external lead including the heat-resistant thin plate is cut and removed. shall be.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例である絶縁耐熱薄板を接
着した状態のリードフレームの平面図、第２図は外部リ
ード先端を切断した状態のリードフレームの平面図、第
３図は外部リードの成形を行なったＩＣの斜視図、第４
図は絶縁耐熱薄板を切断除去した後のＩＣの斜視図であ
る。FIG. 1 is a plan view of a lead frame with an insulating heat-resistant thin plate adhered thereto according to the first embodiment of the present invention, FIG. 2 is a plan view of the lead frame with the external lead tips cut off, and FIG. Perspective view of IC with external leads molded, No. 4
The figure is a perspective view of the IC after cutting and removing the insulating heat-resistant thin plate.
まず、第１図に示すように樹脂封止を行なったリードフ
レーム１において、外部リード３上に各辺ごとに該外部
リード３を連結するようにポリイシド等の絶縁性を有す
る耐熱薄板４を耐熱樹脂により接着する。樹脂ダム部７
及びダイパ一部６を切断除去し、外部リード３の表面に
半田メツキを施した後、第２図に示すように、絶縁耐熱
薄板４より外側に位置する外部リード３をある一定幅に
て切断し、リードフレーム１より分離する。この際、外
部リード３は各辺ごとに絶縁耐熱薄板４のみにて連結支
持された状態となる。封止パッケージ２は各コーナに設
けられた吊りリード５のみによりリードフレーム１に連
結支持されており、この状態にて外部リード３にコンタ
クト端子を接触させ電気的特性試験を行ない良品、不良
品に選別する。良品のＩＣにおいては、第３図に示すよ
うに、外部リード３を絶縁耐熱薄板４にて連結した状態
にてガルウィング状に成形し、最後に外部リード３の先
端部を切断して絶縁耐熱薄板４を除去し、第４図に示す
ような所望の寸法及び形状を得る。First, as shown in FIG. 1, in a resin-sealed lead frame 1, heat-resistant thin plates 4 made of insulating material such as polyamide are placed on the external leads 3 on each side to connect the external leads 3. Adhesive with resin. Resin dam part 7
After cutting and removing the dieper part 6 and applying solder plating to the surface of the external lead 3, the external lead 3 located outside the insulating heat-resistant thin plate 4 is cut to a certain width as shown in FIG. Then, it is separated from the lead frame 1. At this time, the external leads 3 are connected and supported only by the insulating heat-resistant thin plates 4 on each side. The sealed package 2 is connected and supported to the lead frame 1 only by the hanging leads 5 provided at each corner. In this state, contact terminals are brought into contact with the external leads 3 and an electrical characteristic test is conducted to determine whether the product is good or defective. Select. In a good IC, as shown in Fig. 3, the external leads 3 are connected by an insulating and heat-resistant thin plate 4 and formed into a gullwing shape, and finally the tips of the external leads 3 are cut to form an insulating and heat-resistant thin plate. 4 to obtain the desired dimensions and shape as shown in FIG.
本発明においては、ＩＣを絶縁耐熱薄板にて各辺ごとの
外部リードを常に連結支持した状態にて、電気的特性試
験及びリード成形の様に直接外部リードに接触する際に
リード変形を発生させていた工程を流すことにより工程
中のリード曲がりや外部リード先端のばらつきを防止で
き、コブラナリティ等の向上により実装時の安定性の向
上を図ることができる。第５図は本発明の第２の実施例
である絶縁耐熱薄板を接着した状態のリードフレームの
平面図、第６図は外部リード先端を切断した状態のリー
ドフレームの平面図である。In the present invention, the external leads of each side of the IC are always connected and supported by an insulating heat-resistant thin plate, and the leads are deformed when they are brought into direct contact with the external leads, such as during electrical property tests and lead forming. By repeating the previous process, lead bending during the process and variations in the tips of external leads can be prevented, and stability during mounting can be improved by improving coplanarity. FIG. 5 is a plan view of a lead frame with an insulating heat-resistant thin plate adhered thereto according to a second embodiment of the present invention, and FIG. 6 is a plan view of the lead frame with external lead tips cut off.
第２の実施例においては、樹脂封止後のリードフレーム
１の外部リード３上に四角の枠状の絶縁耐熱薄板８を耐
熱樹脂により接着固定する。樹脂ダム部７及びダイパ一
部６を切断除去し、外部リード３の表面に半田メツキを
施した後、第６図に示すように、外部リード３の先端部
を切断した状態にて電気的特性試験を行なう。この場合
は、絶縁耐熱薄板８が各辺の外部リード３のみでなく、
リードフレームｌ上にも接着固定されているため、外部
リード３は横方向、上下方向共しっかりと固定されてお
り、工程中のいかなる外部リード３への接触に対しても
変形を防止できるという利点がある。In the second embodiment, a rectangular frame-shaped insulating heat-resistant thin plate 8 is adhesively fixed with heat-resistant resin onto the external leads 3 of the lead frame 1 after resin sealing. After cutting and removing the resin dam part 7 and the dieper part 6 and applying solder plating to the surface of the external lead 3, as shown in FIG. Do the test. In this case, the insulating heat-resistant thin plate 8 is not only connected to the external leads 3 on each side, but also
Since it is also adhesively fixed on the lead frame l, the external lead 3 is firmly fixed both in the lateral and vertical directions, and has the advantage of being able to prevent deformation even if it comes into contact with any part of the external lead 3 during the process. There is.
以上説明したように、本発明は樹脂封止後に絶縁耐熱薄
板を耐熱樹脂にて外部リード上に接着し、外部リード先
端をリードフレームより切断した後もこの絶縁耐熱薄板
により各週単位で外部リードを連結固定した状態にて、
電気的特性試験やり−ド成形の様に直接外部リードに接
触する工程を流すことにより接触時やハンドリング時の
リード変形を防止することができる、リード横曲がりを
なくし、コブラナリティを向上させることが可能となる
効果がある。As explained above, in the present invention, after resin sealing, an insulating heat-resistant thin plate is bonded onto the external lead using heat-resistant resin, and even after the external lead tip is cut from the lead frame, the external lead is connected weekly using this insulating heat-resistant thin plate. With the connection fixed,
By performing processes that directly contact external leads, such as electrical property testing and lead molding, it is possible to prevent lead deformation during contact and handling, eliminate lead lateral bending, and improve coplanarity. There is an effect that makes it possible.
第１図は本発明の第１の実施例である絶縁耐熱薄板を接
着した状態のリードフレームの平面図、第２図は本発明
の第１の実施例の外部リード先端を切断した状態のリー
ドフレームの平面図、第３図は本発明の第１の実施例の
外部リードの成形を行なったＩＣの斜視図、第４図は本
発明の第１の実施例の絶縁耐熱薄板を切断除去した後の
ＩＣの斜視図、第５図は本発明の第２の実施例の絶縁耐
熱薄板を接着した状態のリードフレームの平面図、第６
図は本発明の第２の実施例の外部リード先端を切断した
状態のリードフレームの平面図、第７図は従来の樹脂封
止後のリードフレームの平面図、第８図は従来の外部リ
ード先端を切断した状態のリードフレームの平面図、第
９図は従来の外部リードの成形後のＩＣの斜視図である
。
■・・・・・・リードフレーム、２・・・・・・封止パ
ッケージ、３・・・・・・外部リード、４・・・・・・
絶縁耐熱薄板、５・・・・・・吊りリード、６・・・・
・・ダイパ一部、７・・・・・・樹脂ダム部、８・・・
・・・絶縁耐熱薄板。FIG. 1 is a plan view of a lead frame with an insulating heat-resistant thin plate adhered thereto, which is the first embodiment of the present invention, and FIG. 2 is a plan view of the lead frame with the external lead tip of the first embodiment of the present invention cut. A plan view of the frame, FIG. 3 is a perspective view of an IC with external leads molded according to the first embodiment of the present invention, and FIG. 4 is a diagram showing the insulating heat-resistant thin plate of the first embodiment of the present invention cut and removed. FIG. 5 is a perspective view of the latter IC, and FIG.
The figure is a plan view of a lead frame with the tips of external leads cut off according to the second embodiment of the present invention, FIG. 7 is a plan view of a conventional lead frame after resin sealing, and FIG. 8 is a plan view of a conventional external lead. FIG. 9 is a plan view of a lead frame with its tip cut off, and a perspective view of an IC after molding of conventional external leads. ■...Lead frame, 2...Sealing package, 3...External lead, 4...
Insulated heat-resistant thin plate, 5... Hanging lead, 6...
... Part of the dieper, 7 ... Resin dam part, 8 ...
...Insulating heat-resistant thin plate.
Claims (1)
封止した後のリードフレームの外部リードに絶縁性を有
する耐熱薄板を耐熱樹脂にて接着し、外部リード先端切
断後は前記耐熱薄板にて外部リードを連結した状態にて
電気的特性試験及び外部リードの成形を行ない、最終工
程にて前記耐熱薄板を切断除去することを特徴とする樹
脂封止型半導体装置の製造方法。After the semiconductor chip is fixed to the lead frame, connected and sealed with resin, an insulating heat-resistant thin plate is adhered to the external leads of the lead frame using heat-resistant resin, and after the tips of the external leads are cut, the heat-resistant thin plate is used to seal the external A method for manufacturing a resin-sealed semiconductor device, characterized in that an electrical characteristic test and external lead molding are performed with the leads connected, and in the final step, the heat-resistant thin plate is cut and removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1169501A JP2504194B2 (en) | 1989-06-29 | 1989-06-29 | Method for manufacturing resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1169501A JP2504194B2 (en) | 1989-06-29 | 1989-06-29 | Method for manufacturing resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0334358A true JPH0334358A (en) | 1991-02-14 |
| JP2504194B2 JP2504194B2 (en) | 1996-06-05 |
Family
ID=15887689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1169501A Expired - Fee Related JP2504194B2 (en) | 1989-06-29 | 1989-06-29 | Method for manufacturing resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2504194B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0590479A (en) * | 1991-09-27 | 1993-04-09 | Nec Kyushu Ltd | Ic package |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5381073A (en) * | 1976-12-27 | 1978-07-18 | Hitachi Ltd | Oroduction of resin seal type semiconductor device and lead frame used the same |
| JPS6124261A (en) * | 1984-07-13 | 1986-02-01 | Nec Corp | Lead frame |
| JPS6489354A (en) * | 1987-09-29 | 1989-04-03 | Nec Corp | Flat package |
-
1989
- 1989-06-29 JP JP1169501A patent/JP2504194B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5381073A (en) * | 1976-12-27 | 1978-07-18 | Hitachi Ltd | Oroduction of resin seal type semiconductor device and lead frame used the same |
| JPS6124261A (en) * | 1984-07-13 | 1986-02-01 | Nec Corp | Lead frame |
| JPS6489354A (en) * | 1987-09-29 | 1989-04-03 | Nec Corp | Flat package |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0590479A (en) * | 1991-09-27 | 1993-04-09 | Nec Kyushu Ltd | Ic package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2504194B2 (en) | 1996-06-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |