JPH0332045A - Integrated circuit package - Google Patents
Integrated circuit packageInfo
- Publication number
- JPH0332045A JPH0332045A JP1167599A JP16759989A JPH0332045A JP H0332045 A JPH0332045 A JP H0332045A JP 1167599 A JP1167599 A JP 1167599A JP 16759989 A JP16759989 A JP 16759989A JP H0332045 A JPH0332045 A JP H0332045A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- integrated circuit
- electromagnetic waves
- resin
- emitted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920005989 resin Polymers 0.000 claims abstract description 18
- 239000011347 resin Substances 0.000 claims abstract description 18
- 229910000859 α-Fe Inorganic materials 0.000 abstract description 19
- 238000000465 moulding Methods 0.000 abstract description 7
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 230000005855 radiation Effects 0.000 abstract description 3
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、マイクロプロセッサ等の高周波でスイッチ
ング動作を行う集積回路チップより放射される電磁波を
効果的に遮蔽する集積回路パッケージに関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit package that effectively shields electromagnetic waves emitted from an integrated circuit chip such as a microprocessor that performs switching operations at high frequencies.
従来の集積回路パッケージの一例を第３図に示す１図に
おいて、１は集積回路（以下ＩＣと称する）チツア、５
は金属細線（金線）であり、リード６と上記ＩＣチップ
１上のボンディングパッドとを電気的に接続するもので
ある。８は上記ＩＣチップ１を支持するダイパッドであ
り、ＩＣチップ１を半田層７により接着支持している。An example of a conventional integrated circuit package is shown in FIG. 3, in which 1 is an integrated circuit (hereinafter referred to as IC) chip;
is a thin metal wire (gold wire), which electrically connects the lead 6 and the bonding pad on the IC chip 1. A die pad 8 supports the IC chip 1, and the IC chip 1 is adhesively supported by a solder layer 7.
１０はフェライト粉末を含有する例えばエポキシ樹脂
からなるモールド樹脂である。上記従来例では、モール
ド樹脂１０にフェライト粉末を添加することにより、Ｉ
Ｃチップ１からの電磁波の放射を低減しようとするもの
である。10 is a molding resin made of, for example, epoxy resin containing ferrite powder. In the above conventional example, by adding ferrite powder to the mold resin 10, I
This is intended to reduce electromagnetic wave radiation from the C chip 1.
従来の集積＠路パッケージでは、モールド樹脂１０に添
加できるフェライト粉末の割合について、モールドを可
能とするモールド樹脂（エポキシ樹脂〉の粘度及び流動
性の点から限界があった。In the conventional integrated package, there is a limit to the proportion of ferrite powder that can be added to the mold resin 10 due to the viscosity and fluidity of the mold resin (epoxy resin) that enables molding.
すなわち、高々モールド樹脂に添加するフェライト粉末
の含有率は、重量比からいって５０％程度であり、この
程度の含有率では電磁波の減衰効果がほとんど期待でき
ないという問題点があった。That is, the content of the ferrite powder added to the molding resin is approximately 50% by weight, and there is a problem in that at this level of content, almost no electromagnetic wave attenuation effect can be expected.
この発明は上記従来の問題点を解消するためになされた
ものであり、ＩＣチップより放射される電磁波をほぼ完
全に吸収する集積回路パッケージを提供することを目的
とする。The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide an integrated circuit package that almost completely absorbs electromagnetic waves emitted from an IC chip.
この発明に係る集積回路パッケージは、集積回路チップ
のボンディングパッドを有する面に対向するようにフェ
ライトを樹脂層を介して配置し、上記集積回路チップと
電磁波遮蔽板を一体化モールド樹脂成形したものである
。The integrated circuit package according to the present invention is one in which a ferrite is arranged via a resin layer so as to face the surface of the integrated circuit chip having the bonding pad, and the integrated circuit chip and the electromagnetic shielding plate are integrally molded with resin. be.
この発明の集積回路チップでは、集積回路チップのボン
ディングパッドを有する面から放射される電磁波がほぼ
完全に電磁波遮蔽板に吸収される。In the integrated circuit chip of the present invention, electromagnetic waves emitted from the surface of the integrated circuit chip having bonding pads are almost completely absorbed by the electromagnetic wave shielding plate.
第１図はこの発明の一実施例に係る集積回路パッケージ
の断面図を示したものであり、図において、１は集積回
路（ＩＣ）チップ、２はフェライト板、３は上記ＩＣチ
ップ１とフェライト板２の間に介在するエポキシ樹脂あ
るいはシリコンゲル等からなる樹脂層であり、この樹脂
層３はＩＣチップ１とフェライト板２とを接着してモー
ルド時にフェライト板２が正規の位置からずれるのを防
止するとともに、フェライト板２が直接ＩＣチップ１の
表面に接触してＩＣチップ表面に機械的ダメージを与え
ることを防止し、かつＩＣチップ１とフェライト板２と
の間の熱膨張係数の差による機械的応力を吸収する役割
を果している。４はエポキシ樹脂等からなるモールド樹
脂、５は上記ＩＣチップ１上のボンディングパッドとリ
ード６とを電気的に接続するための金属細線（金線〉、
８はグイパッドであり、上記ＩＣチップ１を半田層７を
介して固定している。FIG. 1 shows a cross-sectional view of an integrated circuit package according to an embodiment of the present invention. In the figure, 1 is an integrated circuit (IC) chip, 2 is a ferrite plate, and 3 is the IC chip 1 and the ferrite plate. This is a resin layer made of epoxy resin or silicone gel that is interposed between the plates 2. This resin layer 3 adheres the IC chip 1 and the ferrite plate 2 to prevent the ferrite plate 2 from shifting from its normal position during molding. It also prevents the ferrite plate 2 from directly contacting the surface of the IC chip 1 and causing mechanical damage to the IC chip surface, and also prevents the ferrite plate 2 from directly contacting the surface of the IC chip 1 and causing mechanical damage to the surface of the IC chip 1. It plays the role of absorbing mechanical stress. 4 is a mold resin made of epoxy resin or the like; 5 is a thin metal wire (gold wire) for electrically connecting the bonding pad on the IC chip 1 and the lead 6;
Reference numeral 8 denotes a pad to which the IC chip 1 is fixed via a solder layer 7.
次に動作について説明する。フェライト板２がＩＣチッ
プ１の上面に対向して配置されているため、ＩＣチップ
１の上面より放射される電磁波はほぼ完全にフェライト
板２に吸収される。なおＩＣチップ１下面へ放射される
電磁波は、半田層７あるいはＩＣチップ１がマウントさ
れているグイバッド８により遮蔽されるので、問題はな
い。Next, the operation will be explained. Since the ferrite plate 2 is disposed facing the top surface of the IC chip 1, electromagnetic waves emitted from the top surface of the IC chip 1 are almost completely absorbed by the ferrite plate 2. Note that the electromagnetic waves radiated to the lower surface of the IC chip 1 are shielded by the solder layer 7 or the guide pad 8 on which the IC chip 1 is mounted, so there is no problem.
上記実施例のような構造にすれば、特にワンチップマイ
クロコンピータの様にチップ内部での動作周波数がＩ１
０端子で与えられる信号周波数より格段に高い場合には
特に有効となる。If the structure of the above embodiment is adopted, the operating frequency inside the chip will be I1, especially like a one-chip microcomputer.
This is particularly effective when the signal frequency is much higher than the signal frequency given by the 0 terminal.
第２図は、この出願に係る発明をより一層効果的にする
ために、ＩＣチップ１のワイヤボンディングパッドに合
わせてフェライト板２に切欠きを入れた実施例の平面図
を示したものである。このようにＩＣチップ１上面のフ
ェライト板２がカバーする面積を拡げることによりＩＣ
チップ上面からの電磁波の放射を効果的に防止すること
ができる。FIG. 2 shows a plan view of an embodiment in which notches are made in the ferrite plate 2 to match the wire bonding pads of the IC chip 1 in order to make the invention of this application even more effective. . By expanding the area covered by the ferrite plate 2 on the top surface of the IC chip 1 in this way, the IC
Emission of electromagnetic waves from the top surface of the chip can be effectively prevented.
なお、フェライト板の材質、厚みは、ＩＣチップの内部
動作周波数、ＩＣチップから放射される電磁波の周波数
成分により最適値を選択すればよい。The material and thickness of the ferrite plate may be optimally selected depending on the internal operating frequency of the IC chip and the frequency components of electromagnetic waves radiated from the IC chip.
以上のように、この発明によれば集積回路チップ上に電
磁波遮蔽板を配置してモールド成形する構成としたので
、集積回路チップ上面から放射される電磁波はほとんど
電磁波遮蔽板に吸収され、集積回路（特にワンチップマ
イクロコンピュータ等）のＥＭＩ（不要電波放射）を素
子レベルで防止することができる効果がある。As described above, according to the present invention, since the electromagnetic wave shielding plate is disposed on the integrated circuit chip and molded, most of the electromagnetic waves emitted from the top surface of the integrated circuit chip are absorbed by the electromagnetic wave shielding plate, and the integrated circuit chip is This has the effect of preventing EMI (unnecessary radio wave radiation) of devices (particularly one-chip microcomputers, etc.) at the element level.
第１図はこの発明の一実施例による集積回路パッケージ
の断面図、第２図はこの発明の他の実施例の集積回路パ
ッケージの平面図、第３図は従来の集積回路パッケージ
を示す一部断面斜視図である。
図中、１は集積回路チップ、２はフェライト板。
３は樹脂層、４はモールド樹脂、５は金属細線。
６はリード、７は半田層、８はグイパッドを示す。
なお、図中同一符号は同−又は相当部分を示す。FIG. 1 is a cross-sectional view of an integrated circuit package according to one embodiment of the present invention, FIG. 2 is a plan view of an integrated circuit package according to another embodiment of the present invention, and FIG. 3 is a part showing a conventional integrated circuit package. It is a cross-sectional perspective view. In the figure, 1 is an integrated circuit chip and 2 is a ferrite plate. 3 is a resin layer, 4 is a mold resin, and 5 is a thin metal wire. 6 indicates a lead, 7 a solder layer, and 8 a lead pad. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
パッドを有する面に対向するように樹脂層を介して設置
された電磁波遮蔽板を備え、上記集積回路チップと電磁
波遮蔽板を一体モールド樹脂成形した集積回路パッケー
ジ。An integrated circuit comprising an integrated circuit chip and an electromagnetic wave shielding plate installed through a resin layer so as to face a surface of the integrated circuit chip having a bonding pad, the integrated circuit chip and the electromagnetic wave shielding plate being integrally molded with resin. package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1167599A JPH0332045A (en) | 1989-06-29 | 1989-06-29 | Integrated circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1167599A JPH0332045A (en) | 1989-06-29 | 1989-06-29 | Integrated circuit package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0332045A true JPH0332045A (en) | 1991-02-12 |
Family
ID=15852758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1167599A Pending JPH0332045A (en) | 1989-06-29 | 1989-06-29 | Integrated circuit package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0332045A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0732107A2 (en) * | 1995-03-16 | 1996-09-18 | Kabushiki Kaisha Toshiba | Circuit substrate shielding device |
| TWI471985B (en) * | 2009-02-19 | 2015-02-01 | Advanced Semiconductor Eng | Chip package and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60137041A (en) * | 1983-12-26 | 1985-07-20 | Matsushita Electronics Corp | Resin-sealed semiconductor device |
| JPH01138739A (en) * | 1987-11-25 | 1989-05-31 | Nec Corp | Integrated circuit package |
-
1989
- 1989-06-29 JP JP1167599A patent/JPH0332045A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60137041A (en) * | 1983-12-26 | 1985-07-20 | Matsushita Electronics Corp | Resin-sealed semiconductor device |
| JPH01138739A (en) * | 1987-11-25 | 1989-05-31 | Nec Corp | Integrated circuit package |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0732107A2 (en) * | 1995-03-16 | 1996-09-18 | Kabushiki Kaisha Toshiba | Circuit substrate shielding device |
| EP0732107A3 (en) * | 1995-03-16 | 1997-05-07 | Toshiba Kk | Circuit substrate shielding device |
| US5808878A (en) * | 1995-03-16 | 1998-09-15 | Kabushiki Kaisha Toshiba | Circuit substrate shielding device |
| TWI471985B (en) * | 2009-02-19 | 2015-02-01 | Advanced Semiconductor Eng | Chip package and manufacturing method thereof |
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