JPH0328781A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0328781A JPH0328781A JP1164749A JP16474989A JPH0328781A JP H0328781 A JPH0328781 A JP H0328781A JP 1164749 A JP1164749 A JP 1164749A JP 16474989 A JP16474989 A JP 16474989A JP H0328781 A JPH0328781 A JP H0328781A
- Authority
- JP
- Japan
- Prior art keywords
- pull
- circuit
- resistance
- resistor
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims 2
- 230000000644 propagated effect Effects 0.000 abstract description 2
- 238000005259 measurement Methods 0.000 abstract 1
- 239000004020 conductor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000013016 damping Methods 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 1
- 238000007688 edging Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 235000014347 soups Nutrition 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
[ $9 Jjl7)lI+I1 汁Jf ]この琵明
i;t. A4OS トランジスタにより構成され、ブ
ノレr,プ1氏fJ!Lもしくはプノレタウン{氏1ブ
Eをイイ嘩−る老導体染積回路の入力回.格に1!14
−るものである。[Detailed description of the invention] [$9 Jjl7) lI+I1 soup Jf] This bimei;t. Consisting of A4OS transistors, Bunore r, Pu1 fJ! L or Punore Town {Mr. 1 Bu E is the input circuit of the old conductor dyed circuit. Kakuni 1!14
-
〔従東の伎術1
第2図は従来の+導体q>漬同格のプルアップ抵抗及び
プルダウン11【抗を有rる人力同路を示4−[61δ
1飼で・hる。図(・ておいC、(1)は外ijB復続
端子、(2は外部信号を内部論理に1云える人力バソフ
ァ回路、(3)はプルアップ抵抗を構戊するPチャネル
MOSトランジスタ、(3a)はゲート電桶で、GND
電位に接続ざれている。+41 (iプルダウン抵杭を
構成4−るNチャ不ノレMO8トランジスタ、(4a)
はケ゛一F・電桶で、電l原濱位に4妾続されている。[Juto no Kijutsu 1 Figure 2 shows the conventional + conductor q > dipping appositional pull-up resistor and pull-down 11 [resistance r human power circuit]
One pet lasts for hours. (1) is the external ijB continuation terminal, (2 is the human-powered bass sofa circuit that can convert external signals into internal logic, (3) is the P-channel MOS transistor that constitutes the pull-up resistor, ( 3a) is the gate electric bucket, GND
Connected to electrical potential. (4a)
is Key 1F Den Oke, who has four concubines to Den I Hara Hamai.
(5)は八力1呆護ダイオードである。(5) is a 1-power diode.
次に動作について説明する。外部入力端子(1)にt手
えられた入力信号{1、プルアップ抵抗用トランジスタ
(3)と保護ダイオード(5)を4’U、人カバソファ
回路12}に1五搬しさらに内部回路に1云搬される。Next, the operation will be explained. The input signal received at the external input terminal (1) is transferred to {1, the pull-up resistor transistor (3) and the protection diode (5) to the 4'U, human cover sofa circuit 12}, and then to the internal circuit. 1 is carried.
人力信号か164理レベルでHレベルあるいはLレベル
のときは、人力信号として人カバノファ回路(2)に1
云殿するが、人力信号として与えら不tたイ言号か中間
レベルにあるとき、もしくはオープンの状態Kなったと
きは、Pチャ不ノレMOS hランジスタ(3)モシ
くはNチャ不ノレMOSトランジスタ(4)のゲート電
伸かそれぞれGNI)、電暉電位に接続されCいるため
,各々のトランジスタはゞオンケ伏伸となっており、そ
れぞれ電〆原電II・及びGND市イhに1−i′I定
される。即ち、外部入力端子tllKHもしくはLが与
えられた場合と同様の動作となる。When the human power signal is at H level or L level at the 164 logic level, 1
However, when the input signal given as a human input signal is at an intermediate level, or when the open state is reached, the P channel failure MOS h transistor (3) is activated. Since the gate of the MOS transistor (4) is connected to the electric potential (GNI) and electric potential (C), each transistor is connected to the electric potential. −i′I is determined. That is, the operation is the same as when the external input terminal tllKH or L is applied.
従来のプルアップ]圧抗あるいはプルダウン抵抗を備え
た入力回路は以上の様に構成されていたので、内部論理
回路の静的消費電流の測定時には外部より該当入力回路
に与えられる論理による入力回路部の消債電流を考慮し
なければならず、消α電流の測定のために外部入力信号
の設定に制約を加えることが必凌であり、またエージン
グによるgJ朗スクリーニング実施時には、多数個の入
力回路を駆動することによる駆動電流の検討が必歩であ
るなどの問題点があった。[Conventional pull-up] Input circuits equipped with pressure resistors or pull-down resistors are configured as described above, so when measuring the static current consumption of an internal logic circuit, the input circuit section is based on the logic applied to the relevant input circuit from the outside. It is necessary to take into account the depletion current of α, and it is necessary to impose restrictions on the settings of external input signals in order to measure the depletion There were problems such as the necessity to consider the drive current due to the drive.
この発明は上記のような問題点を解消するためになされ
たもので、外部からの制両信号により人力端子のブルア
ップ抵抗あるいはプルダウン低抗を制御できる名導体渠
漬回路を得ることをII的とする。This invention was made in order to solve the above-mentioned problems, and its second objective is to obtain a good conductor conduit circuit that can control the pull-up resistance or pull-down resistance of a human-powered terminal by an external control signal. shall be.
〔課題を解決するための手段1
この発明に係るf.導体集債同路は、入力川路111ツ
のプルアソブ抵抗あるいはプルダウン抵抗を構成するM
OS hランジスタのゲート電極を、各々1つのilt
ll al信号に接続するとともに、プルアップ抵抗の
制御信号、プルダウン1氏抗の制御1言号を1つの外部
制御端子として構成したものである。[Means for solving the problem 1 f. The conductor collector circuit is M which constitutes the pull-association resistor or pull-down resistor of the input channel 111.
The gate electrodes of the OS h transistors are connected to one ilt each.
In addition to being connected to the llal signal, the control signal for the pull-up resistor and one control word for the pull-down resistor are configured as one external control terminal.
〔作用1
この発明におけるプルアップ抵抗もしくはプルダウン抵
抗を構成するMOS トランジスタは、外部制御端子に
与えられる論理レベルによりONまたはOFFの状態を
とり、抵抗素子として動作あるいは動作しflい2つの
機能を持ち、また外部制呻端子は回路にプルダウン抵抗
を付加することにより、通常使用時にはその制#礪能を
任意に設定することが61能となる。[Operation 1] The MOS transistor constituting the pull-up resistor or pull-down resistor in the present invention is turned on or off depending on the logic level applied to the external control terminal, and has two functions: it operates as a resistor element or operates as a resistor element. Also, by adding a pull-down resistor to the external damping terminal circuit, the damping ability can be arbitrarily set during normal use.
[実施例]
販ド、この発明の一実施例を図について説明する。第1
図において、11)は外部接続端子、(2)は外部信号
を内部澹理に1云える人カバッファ回路、(3)はプノ
レアップ→氏抗を構戒するPチャ不ノレMOSトランジ
スタ、(3a)はゲート電極、(4)はプルダウン低抗
を構或するNチャ不ノレMOS トランジスタ. (4
a)はゲート電極,(5)は人力保護ダイオードである
。[Embodiment] An embodiment of the present invention will be described with reference to the drawings. 1st
In the figure, 11) is an external connection terminal, (2) is a buffer circuit that allows external signals to be transferred internally, (3) is a P-channel MOS transistor that prevents the internal delay, and (3a) (4) is a gate electrode, and (4) is an N-channel MOS transistor that constitutes a pull-down resistor. (4
a) is a gate electrode, and (5) is a human power protection diode.
(3b)はPチャ不ノレMOSトランジスタ(3)のゲ
ート電極(3a)を相互に接続する配線、(4b)はN
チャネルMOS トランジスタ(4)のゲート電極(4
a)を弔互に接続する配線で、それぞれ制一回路(6)
の人カバツファ回路(6a ) , (6b)に接続さ
れ、プルダウン抵抗(6C)を介して外部制御端子(6
d)に接続されている。(3b) is the wiring interconnecting the gate electrodes (3a) of the P-channel MOS transistors (3), and (4b) is the N
Gate electrode (4) of channel MOS transistor (4)
Wiring that connects a) to each other, each with a control circuit (6)
It is connected to the human cover circuits (6a) and (6b), and is connected to the external control terminal (6
d).
次に動作について説明する。外部制御端子(6d)に論
理レベルHを与えた場合、人力信号はブノレダウン抵抗
(6C)を介して人カバッノア(6a),(6b) K
伝搬される。人カバッフ7回路(6a)は非■又転、(
6b)は反転素子のためゲート接続配線(3b) ,
(4b)にはそれぞれH及びLレベルが伝えられ、ゲー
ト接続配vA (3b),(4b)を介して各MOSト
ランジスタのゲート電!5 (3a),(3b)にH及
びLレベルに固定される。Next, the operation will be explained. When a logic level H is applied to the external control terminal (6d), the human power signal is transmitted to the human control terminal (6a), (6b) K via the power down resistor (6C).
Propagated. The human Kabuff 7 circuit (6a) is non-■ and also inverts (
6b) is an inversion element, so gate connection wiring (3b),
(4b) are respectively transmitted with H and L levels, and the gate voltage of each MOS transistor is transmitted via gate connection wirings vA (3b) and (4b). 5 (3a) and (3b) are fixed at H and L levels.
即ち、PチャネルMOSトランジスタ(31、及びNチ
ャ不ノレMOShランジスタ(4)はカノトオフ伏態と
なり、ク1朗のプルアソプ抵抗、プルダウン抵抗は・庸
限大となる。That is, the P-channel MOS transistor (31) and the N-channel MOS transistor (4) are turned off, and the pull-up resistance and pull-down resistance of the transistor become extremely large.
一方、外i,+5 ii用御端子(6d)にLレベルま
たは開放状態とした場合、プルダウン抵抗(6C)によ
りLレベルに間定され、各々のゲート電極(3a),(
3b)にL及びHレベルが1云えられ、各トランジスタ
は導虐伏態、即ちトランジスタのオン抵抗を介して電隙
屯位、G N D ?lt位に接続ざれプルγソブ抵抗
、プルダウン抵抗として動作がdJ能となる。On the other hand, when the outer i, +5 ii control terminals (6d) are set to L level or open, they are set to L level by the pull-down resistor (6C), and the respective gate electrodes (3a), (
In 3b), the L and H levels are said to be 1, and each transistor is in a conductive state, that is, the electric gap level, G ND ? When connected to the lt position, the pull-gamma resistor operates as a pull-down resistor with a dJ function.
なお、上記実施例では外部制碑端子(6d)にプルダウ
ン抵抗(6c)を設け、人力バソファ回路(6a)に非
反転、(6b)には転素子を設けた場合をボしたが、外
部di M端子(6d)にプルアップ抵抗を設け、入力
バッファ(6a)に非B<転、(6b)に反転素子を設
けCもよい。この場合、外部制却端子(6d)に与える
制碑信号i′:LLレベルでブルアノブ抵抗、プルダウ
ン抵抗ともにカソトオフの状態となり、開放時には抵抗
素子として動作し同じ劾果を達成できる。In the above embodiment, the external control terminal (6d) is provided with a pull-down resistor (6c), and the human-powered basso circuit (6a) is provided with a non-inverting element and (6b) is provided with a switching element. Alternatively, a pull-up resistor may be provided at the M terminal (6d), a non-B<inversion element may be provided at the input buffer (6a), and an inversion element may be provided at (6b). In this case, when the control signal i' applied to the external control terminal (6d) is at the LL level, both the pull-out knob resistor and the pull-down resistor are turned off, and when they are open, they operate as resistive elements, achieving the same effect.
また、−ヒ記実施例では人力専用回路の場合について説
明したが、人力、出力の双方の機能をあわせ持つ双方句
同路でちってもよく七記実施例と向球の効果を奏rる。In addition, although the case of a circuit exclusively for human power was explained in the embodiment described in Section 7, it is also possible to use a circuit that has both functions of human power and output, and has the same effect as the embodiment described in Section 7. .
以トのよう←ここの発明によれば、プルアノプ抵抗、プ
ルダウン抵抗を構成する1・ランジスタσ)γ− トi
t極を外部制の端子に接続する構成VC Lだので、染
債lit路検賓時の4源電流の測定が谷特にでき、また
fr’t Ill’のlii+いものが(尋られるとと
もシ(、エジンクm路等の設計、製作が安価に−Cきる
,g, 4±がある。As follows←According to the present invention, 1 transistor σ) γ- configuring the pull-up resistor and pull-down resistor
Since the VC L has a configuration in which the t pole is connected to the external control terminal, it is possible to measure the 4-source current at the time of inspection of the dyed bond, and also to measure the lii+ of fr't Ill' (when asked). There are -C, g, and 4±, which allow for inexpensive design and manufacture of cylindrical and edging m-roads, etc.
4.図面の・+4111玉な説明
第1図{4この発明の一実施tallによる廿Ja体果
債同格をl]々rf「±1路図、第2図は従来の半導体
東債[りl路の1i1l+′8図である。図(でおいて
、11.1 +i外部接続端、(2)は人ノjバノノア
回路、(3}はPチャネルMOSトラン・ジスタ、{4
}はN1ヤ不ノレMOS トランジスタ、(5)14人
力1呆護ダイオード、(6}は抵抗制1抑同路である。4. +4111 explanation of the drawings Fig. 1 {4 One embodiment of this invention tall represents the equivalent grade of the 廿Ja body fruit bond l] 1i1l+'8. In the figure, 11.1 +i external connection terminal, (2) is the human node circuit, (3} is the P channel MOS transistor, {4
} is an N1-wire MOS transistor, (5) is a 14-power protection diode, and (6} is a resistor-controlled 1 suppression path.
fl F3、間中、同− 仔号{4向−、Kはvi」+
.1必5ナを/jます。fl F3, middle, same child number {4 direction-, K is vi''+
.. 1 must be 5 na/j.
代坤人 犬g増雄Daikonjin Inug Masuo
Claims (1)
路においてPチャネルMOSトランジスタ、及びNチャ
ネルMOSトランジスタにより構成されるプルアップ抵
抗及びプルダウン抵抗を有する入力回路において、該当
MOSトランジスタのゲート電極を全て接続し外部端子
に接続したことを特徴とする半導体集積回路。In an input circuit of an integrated circuit composed of MOS transistors, in an input circuit having a pull-up resistor and a pull-down resistor composed of a P-channel MOS transistor and an N-channel MOS transistor, all the gate electrodes of the relevant MOS transistors are connected to an external terminal. A semiconductor integrated circuit characterized by being connected to.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1164749A JPH0328781A (en) | 1989-06-27 | 1989-06-27 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1164749A JPH0328781A (en) | 1989-06-27 | 1989-06-27 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0328781A true JPH0328781A (en) | 1991-02-06 |
Family
ID=15799189
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1164749A Pending JPH0328781A (en) | 1989-06-27 | 1989-06-27 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0328781A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0560845A (en) * | 1991-09-04 | 1993-03-12 | Sharp Corp | Digital integrated circuit |
US6150831A (en) * | 1997-07-10 | 2000-11-21 | Mitsubishi Denki Kabushiki Kaisha | Test method and device for semiconductor circuit |
JP2007046401A (en) * | 2005-08-12 | 2007-02-22 | Miyazono Seisakusho:Kk | Roof tile |
-
1989
- 1989-06-27 JP JP1164749A patent/JPH0328781A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0560845A (en) * | 1991-09-04 | 1993-03-12 | Sharp Corp | Digital integrated circuit |
US6150831A (en) * | 1997-07-10 | 2000-11-21 | Mitsubishi Denki Kabushiki Kaisha | Test method and device for semiconductor circuit |
JP2007046401A (en) * | 2005-08-12 | 2007-02-22 | Miyazono Seisakusho:Kk | Roof tile |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3038094B2 (en) | Output circuit of semiconductor integrated circuit device | |
JPH0351306B2 (en) | ||
JPH0746106A (en) | Power-on signal generating circuit | |
US4350906A (en) | Circuit with dual-purpose terminal | |
JPS6096021A (en) | Trigger circuit | |
JPH0328781A (en) | Semiconductor integrated circuit | |
JP3024774B2 (en) | Circuit element | |
JPS63142719A (en) | Complementary type mos integrated circuit with three states | |
JPH0231896B2 (en) | ||
JPH05890B2 (en) | ||
JPS5820980Y2 (en) | input circuit | |
JP2767911B2 (en) | Pull-up / pull-down input circuit | |
JPS6025323A (en) | Semiconductor integrated circuit | |
JP3012276B2 (en) | Output circuit | |
JP2712411B2 (en) | Test circuit | |
JPH04132311A (en) | Input buffer | |
JP2641979B2 (en) | LSI test method | |
JP2531643B2 (en) | Semiconductor integrated device | |
JP2712432B2 (en) | Majority logic | |
JP2595074B2 (en) | Semiconductor integrated circuit device | |
JPH0522110A (en) | Output circuit | |
JPH0287715A (en) | Output circuit | |
JPS62200821A (en) | Semiconductor integrated circuit | |
JPH03204227A (en) | Input protective circuit for mos transistor | |
JP2002271184A (en) | Interface circuit |