JPH03252575A - Self-diagnostic rom - Google Patents
Self-diagnostic romInfo
- Publication number
- JPH03252575A JPH03252575A JP2051019A JP5101990A JPH03252575A JP H03252575 A JPH03252575 A JP H03252575A JP 2051019 A JP2051019 A JP 2051019A JP 5101990 A JP5101990 A JP 5101990A JP H03252575 A JPH03252575 A JP H03252575A
- Authority
- JP
- Japan
- Prior art keywords
- data
- bcc
- bit
- rom
- self
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004364 calculation method Methods 0.000 claims description 25
- 238000004092 self-diagnosis Methods 0.000 claims description 8
- 238000007689 inspection Methods 0.000 abstract description 7
- 238000012360 testing method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ROMの検査に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to testing ROM.
近年のLSI集積密度は日を追って高くなり、それにつ
れてその検査方法もいろいろと改良されてきている。特
にメモリICの検査には多大の時間を要しており、検査
効率を上げるためにいくつものアルゴリズムが提案され
ているが、集積度の向上につれてその効果も薄れ、新た
なアルゴリズムの開発が必要になってきている。In recent years, the integration density of LSI has been increasing day by day, and various inspection methods have been improved accordingly. Testing memory ICs in particular takes a lot of time, and a number of algorithms have been proposed to improve testing efficiency, but as the degree of integration increases, their effectiveness diminishes, making it necessary to develop new algorithms. It has become to.
また、RAMの場合とは異なり、ROMの場合は予めデ
ータが書き込まれているので、書き込みの段階での検査
以外には積極的な監査は行われていないのが実状である
。Further, unlike in the case of RAM, in the case of ROM, data is written in advance, so active auditing is not performed other than the inspection at the writing stage.
従来のROMの検査法としては、例えばR,OMを対象
としているICテスタがある。第2図に従来のROMを
対象としているICテスタのブロック図を示す。As a conventional ROM testing method, there is an IC tester that targets R and OM, for example. FIG. 2 shows a block diagram of a conventional IC tester for ROM.
従来のROMを対象としているICテスタは、データR
AM10とアドレス生成部20と比較部30とから構成
されている。IC testers that target conventional ROMs are data R
It is composed of an AM 10, an address generation section 20, and a comparison section 30.
検査をする場合には、データRAMl0内に被検査体で
あるROM40に書き込まれているものと同じデータを
書き込み、その後、アドレス生成部20から全てのアド
レスを生成し、データを被検査1tkるROM40から
読みだして、データRAM10内のデータと逐一を比較
部で比較していくことにより行う。When testing, the same data as that written in the ROM 40, which is the object to be tested, is written into the data RAM 10, and then all addresses are generated from the address generation unit 20, and the data is transferred to the ROM 40 to be tested. This is done by reading out the data from the data RAM 10 and comparing it point by point with the data in the data RAM 10 in a comparing section.
上述した従来のROMの検査法は、全てのデータを比較
するので、ROMの容量が大きくなった場合、全てのデ
ータを読みだす時間がかかり、検査時間が非常に長くな
るという欠点があった。The conventional ROM inspection method described above compares all data, so when the capacity of the ROM becomes large, it takes time to read all the data, resulting in a very long inspection time.
本発明の自己診断ROMは、データ幅nビットのメモリ
セルアレイと、全データの第1ビットのデータ線に接続
され、アドレスの増加方向に第1ビットのデータに関し
てBCC演算をする第1BCC演算部と、該BCC演算
部に接続され、この結果を書き込む第1BCC部と、全
データの第2ビットのデータ線に接続され、アドレスの
増加方向に第2ビットのデータに関してBCC演算をす
る第28CC演算部と、該BCC演算部に接続され、こ
の結果を書き込む第2BCC部と、以下同様にアドレス
の増加方向に第nビットのデータに関してBCC演算を
行う第nBCC演算部Ionと、第nBCC演算部10
nの各々に接続され、その結果を書き込むn個の第nB
cc2゜n部と、各BCC部に書き込まれなりCCデー
タをデータバス2にのせる信号を入力する自己診断端子
とからなる。The self-diagnosis ROM of the present invention includes a memory cell array having a data width of n bits, and a first BCC operation section connected to the data line of the first bit of all data and performing a BCC operation on the data of the first bit in the increasing direction of the address. , a first BCC unit that is connected to the BCC calculation unit and writes the result, and a 28th CC calculation unit that is connected to the data line of the second bit of all data and performs a BCC calculation on the data of the second bit in the increasing direction of the address. , a second BCC unit that is connected to the BCC calculation unit and writes this result, an n-th BCC calculation unit Ion that similarly performs a BCC calculation on the data of the n-th bit in the increasing direction of the address, and an n-th BCC calculation unit 10.
nth nB connected to each of n and writing its result
It consists of a cc2゜n section and a self-diagnosis terminal that inputs a signal to put the CC data written in each BCC section on the data bus 2.
次に本発明の実施例について図面を参照して詳細に説明
する。Next, embodiments of the present invention will be described in detail with reference to the drawings.
第1図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
本実施例は、データ幅nビットのメモリセルアレイ1と
、全データの第1ビットのデータ線に接続され、アドレ
スの増加方向に第1ビットのデータに関してBCC演算
をする第1BCC演算部101と、第1 BCC演算部
101に接続され、二の結果を書き込む第1 BCC演
算部201と、全データの第2ビットデータ線に接続さ
れ、アドレスの増加方向に第2ビットのデータに関して
BCC演算をする第2BCC演算部102と、第28C
C演算部102接続され、この結果を書き込む第2BC
C部202と、以下同様にアドレスの増加方向に第nビ
ットのデータに関してBCC演算を行う第nBCC演算
部Ionと、第rxBcc演算部Ionに接続され、こ
の結果を書き込むn個の第nBCC部2Onと、各BC
C部に書き込まれたBCCデータをデータバス2にのせ
る信号を入力する自己診断端子とからなる。This embodiment includes a memory cell array 1 with a data width of n bits, a first BCC operation unit 101 connected to the data line of the first bit of all data, and performing a BCC operation on the data of the first bit in the increasing direction of the address; The first BCC calculation unit 201 is connected to the first BCC calculation unit 101 and writes the second result, and is connected to the second bit data line of all data, and performs BCC calculation on the second bit data in the increasing direction of the address. The second BCC calculation unit 102 and the 28th C
The second BC is connected to the C calculation unit 102 and writes this result.
C unit 202, an n-th BCC calculation unit Ion that similarly performs a BCC calculation on data of the n-th bit in the increasing direction of the address, and n-th nBCC calculation units 2On that are connected to the rxBcc calculation unit Ion and write the results. and each B.C.
It consists of a self-diagnosis terminal that inputs a signal to put the BCC data written in the C section on the data bus 2.
次に動作について説明する。先ず、自己診断端子3をイ
ナクティブにして、ROMライタを用いてデータの書き
込みを行う。ここで、書き込みのときに、外部に接続さ
れるROMのライタから生成されるアドレスに従って、
メモリセルのうちの1つのデータが選択され、ROMラ
イタから与えられるデータバス2上のデータが書き込ま
れる。この時、各ビット毎のデータ線に接続されたBC
C演算部101〜Ionでは、全てのアドレスが終了す
るまで、該データ線に現れるデータについて、アドレス
の増加方向についてBCCを計算し、その結果を各BC
C201〜2Onに書き込む。Next, the operation will be explained. First, the self-diagnosis terminal 3 is made inactive and data is written using a ROM writer. Here, when writing, according to the address generated from the externally connected ROM writer,
Data in one of the memory cells is selected, and data on the data bus 2 provided from the ROM writer is written. At this time, the BC connected to the data line for each bit
The C calculation units 101 to Ion calculate the BCC in the increasing direction of the address for the data appearing on the data line until all addresses are completed, and the result is applied to each BC.
Write to C201-2On.
次に、検査を行うときは、自己診断端子3をアクティブ
にする。これにより、各BCC部201〜2Onのデー
タがデータバスに乗り、ROMの外部にデータバス2を
介して出力される。ROMの外部には、ビット毎の正し
いBCCを記憶したRAMを用意する。ここで、このR
AM内のBCCとROMから読みだしたBCCとを比較
する。Next, when performing a test, the self-diagnosis terminal 3 is activated. As a result, the data of each BCC section 201 to 2On gets on the data bus and is outputted to the outside of the ROM via the data bus 2. A RAM storing correct BCC for each bit is prepared outside the ROM. Here, this R
The BCC in AM and the BCC read from ROM are compared.
本発明は、ROMの内部にBCCを記憶しており、検査
はこのBCCを読みだすことにより行い、ROM内の全
てのデータを読みだす必要はないので、検査に要する時
間はBCCを読みだす時間だけでよく、高々データ幅の
回数となる。従って、その時間は従来の検査法のように
書き込まれた全てのデータを読みだすのに比べ、遥かに
少なくてよいという多大な効果がある。In the present invention, the BCC is stored inside the ROM, and the test is performed by reading this BCC. Since it is not necessary to read all the data in the ROM, the time required for the test is the time required to read the BCC. The number of times is at most the same as the data width. Therefore, this method has the great effect of requiring far less time than reading all written data as in the conventional inspection method.
第1図は本発明の一実施例を示すブロック図、第2図従
来の技術の実施例を示すブロック図である。
1・・・メモリセルアレイ、2・・・データバス、3・
・・自己診断端子、101〜Ion・・・BCC演算部
、201〜20 I n−BCC部、301〜30 n
−データビット、10・・・データROM、20・・
・アドレス生成部、30・・・比較部、40・・・被試
験体ROM。FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an embodiment of a conventional technique. 1...Memory cell array, 2...Data bus, 3.
...Self-diagnosis terminal, 101-Ion...BCC calculation section, 201-20 I n-BCC section, 301-30 n
-Data bit, 10...Data ROM, 20...
- Address generation section, 30... Comparison section, 40... Test object ROM.
Claims (1)
1ビットのデータ線に接続され、アドレスの増加方向に
第1ビットのデータに関してチェクサム(以下BCCと
略す)演算をする第1BCC演算部と、該BCC演算部
に接続され、この結果を書き込む第1BCC部と、全デ
ータの第2ビットのデータ線に接続され、アドレスの増
加方向に第2ビットのデータに関してBCC演算をする
第2BCC演算部と、該BCC演算部に接続され、この
結果を書き込む第2BCC部と、以下同様にアドレスの
増加方向に第nビットのデータに関してBCC演算を行
うn個のBCC演算部と、該n個のBCC演算部の各々
に接続され、その結果を書き込むn個のBCC部と、各
BCC部に書き込まれたBCCデータをデータバスにの
せる信号を入力する自己診断端子とからなることを特徴
とする自己診断ROM。a memory cell array with a data width of n bits, a first BCC operation unit connected to the data line of the first bit of all data and performing a checksum (hereinafter abbreviated as BCC) operation on the data of the first bit in the increasing direction of the address; a first BCC unit that is connected to the BCC calculation unit and writes this result; a second BCC calculation unit that is connected to the data line of the second bit of all data and performs a BCC calculation on the data of the second bit in the increasing direction of the address; a second BCC unit that is connected to the BCC calculation unit and writes this result; n BCC calculation units that similarly perform BCC calculations on the n-th bit data in the increasing direction of the address; and the n BCC calculation units. A self-diagnosis ROM characterized by comprising: n BCC sections which are connected to each of the BCC sections and write the results thereof, and a self-diagnosis terminal which inputs a signal to put the BCC data written in each BCC section on a data bus. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2051019A JPH03252575A (en) | 1990-03-01 | 1990-03-01 | Self-diagnostic rom |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2051019A JPH03252575A (en) | 1990-03-01 | 1990-03-01 | Self-diagnostic rom |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03252575A true JPH03252575A (en) | 1991-11-11 |
Family
ID=12875085
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2051019A Pending JPH03252575A (en) | 1990-03-01 | 1990-03-01 | Self-diagnostic rom |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03252575A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8925689B2 (en) | 2011-01-19 | 2015-01-06 | Smart Lifts, Llc | System having a plurality of elevator cabs and counterweights that move independently in different sections of a hoistway |
-
1990
- 1990-03-01 JP JP2051019A patent/JPH03252575A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8925689B2 (en) | 2011-01-19 | 2015-01-06 | Smart Lifts, Llc | System having a plurality of elevator cabs and counterweights that move independently in different sections of a hoistway |
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