JPH03242925A - Liquid phase epitaxy method - Google Patents
Liquid phase epitaxy methodInfo
- Publication number
- JPH03242925A JPH03242925A JP4073590A JP4073590A JPH03242925A JP H03242925 A JPH03242925 A JP H03242925A JP 4073590 A JP4073590 A JP 4073590A JP 4073590 A JP4073590 A JP 4073590A JP H03242925 A JPH03242925 A JP H03242925A
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- substrate
- liquid phase
- molten metal
- epitaxial growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000004943 liquid phase epitaxy Methods 0.000 title abstract 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 239000007791 liquid phase Substances 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims description 18
- 150000001875 compounds Chemical class 0.000 claims description 4
- 239000000155 melt Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 25
- 230000007547 defect Effects 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 9
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 6
- 229910052733 gallium Inorganic materials 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- -1 GaAs compound Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ｍ−ｖ族化合物からなる基材に■族の溶融金
属を液相エピタキシャル成長させる、特に■−ｖ族化合
物半導体からｐ−ｎ接合半導体を製造する上で好適な液
相エピタキシャル威長方法に関する。Detailed Description of the Invention (Industrial Field of Application) The present invention involves liquid phase epitaxial growth of a molten metal of group Ⅰ on a base material made of an m-v group compound. The present invention relates to a liquid phase epitaxial growth method suitable for manufacturing junction semiconductors.
（従来の技術）
液相エピタキシャル成長を行なう場合、例えば第２図に
示す装置、即ち、グラファイト、石英又は酸化アルミニ
ウムからなる第１の台板ｌ上に溶融金属４、例えば溶融
ガリウムとこれを液相エピタキシャル成長させる基板５
、例えばＧａＡｓやＧａＰからなる基板を隣接して配置
し、更にこの上に第２の台板２を例えばスペーサ８によ
りこの第１の台板との間に間隙を開けて載置した装置を
用いて、第４図に示すように前記溶融金属を液相エピタ
キシャル成長開始温度以上に昇温し、この温度に一定時
間保持した後冷却を行なうことによって液相エピタキシ
ャル成長を行なう方法が特開昭５５−５９７１７号公報
に記載されている。(Prior Art) When performing liquid phase epitaxial growth, for example, the apparatus shown in FIG. Substrate 5 for epitaxial growth
For example, an apparatus is used in which substrates made of GaAs or GaP are placed adjacent to each other, and a second base plate 2 is placed on top of the substrates with a gap formed between them and the first base plate by, for example, spacers 8. As shown in FIG. 4, a method is disclosed in JP-A-55-59717 in which liquid phase epitaxial growth is carried out by heating the molten metal to a temperature above the liquid phase epitaxial growth starting temperature, holding it at this temperature for a certain period of time, and then cooling it. It is stated in the No.
ここで、上記第２の台板２及びスペーサ８は第１の台板
１と同様な材料で構成されている。Here, the second base plate 2 and the spacer 8 are made of the same material as the first base plate 1.
また、前記公報には、ｐ−ｎ接合半導体を得る場合、第
１図に示すように、第１の台板ｌの溶融金属４と反対側
の基板５に隣接する面に溝７を形成して、この溝７の中
に不純物６、例えばＳｉを入れて液相エピタキシャル成
長を行なう方法が記載されている。The publication also states that when obtaining a p-n junction semiconductor, as shown in FIG. A method is described in which an impurity 6, for example, Si, is introduced into the groove 7 and liquid phase epitaxial growth is performed.
（発明が解決しようとする課題）
しかしながら、このような方法でエピタキシャル成長を
行なうと、たとえ、還元雰囲気中でエピタキシャル成長
を行なったとしても基板上の酸化被膜が十分に除去され
ないうちに溶融金属、例えば溶融ガリウムの移動が起こ
るので均一なエピタキシャル層が得られない。(Problem to be Solved by the Invention) However, when epitaxial growth is performed using such a method, even if epitaxial growth is performed in a reducing atmosphere, molten metal, e.g. Since gallium migration occurs, a uniform epitaxial layer cannot be obtained.
また、ｐ−ｎ接合半導体を製造する場合、基板上の酸化
被膜が十分に除去されていないので残存する酸化被膜に
よって得られるｐ−ｎ接合半導体への不純物のドーピン
グ量が異なってくるため、安定した特性のｐ−ｎ接合半
導体が得られないといった問題がある。In addition, when manufacturing a p-n junction semiconductor, the oxide film on the substrate is not sufficiently removed, so the amount of impurity doped into the resulting p-n junction semiconductor varies depending on the remaining oxide film, resulting in a stable There is a problem that a pn junction semiconductor with such characteristics cannot be obtained.
更には、基板の一部にくわれが生じ、このため、上記基
板上の酸化被膜による問題と併せて、従来の特開昭５５
−５９７１７号公報に記載された方法では均一で欠陥の
少ないメルトバック界面が得られないといった問題があ
る。Furthermore, cracks occur in a part of the substrate, which, in addition to the problem caused by the oxide film on the substrate,
The method described in Japanese Patent No. 59717 has a problem in that a uniform meltback interface with few defects cannot be obtained.
（課題を解決するための手段）
本発明は上記課題を解決するため、前記基材を還元雰囲
気中でその表面が溶融して溶融金属中に０．１重量バー
セントル０．２重量パーセントの割合で溶解する温度に
昇温してこの温度に一定時間保ち１次いで溶融金属な液
相エピタキシャル成長開始温度以上に昇温する方法で溶
融金属を液相エピタキシャル成長させるようにしたもの
である。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention is directed to melting the surface of the base material in a reducing atmosphere and adding 0.1 weight percent to 0.2 weight percent of the base material to the molten metal. The liquid phase epitaxial growth of the molten metal is carried out by raising the temperature to a melting temperature, maintaining this temperature for a certain period of time, and then increasing the temperature to a temperature higher than the liquid phase epitaxial growth start temperature of the molten metal.
（作用）
上記本発明方法によれば、溶融金属を液相エピタキシャ
ル成長させるまでの一定時間にわたって基材は液相エピ
タキシャル成長開始温度未満の高温の還元雰囲気にさら
され、基板上の酸化被膜は還元される。更に、この酸化
被膜の還元反応は基材の表面が溶融しているため、酸化
被膜の内部まで進行する。(Function) According to the method of the present invention, the base material is exposed to a reducing atmosphere at a high temperature below the liquid phase epitaxial growth start temperature for a certain period of time until the molten metal is liquid phase epitaxially grown, and the oxide film on the substrate is reduced. . Furthermore, since the surface of the base material is melted, this reduction reaction of the oxide film progresses to the inside of the oxide film.
また、このように基材の表面が溶融し、溶融金属中に０
．１重量バーセントル０．２重量パーセントの割合で溶
解しているため、スムーズな溶融金属のエピタキシャル
成長がなされ、メルトバック界面が得られる。In addition, the surface of the base material is melted in this way, and 0% is added to the molten metal.
．． Since the metal is melted at a ratio of 0.2 weight percent to 1 weight percent, smooth epitaxial growth of the molten metal is achieved and a melt-back interface is obtained.
（実施例） 以下に実施例を示し、本発明を更に詳しく説明する。(Example) The present invention will be explained in more detail with reference to Examples below.
既に説明した第１図の装置でｐ−ｎ接合ＧａＡｓ化合物
半導体を製造する場合につき、以下に説明する。The case where a pn junction GaAs compound semiconductor is manufactured using the apparatus shown in FIG. 1 described above will be described below.
即ち、第１図の装置において、第１の台板ｌ、第２の台
板２に平板状の石英板又はグラファイト板を使用し、ま
た、スペーサ８にも同様の材質のものを使用する。That is, in the apparatus shown in FIG. 1, a flat quartz plate or a graphite plate is used for the first base plate 1 and the second base plate 2, and the spacer 8 is also made of the same material.
そして、まず、溝７を形成した第１の台板１のこの溝７
の端面に基板（ＧａＡｓ基板）５の端面を合せて第１の
台板ｌ上に基板５を配置し、更にこの基板５の他端に接
して溶融金属（溶融ガリウム）４を配置し、溝７中に不
純物（Ｓｔ）６を入れる。First, the groove 7 of the first base plate 1 in which the groove 7 was formed is
A substrate 5 is placed on the first base plate l with the end surface of the substrate (GaAs substrate) 5 aligned with the end surface of the substrate 5, and a molten metal (molten gallium) 4 is placed in contact with the other end of the substrate 5, and a groove is formed. Impurity (St) 6 is introduced into 7.
次いで、第３図に示すように、この状態で基板５のＧａ
Ａｓの溶融金属４である溶融ガリウムへの溶解度が０．
１重量バーセントル０．２重量パーセントとなる温度、
即ち６７０℃〜６８０℃まで昇温し、この温度で基板５
及び溶融金属４をＨ？還元雰囲気中で１時間保持し、し
かる後、この基板５及び溶融金属４を第２の台板２で覆
う。この際に過剰な溶融金属４である溶融ガリウムが溝
７中に流れ込むので不純物６であるＳｔが製品中に取り
込まれる。Next, as shown in FIG. 3, Ga of the substrate 5 is removed in this state.
The solubility of As in molten gallium, which is the molten metal 4, is 0.
The temperature at which 1 weight bar centre is 0.2 weight percent,
That is, the temperature is raised to 670°C to 680°C, and the substrate 5 is heated at this temperature.
and molten metal 4 to H? The substrate 5 and molten metal 4 are kept in a reducing atmosphere for one hour, and then covered with a second base plate 2. At this time, excess molten gallium, which is the molten metal 4, flows into the groove 7, so that St, which is the impurity 6, is incorporated into the product.
この後、基板５及び溶融金属４を９３０℃まで昇温し、
この温度で一定時間、例えば１時間保持し、次いでｌ”
Ｑ／ｍｉｎ〜２℃／ ｍ ｉ ｎの冷却速度で冷却する
ことにより溶融金属４である溶融ガリウムを基板５のＧ
ａＡｓ上にエピタキシャル成長させる。 ここで不純物
６であるＳｉは両性不純物であるので、このようにして
ｐ−ｎ接合半導体を得ることができる。After that, the temperature of the substrate 5 and the molten metal 4 is raised to 930°C,
Hold at this temperature for a certain period of time, for example 1 hour, then l”
The molten gallium, which is the molten metal 4, is cooled to the G of the substrate 5 by cooling at a cooling rate of Q/min to 2°C/min.
Epitaxially grown on aAs. Since Si, which is the impurity 6, is an amphoteric impurity, a pn junction semiconductor can be obtained in this manner.
以上にＧａＡｓ化合物半導体に溶融ガリウムをエピタキ
シャル成長させ、Ｓｉ不純物をドーピングする場合につ
いて述べたが、上記ＧａＡｓ化合物半導体に代えてＧａ
ＡＪＩＡｓ化合物半導体を使用したりすることができる
など、本発明方法は基材がｍ−ｖ族化合物であって溶融
金属が■族の金属である他のものについても適用できる
のは勿論である。The case where molten gallium is epitaxially grown on a GaAs compound semiconductor and doped with Si impurities has been described above.
Of course, the method of the present invention can also be applied to other materials in which the base material is an m-v group compound and the molten metal is a group (I) metal, such as AJIAs compound semiconductor.
（発明の効果）
以上の実施例のようにして液相エピタキシャル成長を行
なうことにより、液相エピタキシャル成長開始前の還元
雰囲気中で基材表面の酸化被膜が除去され、また、基材
表面が溶融金属への溶解度が０．１重量バーセントル０
．２重量パーセントとなる程度の僅かな量、即ち基材に
影響を与えない程度に溶融しているので、欠陥の少ない
エピタキシャル層が得られるとともに、基材とエピタキ
シャル層との界面を均一なメルトバックとすることがで
きる。(Effects of the Invention) By performing liquid phase epitaxial growth as in the above embodiments, the oxide film on the surface of the base material is removed in a reducing atmosphere before the start of liquid phase epitaxial growth, and the surface of the base material is transferred to molten metal. Solubility of 0.1 weight bar centre 0
．． Since it is melted in a small amount of 2% by weight, that is, to the extent that it does not affect the base material, an epitaxial layer with few defects can be obtained, and the interface between the base material and the epitaxial layer can be uniformly melted back. It can be done.
更には、不純物をドーピングする場合においては、不純
物が均一に取り込まれた平滑度の良好なエピタキシャル
層が得られる。Furthermore, in the case of doping with impurities, an epitaxial layer with good smoothness in which the impurities are uniformly incorporated can be obtained.
第１図及び第２図はそれぞれ本発明に係る液相エピタキ
シャル装置を模式的に表わした断面図、第３図は本発明
方法における昇温過程を示すグラフ、第４図は従来方法
における昇温過程を示すグラフである。
１・・・第１の台板、２・・・第２の台板、３・・・間
隙、４・・・溶融金属、５・・・基板、６・・・不純物
、７・・・溝、８・・・スペーサ。
特 許 出 願 人 日本ビクター株式会社第４図FIGS. 1 and 2 are cross-sectional views schematically showing the liquid phase epitaxial apparatus according to the present invention, FIG. 3 is a graph showing the temperature increase process in the method of the present invention, and FIG. 4 is a graph showing the temperature increase in the conventional method. It is a graph showing the process. DESCRIPTION OF SYMBOLS 1... First base plate, 2... Second base plate, 3... Gap, 4... Molten metal, 5... Substrate, 6... Impurity, 7... Groove , 8... Spacer. Patent applicant: Victor Japan Co., Ltd. Figure 4
Claims (1)
なる基材を隣接して配置し、更にこの上に第２の台板を
前記第１の台板との間に間隙を開けて載置して行なう液
相エピタキシャル成長方法において、前記基材を還元雰
囲気中でその表面が溶融して前記溶融金属中に０．１重
量パーセント乃至０．２重量パーセントの割合で溶解す
る温度に昇温してこの温度に一定時間保ち、次いで前記
溶融金属を液相エピタキシャル成長開始温度以上に昇温
することを特徴とする液相エピタキシャル成長方法。A base material made of a group III molten metal and a group III-V compound is placed adjacent to each other on a first base plate, and a second base plate is placed on top of the base material with a gap between it and the first base plate. In a liquid phase epitaxial growth method performed by opening and placing the base material, the temperature at which the surface of the base material melts in a reducing atmosphere and dissolves in the molten metal at a rate of 0.1% by weight to 0.2% by weight. 1. A method for liquid phase epitaxial growth, characterized in that the temperature is raised to a temperature of 100 to 100 nm, maintained at this temperature for a certain period of time, and then the temperature of the molten metal is raised to a temperature higher than a temperature at which liquid phase epitaxial growth starts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4073590A JPH03242925A (en) | 1990-02-21 | 1990-02-21 | Liquid phase epitaxy method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4073590A JPH03242925A (en) | 1990-02-21 | 1990-02-21 | Liquid phase epitaxy method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03242925A true JPH03242925A (en) | 1991-10-29 |
Family
ID=12588894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4073590A Pending JPH03242925A (en) | 1990-02-21 | 1990-02-21 | Liquid phase epitaxy method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03242925A (en) |
-
1990
- 1990-02-21 JP JP4073590A patent/JPH03242925A/en active Pending
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