JPH0323648A - Manufacture of dielectric isolation substrate - Google Patents
Manufacture of dielectric isolation substrateInfo
- Publication number
- JPH0323648A JPH0323648A JP15689989A JP15689989A JPH0323648A JP H0323648 A JPH0323648 A JP H0323648A JP 15689989 A JP15689989 A JP 15689989A JP 15689989 A JP15689989 A JP 15689989A JP H0323648 A JPH0323648 A JP H0323648A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- island
- insulating film
- groove
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000002955 isolation Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 26
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 24
- 239000013078 crystal Substances 0.000 description 10
- 239000003513 alkali Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 241000238557 Decapoda Species 0.000 description 1
- 208000012868 Overgrowth Diseases 0.000 description 1
- 235000009754 Vitis X bourquina Nutrition 0.000 description 1
- 235000012333 Vitis X labruscana Nutrition 0.000 description 1
- 240000006365 Vitis vinifera Species 0.000 description 1
- 235000014787 Vitis vinifera Nutrition 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、同一基板内に異なる深さの単結晶半導体島
を有する誘電体分離基板の製造方法に関するものである
．
（従来の技術）
誘電体分離構造を有する半導体集積回路装置において、
高耐圧素子と低耐圧素子とを同一誘電体分ＩＩＩＩｌ＆
板に混載する場合、高耐圧素子が形成される島は、逆バ
イアス時の空乏層輻に応じて深くし、低耐圧素子が形成
される島は、縦型ＮＰＮ ｝ランジスタのコ゛レクタ抵
抗を小さくするために浅くするというように、内蔵素子
の特性に応じて島の深さを最適化する試みがなされてい
る．
このように深い島と浅い島を同一基板内に混載する誘電
体分離基板の製造方法は、公知文献例として特開昭５５
− １０５３４０号公報があり、この文献に記載され
ているように、二段以上の異方性エッチングを行って形
成されている．
以下その製造方法を第２図（ω〜（ｅ）に示す工程断面
図により説明する．
まず第２図（ａ）に示すように、Ｎ型で（１０（ｃ）面
を有する単結晶Ｓｉ基板ｌの主表面側に酸化膜２を形成
し、バターニングした後、この酸化膜２をエッチングマ
スクとして、所望の深さをもった凹部３を、アルカリ異
方性エッチング技術を用いて基板ｌに形或する．
次に第２図（ハ）に示すように酸化Ｉ１２を除去した後
、凹部３を含む基板１の主表面に酸化膜４を新たに被着
し、これをフォト・エッチング技術にて図のように所望
のパターンとする．
次に、パターニングされた酸化膜４をマスクとして第２
図（ａ）と同様に基板ｌのアルカリ異方性エッチングを
行い、第２図（Ｃ）に示すように■溝５を形戒する．
次に第２図（ロ）に示すように酸化膜４を除去した後、
前記Ｖ溝５を含む基板１の主表面上に酸化膜６を被着し
、さらにその上に支持体となる多結晶ｈ層７を形或する
．
次に単結晶訓基板１の反対主表面側より、前記Ｖ溝５の
底部先端が露出するまで（第２図（ｄ）中のＡ−Ａライ
ンの位置まで）基板ｌを研磨除去する．これにより第２
図（ｅ）に示すように酸化Ｈ６で完全分離された、残存
Ｓｔ基板部がらなる深い島８ａと浅い島８ｂが同一 基
板内に形成された誘電体分屠基板が完威する．
（発明が解決しようとする課ＩＩＩ）
しかしながら、上記従来の製造方法では、まず第２図（
萄の凹部３形成の際エッチングスピードの速い（１０Ｇ
）面を底面に残すため凹部３の深さにバラッキが生じや
すいことや、第２図（ロ）の酸化Ｉ１４のパターニング
の際、凹部３の底面と基板ｌ主表面が通常１０一以上の
段差をもっているため、凹部３内での酸化膜４のパター
ニング精度が著じるしく低下し、所望のパターニング寸
法が安定して得られないといったことから、第２図（ロ
）で形成されるＶ溝５の底部先端位置が、凹部３でのＶ
溝と基板ｌ主表面上からのＶ溝とで不揃いになるといっ
た問題があった．そのため、次のＳｌ基板ｌの研磨の際
、精度よく平坦に研磨が進行しても、■溝５先端の露出
が一様にはならず、研磨オーバー領域や逆に不足の領域
が基板内に混在して現われる等歩留り低下の一原因とな
っていた．また、この従来の方法は、アルカリ異方性エ
ッチングを２回も行う煩わしさもあった．
この発明は上記の点に鑑みなされたもので、異なる深さ
の単結晶半導体島を有する誘電体分離基板を高精度に歩
留り良く容易に形或することができる誘電体分ｊｌ１碁
板の製造方法を提供することを目的とする．
（課題を解決するための手段）
この発明は、異なる深さの単結晶半導体島を有する誘電
体分離基板の製造方法において、凹部形戒の必要のない
、しかも一回のアルカリ異方性エッチングで底部先端位
置の揃ったＶ溝が形成できる方法としたものである．
詳しくは、単結晶半導体基板の第１の主表面側に第１の
絶縁膜を被着した後、これをバターニングし、浅い島の
底面予定領域上と、■溝形成予定頷城の周囲の所望の幅
の領域にのみ第１の絶縁膜を残す．その第１の絶縁膜が
選択的に残存する前記基板の第１の主表面側全面に半導
体層を形成する．その半導体層上に第２の絶縁膜を被着
し、バターニングすることにより、この第２の絶縁膜を
浅い島形成予定領域および深い島形成予定領域にのみ残
し、Ｖ溝形成予定領域からは除去するか、あるいは、深
い島形成予定領域にのみ残して、■溝形或予定領域およ
び浅い島形成予定領域から除去する．その後、残存第２
の絶縁膜をマスクに半導体層の異方性エッチングを行い
、その異方性エッチングが前記第１の絶縁膜に到達した
ならば、この第１の絶縁膜を新たなマスクとして基板の
異方性エッチングを続けることにより、半導体層および
基板に分離用Ｖ溝を形成する．その後、第２の絶縁膜お
よび露出した第１の絶縁膜を除去した後、Ｖ溝を含む第
１の主表面側全体に第３の絶縁膜を被着し、その上に支
持体層を形戒する．その後、半導体基板を第２の主表面
側より前記Ｖ溝の底部先端が露出するまで研磨除去する
．（作 用）
上記のこの発明においては、例えば第１図に示すように
、浅い島の底面予定領域に残存させた第ｉの絶縁膜下（
第１図（ｅ）では上）の基板部で浅い島が形成され、か
つ基板部と半導体層で深い島が形成される．また、製造
途中において凹部の形成は全くなく、絶縁膜のパターニ
ングもすべて平面上で行われる．さらに、異方性エッチ
ングは唯一回であり、しかもこの異方性エッチング（Ｖ
溝形ｔｃ＞においては、途中から第ｌの絶縁膜を新たな
マスクとしてＶ溝底部のエッチングが行われる．（実施
例）
第１図（ａ）〜（ｅ）はこの発明の一実施例を示す工程
断面図であり、以下この図に基づき一実施例を説明する
．
まず第１図（ａ）に示すように、（１０（ｃ）面を有す
る単結晶Ｓｉ基板１ｌの主表面に酸化１１１２を被着し
、この酸化ＷＡ１２をフォト・エッチング工程によりバ
ターニングして、後に浅い島の底面となる領域ｌ３上と
、Ｖ溝形成予定領域１４の周囲の所定幅Ｗの領域にのみ
酸化８１２を残す．ここで、■溝形戒予定ｆＩＪｌ域ｌ
４の開口幅は、後のＶ溝形戒の際、所望する浅い島の島
厚に相当する■溝深さが得られる幅としておく．又、Ｖ
溝形成予定領域１４の周囲の酸化膜ｌ２の幅Ｗは、後の
Ｖ溝形戒の後のマスク合わせ余裕程度でよく、、出来る
だけ小さい方が望ましい．この実施例では、■溝形成予
定領域１４の開口幅は３６μ，その周囲の酸化ｒＰＡ１
２の幅Ｗは６μとした．なお、浅い島底面予定領域ｌ３
の酸化膜ｌ２の端部は、■溝形或予定ｌ′ｌ域１４の周
囲の幅Ｗの一対の酸化ＷＡ１２の一方を兼ねるといえる
．
次に、第１図（ハ）に示すように、前記酸化膜ｌ２が選
択的に残存する単結晶Ｓ＋基板１１の主表面側全面に、
該単結晶ＳＩ基板１ｌと同じ導電型で同じ比抵抗のエビ
タキシャル層１５を威長させる．ここで、エビタキシャ
ル層ｌ５の厚みは、所望する深い島の島厚と浅い島の島
厚の差分とし、この実施例では２０−とした．又、エビ
タキシャル層１５は、酸化膜１２上においても単結晶膜
であることが望ましく、そのため威長に際しては、例え
ば「月刊セミコンダクタ・ワールド（Ｓｅｗ ｉｃｏｎ
ｄｕｃ ｔｏｒ１１ｏｒｌｄ） Ｊ １９Ｂ８年ｌＯ月
号Ｐ３３ 〜４０の最新技術情報で紹介されているよう
なＳ１選択エビ技術およびＥ Ｌ Ｏ （ｅｐｉｔａｘ
ｉａｌ ｌａｔｅｒａｌ ｏｖｅｒｇｒｏｗｔｈ）技術
を用いて行い目的のエビタキシャル層を得るのが望まし
い．ただし、浅い島底面予定領域１３の幅広の酸化１１
１１２の中央部上においては、単結晶膜でなくて多結晶
膜であってもかまわない．次に第１図（Ｃ）に示すよう
に、エビタキシ中ル層ｌ５の表面上に酸化膜ｌ６を被着
した後、この酸化膜ｌ６をフォト・エッチング工程によ
りバターニングし、この酸化１１１１６を浅い島形成予
定領域ｌ７および深い島形成予定ｅＪＩＪａｔｌ−８に
のみ残し、Ｖ溝形成予定領域１４′からは除去する．し
かる後、この残存酸化ＩＦＪ１６をマスクとして、Ｋｏ
ｎ Ｉ液等によるアルカリ異方性エッチングを同第１図
（Ｃ）に示すようにエビタヰシャル層ｌ５および単結晶
ＳＩ基板１１に対して行い、■溝ｌ９を形成する．この
時、エッチングは、エビタキシャル層ｌ５のエッチング
を終了した途中において酸化１ｌ！１２に到達し、その
時点からは該酸化８１２を新たなマスクとして基板１１
のエッチングが続き、■溝底部が形成される．
次に、エッチングマスクとして使用した酸化膜１６及び
露出した酸化膜ｌ２を除去した後、第１図（ｄ）に示す
ように、Ｖ７１１１１９の内壁を含むエピタ゛キシャル
層ｌ５の表面に酸化Ｍ２０を被着し、さらにその上に支
持体となる多結晶Ｓｔ層２ｌを初期材料の単結晶ｓｉ基
板１１と同程度の厚さに形成する．
しかる後、第１図（ｅ）に示すように、単結晶Ｓｔ基板
１１を反対主表面側よりＶ溝１９の底部先端が露出する
まで研磨する．これにより、第１図Ｏの浅い島形成予定
領域１７部分の単結晶Ｓｔ碁板１１は、底面部が酸化１
１１２、側面部が酸化膜２０により他と完全に分離され
て、第１図（ｅ）に示すように浅い島２２ｂとなる．同
時に、第１図（Ｃ）の深い島形成予定領域１８部分のエ
ビタキシ中ル層１５と単結晶Ｓｔ基板１１は、底面部お
よび側面部の両方が酸化膜２０により他と完全に分離さ
れて、第１図（ｅ）に示すように深い島２２ａとなる．
そして、この深い島２２ａと浅い島２２ｂを同一基板内
に有する誘電体分離基板が完處することになる．なお、
上述したー実施例では、浅い島形成予定領域１７にも酸
化１ｌＩ１６をマスクとして残して、第１図（ｅ）での
アルカリ異方性エッチング（Ｖ溝形或）の際、浅い島形
成予定領域ｌ７のエビタキシャル層ｌ５をエッチング除
去しなかったが、この領域１７のマスクとしての酸化膜
１６を除去して、この領域ｌ７のエビタキシ中ル層１５
は、酸化膜１２をストッパーにして除去してもかまわな
い．又、完成後の深い島２２ａ中に酸化＠１２が両壁に
僅かに残った形となるが、形成される素子の空乏層がこ
の部分に当らない限り問題はない．（発明の効果）
以上のようにこの発明の製造方法によれば、従来行って
いた凹部の形戒及び段差のある凹部内でのパターニング
といった工程は全ぐ不要となり、しかも、異方性エッチ
ング（Ｖ溝形成）の途中から、最初の段階で予め形成し
ておいた第１の絶縁膜を新たなマスクとしてＶ溝底部の
形戒を行うようにしたので、Ｖ溝底部先端位置のバラツ
キを確実に無《すことができる．したがって、深い島と
浅い島の両方ともを同一基板内に精度よく形成でき、歩
留りを向上させることができる．また、この発明の方法
は異方性エッチングが１回だけですみ、上記のような高
精度の誘電体分＋＊碁板を容易゛に形成できる．DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a dielectrically isolated substrate having single crystal semiconductor islands of different depths within the same substrate. (Prior art) In a semiconductor integrated circuit device having a dielectric isolation structure,
The high withstand voltage element and the low withstand voltage element are made of the same dielectric material.
When mixed on a board, the island where the high breakdown voltage element is formed is deepened according to the depletion layer radiation during reverse bias, and the island where the low breakdown voltage element is formed is made to reduce the collector resistance of the vertical NPN transistor. Attempts have been made to optimize the depth of the island according to the characteristics of the built-in elements, such as making the island shallower. A method of manufacturing a dielectric separation substrate in which deep islands and shallow islands are mixedly mounted on the same substrate is described in Japanese Patent Application Laid-Open No. 55-1991 as an example of a known document.
- No. 105340, and as described in this document, it is formed by performing two or more stages of anisotropic etching. The manufacturing method will be explained below with reference to the process cross-sectional diagrams shown in FIG. 2 (ω to (e)). First, as shown in FIG. After forming an oxide film 2 on the main surface side of the substrate l and buttering it, using the oxide film 2 as an etching mask, a recess 3 with a desired depth is formed on the substrate l using an alkali anisotropic etching technique. Next, as shown in FIG. 2(c), after removing the oxide I12, an oxide film 4 is newly deposited on the main surface of the substrate 1 including the recesses 3, and this is applied using photo-etching technology. Then, using the patterned oxide film 4 as a mask, a second pattern is formed as shown in the figure.
The substrate 1 is subjected to alkali anisotropic etching in the same manner as shown in Fig. 2(a), and grooves 5 are formed as shown in Fig. 2(C). Next, as shown in FIG. 2(b), after removing the oxide film 4,
An oxide film 6 is deposited on the main surface of the substrate 1 including the V-groove 5, and a polycrystalline H layer 7 serving as a support is formed thereon. Next, the substrate 1 is polished away from the opposite main surface side of the single-crystal fiber substrate 1 until the bottom tip of the V-groove 5 is exposed (to the position of line A-A in FIG. 2(d)). This allows the second
As shown in Figure (e), a deep island 8a and a shallow island 8b made up of the remaining St substrate, which have been completely separated by H6 oxide, are formed in the same substrate, resulting in a completely destroyed dielectric substrate. (Problem III to be solved by the invention) However, in the above conventional manufacturing method, first of all, as shown in FIG.
When forming the concave portion 3 of the grape, the etching speed is high (10G
) surface is left on the bottom surface, which tends to cause variations in the depth of the recess 3, and when patterning the oxidized I14 shown in FIG. As a result, the patterning accuracy of the oxide film 4 within the recess 3 is significantly reduced, and the desired patterning dimension cannot be stably obtained. The bottom tip position of 5 is V at recess 3.
There was a problem in that the groove and the V-groove from the main surface of the substrate were not aligned. Therefore, during the next polishing of the Sl substrate 1, even if the polishing progresses accurately and flatly, the tip of the groove 5 will not be exposed uniformly, and there will be over-polished areas or under-polished areas within the substrate. This was one of the causes of a drop in yield due to the mixture. Furthermore, this conventional method has the trouble of performing alkaline anisotropic etching twice. The present invention has been made in view of the above points, and provides a method for manufacturing a dielectric board, which allows dielectric isolation substrates having single crystal semiconductor islands of different depths to be easily formed with high precision and high yield. The purpose is to provide the following. (Means for Solving the Problems) The present invention provides a method for manufacturing a dielectric isolation substrate having single crystal semiconductor islands of different depths, which does not require the formation of recessed portions and can be performed using a single alkali anisotropic etching process. This method allows the formation of V-grooves with the bottom tips aligned. Specifically, after a first insulating film is deposited on the first main surface side of a single crystal semiconductor substrate, this is buttered to form a layer on the bottom area of the shallow island and around the nodule where the groove is planned to be formed. The first insulating film is left only in an area of the desired width. A semiconductor layer is formed on the entire first main surface side of the substrate where the first insulating film selectively remains. By depositing a second insulating film on the semiconductor layer and buttering it, the second insulating film is left only in the shallow island formation area and the deep island formation area, and from the V-groove formation area. Either remove it, or leave it only in the region where deep islands are expected to be formed, and remove it from the groove-shaped region and the region where shallow islands are expected to be formed. After that, the remaining second
Anisotropic etching of the semiconductor layer is performed using the insulating film as a mask, and once the anisotropic etching reaches the first insulating film, the anisotropic etching of the substrate is performed using the first insulating film as a new mask. By continuing etching, a V-groove for isolation is formed in the semiconductor layer and substrate. After that, after removing the second insulating film and the exposed first insulating film, a third insulating film is deposited on the entire first main surface side including the V-groove, and a support layer is formed on top of the third insulating film. I warn you. Thereafter, the semiconductor substrate is polished away from the second main surface side until the bottom tip of the V-groove is exposed. (Function) In the above invention, as shown in FIG. 1, for example, under the i-th insulating film (
In FIG. 1(e), a shallow island is formed in the substrate portion (above), and a deep island is formed in the substrate portion and the semiconductor layer. Additionally, no recesses are formed during manufacturing, and the patterning of the insulating film is all done on a flat surface. Furthermore, anisotropic etching is performed only once, and this anisotropic etching (V
In the groove shape tc>, the bottom of the V-groove is etched using the lth insulating film as a new mask from the middle. (Example) FIGS. 1(a) to 1(e) are process sectional views showing one embodiment of the present invention, and one embodiment will be described below based on these figures. First, as shown in FIG. 1(a), oxide 1112 is deposited on the main surface of a single crystal Si substrate 1l having a (10(c) plane), and this oxidized WA 12 is patterned by a photo-etching process. Oxidation 812 is left only on the region l3 that will later become the bottom surface of the shallow island and on a region of a predetermined width W around the V-groove formation region 14. Here,
The width of the opening in step 4 should be such that a groove depth corresponding to the desired thickness of the shallow island can be obtained when forming the V-groove shape later. Also, V
The width W of the oxide film l2 around the region 14 where the groove is to be formed may be the same as the mask alignment margin after forming the V-groove, and is preferably as small as possible. In this example,
The width W of 2 was 6μ. In addition, the shallow island bottom planned area l3
It can be said that the end of the oxide film l2 serves as one of the pair of oxides WA12 having a width W around the groove-shaped or planned l'l area 14. Next, as shown in FIG. 1(c), on the entire main surface side of the single crystal S+ substrate 11 where the oxide film l2 selectively remains,
The epitaxial layer 15 having the same conductivity type and the same resistivity as the single-crystal SI substrate 1l is enhanced. Here, the thickness of the epitaxial layer l5 is the difference between the desired thickness of the deep island and the thickness of the shallow island, and in this example, it is set to 20-. Further, it is preferable that the epitaxial layer 15 is a single crystal film even on the oxide film 12, and therefore, for example, "Monthly Semiconductor World"
S1 selected shrimp technology and E L O (epitax
ial lateral overgrowth) technique to obtain the desired epitaxial layer. However, the wide oxidation 11 of the planned shallow island bottom area 13
112 may be a polycrystalline film instead of a single crystalline film. Next, as shown in FIG. 1(C), after depositing an oxide film l6 on the surface of the epitaxy intermediate layer l5, this oxide film l6 is buttered by a photo-etching process, and this oxide film 11116 is formed into a shallow layer. It is left only in the planned island formation region l7 and deep island formation planned eJI Jatl-8, and is removed from the V groove formation planned region 14'. After that, using this remaining oxidized IFJ16 as a mask, Ko
As shown in FIG. 1(C), alkaline anisotropic etching using an I solution or the like is performed on the epitaxial layer 15 and the single-crystal SI substrate 11 to form a groove 19. At this time, the etching is performed by oxidizing 1l! in the middle of completing the etching of the epitaxial layer 15! 12, and from that point on, the substrate 11 is coated using the oxidation 812 as a new mask.
Etching continues, and the groove bottom is formed. Next, after removing the oxide film 16 used as an etching mask and the exposed oxide film l2, oxide M20 is deposited on the surface of the epitaxial layer l5 including the inner wall of V711119, as shown in FIG. 1(d). Further, a polycrystalline St layer 2l serving as a support is formed thereon to a thickness comparable to that of the single crystal Si substrate 11 as the initial material. Thereafter, as shown in FIG. 1(e), the single-crystal St substrate 11 is polished from the opposite main surface side until the bottom tip of the V-groove 19 is exposed. As a result, the bottom surface of the monocrystalline St Go board 11 in the shallow island formation area 17 shown in FIG.
112, the side surface is completely separated from the others by the oxide film 20, forming a shallow island 22b as shown in FIG. 1(e). At the same time, both the bottom and side surfaces of the epitaxy core layer 15 and the single-crystal St substrate 11 in the deep island formation region 18 portion of FIG. As shown in FIG. 1(e), this becomes a deep island 22a.
Then, a dielectric isolation substrate having the deep island 22a and the shallow island 22b in the same substrate is completed. In addition,
In the above-mentioned embodiment, 1lI16 oxide is left as a mask in the area 17 where the shallow island is to be formed, and during the alkali anisotropic etching (V-groove type or the like) shown in FIG. Although the epitaxial layer 15 of 17 was not removed by etching, the oxide film 16 serving as a mask in this region 17 was removed, and the epitaxial layer 15 of this region 17 was removed by etching.
may be removed using the oxide film 12 as a stopper. In addition, a small amount of oxide @12 remains on both walls of the deep island 22a after completion, but there is no problem as long as the depletion layer of the element to be formed does not hit this part. (Effects of the Invention) As described above, according to the manufacturing method of the present invention, the conventional steps of determining the shape of the recess and patterning within the stepped recess are completely unnecessary, and furthermore, anisotropic etching ( From the middle of the V-groove formation, the shape of the V-groove bottom was determined using the first insulating film that had been previously formed in the first stage as a new mask, ensuring that the position of the V-groove bottom tip did not vary. It is possible to eliminate it. Therefore, both deep islands and shallow islands can be formed on the same substrate with high precision, and the yield can be improved. Furthermore, the method of the present invention requires only one anisotropic etching process, making it possible to easily form a highly accurate dielectric board as described above.
第１図はこの発明の誘電体分離基板の製造方法の一実施
例を示す工程断面図、第２図は従来の銹電体分離基板の
製造方法を示す工程断面図である．１ｌ・・・単結晶Ｓ
ｉ基板、ｌ２・・・酸化膜、ｌ３・・・浅い島底面予定
領域、ｌ４・・・Ｖ溝形戒予定領域、１５・・・エビタ
キシャル層、ｌ６・・・酸化膜、ｌ７・・・浅い島形成
予定領域、ｌ８・・・深い島形成予定領域、ｌ９・・・
Ｖ溝、２０・・・酸化膜、２１。・・・多結晶Ｓｉ層、
２２ａ・・・深い島、２２ｂ・・・浅い島．第１図FIG. 1 is a process sectional view showing an embodiment of the method for manufacturing a dielectric isolation substrate of the present invention, and FIG. 2 is a process sectional view showing a conventional method for manufacturing a dielectric isolation substrate. 1l...Single crystal S
i-substrate, l2... oxide film, l3... shallow island bottom planned area, l4... V groove shaped predetermined area, 15... epitaxial layer, l6... oxide film, l7... Shallow island formation planned area, l8...Deep island formation planned area, l9...
V groove, 20... oxide film, 21. ...polycrystalline Si layer,
22a...deep island, 22b...shallow island. Figure 1
Claims (1)
着した後、これをパターニングし、浅い島の底面予定領
域上と、Ｖ溝形成予定領域の周囲の所望の幅の領域にの
み第１の絶縁膜を残す工程と、（ｂ）その第１の絶縁膜
が選択的に残存する前記基板の第１の主表面側全面に半
導体層を形成する工程と、 （ｃ）その半導体層上に第２の絶縁膜を被着し、パター
ニングすることにより、この第２の絶縁膜を浅い島形成
予定領域および深い島形成予定領域にのみ残し、Ｖ溝形
成予定領域からは除去するか、あるいは、深い島形成予
定領域にのみ残して、Ｖ溝形成予定領域および浅い島形
成予定領域から除去する工程と、 （ｄ）その後、残存第２の絶縁膜をマスクに半導体層の
異方性エッチングを行い、その異方性エッチングが前記
第１の絶縁膜に到達したならば、この第１の絶縁膜を新
たなマスクとして基板の異方性エッチングを続けること
により、半導体層および基板に分離用Ｖ溝を形成する工
程と、 （ｅ）その後、第２の絶縁膜および露出した第１の絶縁
膜を除去した後、Ｖ溝を含む第１の主表面側全体に第３
の絶縁膜を被着し、その上に支持体層を形成する工程と
、 （ｆ）その後、半導体基板を第２の主表面側より前記Ｖ
溝の底部先端が露出するまで研磨除去する工程とを具備
してなる誘電体分離基板の製造方法。[Scope of Claims] (a) After depositing a first insulating film on the first main surface side of a semiconductor substrate, this is patterned to form a region on the bottom of the shallow island and a region where a V-groove is to be formed. (b) forming a semiconductor layer over the entire first main surface side of the substrate where the first insulating film selectively remains; (c) Depositing a second insulating film on the semiconductor layer and patterning it, leaving this second insulating film only in the shallow island formation area and the deep island formation area, and forming a V-groove. (d) removing the remaining second insulating film from the region where the island is to be formed, or leaving it only in the region where the deep island is to be formed, and removing it from the region where the V-groove is expected to be formed and the region where the shallow island is expected to be formed; Performing anisotropic etching of the semiconductor layer using the mask, and once the anisotropic etching reaches the first insulating film, continue anisotropic etching of the substrate using the first insulating film as a new mask. (e) After that, after removing the second insulating film and the exposed first insulating film, the first main surface side including the V-groove is removed. 3rd overall
(f) After that, the semiconductor substrate is heated from the second main surface side to the above-mentioned V
A method for manufacturing a dielectric isolation substrate, comprising the step of polishing and removing the bottom tips of the grooves until they are exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15689989A JPH0323648A (en) | 1989-06-21 | 1989-06-21 | Manufacture of dielectric isolation substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15689989A JPH0323648A (en) | 1989-06-21 | 1989-06-21 | Manufacture of dielectric isolation substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0323648A true JPH0323648A (en) | 1991-01-31 |
Family
ID=15637830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15689989A Pending JPH0323648A (en) | 1989-06-21 | 1989-06-21 | Manufacture of dielectric isolation substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0323648A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009144537A (en) * | 2007-12-12 | 2009-07-02 | Mazda Motor Corp | Front structure of vehicle |
-
1989
- 1989-06-21 JP JP15689989A patent/JPH0323648A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009144537A (en) * | 2007-12-12 | 2009-07-02 | Mazda Motor Corp | Front structure of vehicle |
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