JPH03231472A - Manufacture of thin-film transistor - Google Patents

Manufacture of thin-film transistor

Info

Publication number
JPH03231472A
JPH03231472A JP2026824A JP2682490A JPH03231472A JP H03231472 A JPH03231472 A JP H03231472A JP 2026824 A JP2026824 A JP 2026824A JP 2682490 A JP2682490 A JP 2682490A JP H03231472 A JPH03231472 A JP H03231472A
Authority
JP
Japan
Prior art keywords
gate insulating
insulating film
gas
sputtering
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2026824A
Other languages
Japanese (ja)
Other versions
JP2585118B2 (en
Inventor
Kouyuu Chiyou
宏勇 張
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2026824A priority Critical patent/JP2585118B2/en
Priority to EP91101533A priority patent/EP0445535B1/en
Priority to DE69107101T priority patent/DE69107101T2/en
Priority to KR1019910001992A priority patent/KR950010282B1/en
Publication of JPH03231472A publication Critical patent/JPH03231472A/en
Priority to US07/966,607 priority patent/US6586346B1/en
Application granted granted Critical
Publication of JP2585118B2 publication Critical patent/JP2585118B2/en
Priority to US10/459,430 priority patent/US6960812B2/en
Priority to US11/229,651 priority patent/US7301211B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To manufacture a thin-film transistor having a good characteristic by a low-temperature process by a method wherein a gate insulating film is formed by a sputtering method under an atmosphere in which an oxidizing gas is more than an inert gas. CONSTITUTION:A gate insulating film is formed by a sputtering method. It is desirable that the ratio of an inert gas in a gas used for the sputtering is 50% or lower, especially 20vol.% or lower. That is to say, the gate insulating film is manufactured by executing the sputtering method under an atmosphere in which an oxidizing gas is more than the inert gas. As the sputtering method, an RF sputtering method, a DC sputtering method or the like can be used. As the oxidizing gas, oxygen, ozone, nitrous oxide or the like can be enumerated. Especially, when ozone or oxygen is used, it is possible to obtain the gate oxide film which is very good.

Description

【発明の詳細な説明】 「産業上の利用分野」 本発明は、液晶デイスプレー、イメージセンサ−等に適
用可能な薄膜トランジスタの作製方法に関する。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a method for manufacturing a thin film transistor applicable to liquid crystal displays, image sensors, and the like.

「従来の技術」 最近、化学的気相法等によって、作製された非単結晶半
導体薄膜を利用した薄膜トランジスタが注目されている
。"Prior Art" Recently, thin film transistors using non-single crystal semiconductor thin films fabricated by chemical vapor deposition or the like have been attracting attention.

この薄膜トランジスタは、絶縁性基板上に前述の如く化
学的気相法等を用いて形成されるので、その作製雰囲気
温度が最高で４５０°Ｃ程度と低温で形成でき、安価な
ソーダガラス、ホウケイ酸ガラス等を基板として用いる
ことができる。Since this thin film transistor is formed on an insulating substrate using a chemical vapor phase method as mentioned above, it can be formed at a low temperature of about 450°C at maximum, and it can be formed using inexpensive soda glass or borosilicate. Glass or the like can be used as the substrate.

この薄膜トランジスタは電界効果型であり、いわゆるＭ
ＯＳＦＥＴと同様の機能を有しているが、前述の如く安
価な絶縁性基板上に低温で形成でき、さらにその作製す
る最大面積は薄膜半導体を形成する装置の寸法にのみ限
定されるもので、容易に大面積基板上にトランジスタを
作製できるという利点を持っていた。このため多量の画
素を持つマトリクス構造の液晶デイスプレーのスイッチ
ング素子や一次元又は二次元のイメージセンサ等のスイ
ッチング素子として極めて有望である。This thin film transistor is a field effect type, so-called M
It has the same function as an OSFET, but as mentioned above, it can be formed at low temperature on an inexpensive insulating substrate, and the maximum area that can be manufactured is limited only by the dimensions of the device that forms the thin film semiconductor. It had the advantage that transistors could be easily fabricated on large-area substrates. Therefore, it is extremely promising as a switching element for matrix-structured liquid crystal displays having a large number of pixels, one-dimensional or two-dimensional image sensors, and the like.

また、この薄膜トランジスタを作製するにはすでに確立
された技術であるフォトリソグラフィーが応用可能で、
いわゆる微細加工が可能であり、ＩＣ等と同様に集積化
を図ることも可能であった。In addition, photolithography, which is an already established technology, can be applied to fabricate this thin film transistor.
So-called microfabrication was possible, and it was also possible to integrate it like ICs and the like.

この従来より知られたＴＰＴの代表的な構造を第２図に
概略的に示す。A typical structure of this conventionally known TPT is schematically shown in FIG.

（２０）はガラスよりなる絶縁性基板であり、（２１）
は非単結晶半導体よりなる薄膜半導体、（２２）　、　
（２３）はソースドレイン領域で、（２４）　、　（２
５）はソースドレイン電極、（２６）はゲイト絶縁膜で
（２７）はゲイト電極であります。(20) is an insulating substrate made of glass, (21)
is a thin film semiconductor made of a non-single crystal semiconductor, (22),
(23) is the source/drain region, (24), (2
5) is the source/drain electrode, (26) is the gate insulating film, and (27) is the gate electrode.

このように構成された薄膜トランジスタはゲイト電極（
２７）に電圧を加えることにより、ソースドレイン（２
２）　、　（２３）間に流れる電流を調整するものであ
ります。A thin film transistor configured in this way has a gate electrode (
By applying a voltage to source-drain (27),
2) and (23) to adjust the current flowing between them.

このような薄膜トランジスタに用いられるゲイト酸化膜
は、半導体材料の直接熱酸化法、減圧または常圧下での
熱ＣＶＤ法等によって作製されていた。Gate oxide films used in such thin film transistors have been manufactured by direct thermal oxidation of semiconductor materials, thermal CVD under reduced pressure or normal pressure, and the like.

この薄膜トランジスタの素子特性は、チャネルが形成さ
れる部分の半導体膜の膜質と、ゲイト絶縁膜の特性に大
きく左右される。The device characteristics of this thin film transistor are greatly influenced by the film quality of the semiconductor film in the portion where the channel is formed and the characteristics of the gate insulating film.

特に良好な膜質のゲイト絶縁膜を作製することが強く望
まれていた。It has been strongly desired to produce a gate insulating film with particularly good film quality.

前述の方法により、作製されたゲイト絶縁膜を薄膜トラ
ンジスタに用いて良好な素子特性を得るためには、ゲイ
ト絶縁膜の作製温度を６００″Ｃ付近に設定する必要が
あり、そのため結晶化ガラス。In order to obtain good device characteristics by using the gate insulating film produced by the above method in a thin film transistor, it is necessary to set the manufacturing temperature of the gate insulating film to around 600''C, and therefore, crystallized glass is used.

石英ガラス等の非常に高価な基板材料を使用しなければ
ならなかった。すなわち、４５０°Ｃ程度の低温プロセ
スで作製でき、その結果安価な基板材料（ソーダガラス
等）を使用できる薄膜トランジスタの特徴をなくすもの
であった。Very expensive substrate materials such as quartz glass had to be used. That is, it eliminates the characteristics of thin film transistors, which can be manufactured by a low-temperature process of about 450° C. and, as a result, can use inexpensive substrate materials (soda glass, etc.).

また低温にてゲイト絶縁物を作製する方法として、プラ
ズマＣＶＤ法やスパッタリング法が知られているが、い
ずれの方法においても、出発材料中に含まれ、かつ反応
中にも存在する原子（例えばＡｒ、Ｃ１，Ｆ、Ｎ等）が
、ディト絶縁膜中に多数取り込み膜中の固定電荷発生の
原因となる。さらに、反応中に存在する原子のイオン種
が、薄膜トランジスタの活性層表面に衝突し、ゲイト絶
縁膜と活性層との界面近傍に界面準位を形成し、いずれ
の場合も良好な薄膜トランジスタの特性を得るに至って
いない。Additionally, plasma CVD and sputtering methods are known as methods for producing gate insulators at low temperatures, but in both methods, atoms contained in the starting materials and also present during the reaction (for example, Ar , C1, F, N, etc.) are incorporated into the Dito insulating film, causing the generation of fixed charges in the film. Furthermore, the ionic species of atoms present during the reaction collide with the surface of the active layer of the thin film transistor, forming an interface state near the interface between the gate insulating film and the active layer, and in either case, good characteristics of the thin film transistor are maintained. I haven't gotten it yet.

さらに、光ＣＶＤ法によってゲイト絶縁膜を作製するこ
とが試みられており、熱酸化膜とほぼ同様レベルの２　
Ｘ　１０”　ｅＶ−’ｃｍ−”程度の界面準位密度が得
られているが、膜作製に必要とする時間が長く（成膜速
度が非常に遅い）工業的な応用には不向きであった。Furthermore, attempts have been made to fabricate a gate insulating film using the photo-CVD method, which has a level of 2.
Although an interface state density of approximately .

「本発明の目的」 本発明は、従来の問題点を解決する方法であり、良好な
特性の薄膜トランジスタを低温プロセスで作製する方法
を提供するものであります。``Objective of the present invention'' The present invention is a method for solving the problems of the conventional method, and provides a method for manufacturing thin film transistors with good characteristics using a low-temperature process.

「発明の構成」 本発明の構成は、薄膜トランジスタを作製する工程にお
いて、ゲイト絶縁膜の作製をスパッタリング法にて行な
い、さらにスパッタリングに用いる気体における不活性
ガスの割合を５０％以下、すなわち酸化性ガスの方が不
活性ガスより多い雰囲気下でスパッタリングを行ないゲ
イト絶縁膜を作製することを特徴とするものであります
。"Structure of the Invention" The structure of the present invention is that in the process of fabricating a thin film transistor, a gate insulating film is fabricated by a sputtering method, and the proportion of an inert gas in the gas used for sputtering is 50% or less, that is, an oxidizing gas. The feature of this method is that the gate insulating film is fabricated by sputtering in an atmosphere containing more than inert gas.

本発明に用いられるスパッタリング法としては、ＲＦス
パッタ、直流スパッタ等いずれの方法も使用できるが、
スパッタリングターゲットが導電率の悪い酸化物２例え
ば５ｉ０２等の場合、安定した放電を持続するためにＲ
Ｆマグネトロンスパッタ法を用いることが好ましい。As the sputtering method used in the present invention, any method such as RF sputtering or DC sputtering can be used.
When the sputtering target is an oxide 2 with poor conductivity, such as 5i02, R
It is preferable to use F magnetron sputtering.

また酸化性気体としては酸素、オゾン、亜酸化窒素等を
挙げることができるが、特にオゾンや酸素を使用した場
合、ゲイト絶縁膜中に取り込まれる不用な原子が存在し
ないので、非常に良好なゲイト絶縁膜を得ることができ
た。In addition, oxygen, ozone, nitrous oxide, etc. can be cited as oxidizing gases, but especially when ozone or oxygen is used, there are no unnecessary atoms incorporated into the gate insulating film, so the gate insulation film is very good. We were able to obtain an insulating film.

またオゾンは、Ｏラジカルに分解されやす（、単位体積
当りの０ラジ力ル発生量が多く、成膜速度向上に寄与す
ることができる。Further, ozone is easily decomposed into O radicals (and generates a large amount of 0 radicals per unit volume), which can contribute to improving the film formation rate.

従来より行なわれてきたスパッタリング法によるゲイト
絶縁膜の作製においては、不活性ガスであるＡｒが酸素
ガスより多く、通常は酸素が０〜１０体積％程度で作製
されていた。すなわち、従来から行なわれていたスパッ
タは、Ａｒがターゲット材料をたたき成膜することが当
然の如く考えられていた。これはＡｒ等の不活性ガスが
ターゲット材料をたたき出す確率（スパッタリングイー
ルド）が高い為であった。本発明者らは、スパッタリン
グ法によって作製されたゲイト絶縁膜の特性について鋭
意検討した結果、ゲイト絶縁膜の性能を示す活性層とゲ
イト絶縁膜界面の界面準位、及びゲイト絶縁膜中の固定
電荷の数を反映するフラットバンド電圧の理想値よりの
ズレが、スパッタリング時の静ガスの割合に大きく依存
することが判明した。In the production of gate insulating films by the conventional sputtering method, the amount of Ar, which is an inert gas, is greater than that of oxygen gas, and the amount of oxygen is usually about 0 to 10% by volume. That is, in conventional sputtering, it has been thought that Ar strikes a target material to form a film. This is because there is a high probability that an inert gas such as Ar will knock out the target material (sputtering yield). As a result of intensive studies on the characteristics of gate insulating films fabricated by sputtering, the present inventors found that the interface state at the interface between the active layer and the gate insulating film, which indicates the performance of the gate insulating film, and the fixed charge in the gate insulating film It has been found that the deviation from the ideal value of the flat band voltage, which reflects the number of , greatly depends on the proportion of static gas during sputtering.

第３図に、気体に占めるＡｒガスの割合と界面準位の関
係を示す。Ａｒガス１００％に比べ、Ａｒガスの量を酸
化性ガス（第３図では酸素）の量より少なく、５０％以
下とすると界面準位密度が約ｌ／１０程度に減っている
ことがわかり、Ａｒガスの割合が２０％以下の場合は、
はぼ一定の低い界面準位の値となっている。FIG. 3 shows the relationship between the proportion of Ar gas in the gas and the interface level. Compared to 100% Ar gas, it can be seen that when the amount of Ar gas is less than the amount of oxidizing gas (oxygen in Figure 3) and is 50% or less, the interface state density is reduced to about 1/10. If the proportion of Ar gas is less than 20%,
The value of the interface state is almost constant and low.

第４図にスパッタリング時の気体の占める静ガスの割合
とフラットバンド電圧のズレ量との関係を示す。FIG. 4 shows the relationship between the proportion of static gas occupied by gas during sputtering and the amount of deviation in flat band voltage.

フラットバンド電圧の理想電圧からのズレは、Ａｒガス
の割合に太き（依存し、Ａｒガスの割合が２０％以下の
場合、はぼ理想電圧に近い値となっている。The deviation of the flat band voltage from the ideal voltage greatly depends on the proportion of Ar gas, and when the proportion of Ar gas is 20% or less, the value is almost close to the ideal voltage.

これらのことより、スパッタリングにより成膜時に反応
雰囲気下に存在する活性化されたＡｒ原子が、ゲイト絶
縁膜の膜質に影響を与えており、できるだけＡｒ原子の
存在を減らしてスパッタリング成膜することが望ましい
ことが判明した。From these facts, activated Ar atoms present in the reaction atmosphere during film formation by sputtering affect the film quality of the gate insulating film, and it is recommended to reduce the presence of Ar atoms as much as possible during sputtering film formation. It turned out to be desirable.

その理由としては、Ａｒイオン、または活性化されたＡ
ｒ原子が、界面に衝突して界面での欠陥を形成し、更に
ゲイト絶縁膜に取り込まれて固定電荷発生の原因となっ
ていることが考えられる。The reason is that Ar ions or activated A
It is conceivable that the r atoms collide with the interface, form defects at the interface, and are further taken into the gate insulating film, causing the generation of fixed charges.

また酸素原子は、Ａｒ原子と比較して質量が軽いため、
界面近傍に衝突しても、重大なダメージを界面付近に与
えることはない。さらに膜中には、主構成成分なので取
り込まれても、固定電荷発生の原因となることはない。Also, since oxygen atoms have a lighter mass than Ar atoms,
Even if a collision occurs near the interface, no serious damage will be caused to the area near the interface. Furthermore, since it is a main component in the film, even if it is incorporated into the film, it will not cause the generation of fixed charges.

また、スパッタリングに用いる材料は全て高純度のもの
が好ましい、例えば、スパッタリングターゲットは４Ｎ
以上の合成石英または、ＬＳＩの基板に使用される程度
に高純度のシリコン等が最も好ましい。In addition, all materials used for sputtering are preferably of high purity; for example, the sputtering target is 4N
Most preferably, the above-mentioned synthetic quartz or silicon having a high purity enough to be used for LSI substrates is used.

即ち、ゲイト絶縁膜内に存在する不純物を極力少なくす
る必要がある。同様にスパッタリングに使用するガスも
高純度（５Ｎ以上）の物を用い、不純物がゲイト絶縁膜
中に混入することを極力さけた。That is, it is necessary to minimize the amount of impurities present in the gate insulating film. Similarly, the gas used for sputtering was of high purity (5N or higher) to prevent impurities from entering the gate insulating film as much as possible.

以下に実施例により本発明の詳細な説明する。The present invention will be explained in detail below using Examples.

「実施例１１ 第１図に本発明の薄膜トランジスタの作製工程を示す。“Example 11 FIG. 1 shows the manufacturing process of the thin film transistor of the present invention.

本実施例においては、基板材料として安価なソーダガラ
スを基板（１）として用いた。この基板（１）上に公知
のプラズマＣＶＤ法により、■型の非単結晶半導体層（
２）をアイランド状に形成し、第１図（Ａ）の状態を得
る。In this example, inexpensive soda glass was used as the substrate (1). A ■-type non-single crystal semiconductor layer (
2) is formed into an island shape to obtain the state shown in FIG. 1(A).

その作製条件は以下の通りであった。The manufacturing conditions were as follows.

基板温度　　　　　　　　　３５０°Ｃ反応時圧力　　
　　　　　０．０６ＴｏｒｒＲｆパワー（１３，５６Ｍ
　Ｈｚ　）　　１００Ｗ使用ガス　　　　　　　　　Ｓ
ｉＨ。Substrate temperature 350°C reaction pressure
0.06TorrRf power (13,56M
Hz) 100W Gas used S
iH.

膜厚　　　　　　　　　　２０００人 またアイランド状に形成する際本実施例ではメタルマス
クを使用したが、公知のフォトリソグラフィー技術を使
用しても良い。Film thickness: 2000 In addition, in this embodiment, a metal mask was used to form the island shape, but a known photolithography technique may also be used.

次に、第１図（Ｂ）に示すようにエキシマレーザ光（３
）を、非単結晶半導体（２）の素子領域付近に照射して
結晶化し、粒径サイズの大きい多結晶状態、またはほぼ
素子領域に等しいサイズの単結晶状態とする。この時の
エキシマレーザ光の照射条件を以下に示す。Next, as shown in FIG. 1(B), excimer laser light (3
) is irradiated near the device region of the non-single crystal semiconductor (2) to crystallize it into a polycrystalline state with a large grain size or a single crystal state with a size approximately equal to the device region. The irradiation conditions of excimer laser light at this time are shown below.

レーザ光波長　　　　　　　　２８４ｒｖ（ＫｒＦ）照
射エネルギー量　　　　　　２００＠Ｊ／ｃｍ”ショツ
ト数　　　　　　　　　　１０ 光パルス巾　　　　　　　　　　３０ｎｓ次に、公知の
プラズマＣＶＤ法により、Ｎ型の非単結晶半導体層を全
面に形成した後、公知のフォトリソグラフィー技術によ
り、ソース、ドレイン領域（４）　、　（５）を残すよ
うにバターニングし、第１図（Ｃ）の状態を得た。Laser light wavelength: 284rv (KrF) Irradiation energy amount: 200@J/cm" Shot number: 10 Light pulse width: 30nsNext, after forming an N-type non-single crystal semiconductor layer on the entire surface by a known plasma CVD method, By photolithography, patterning was performed so as to leave the source and drain regions (4) and (5), resulting in the state shown in FIG. 1(C).

このＮ型非単結晶半導体層の作製条件を以下に示す。The conditions for manufacturing this N-type non-single crystal semiconductor layer are shown below.

基板温度　　　　　　　　　２５０″Ｃ反応時圧力　　
　　　　　０．０５ＴｏｒｒＲｆパワー（１３，５６Ｍ
Ｈ，）　　　　１５０Ｗ使用ガス　　　　　　　５ｉＨ
ｎ　＋　ＰＨ３＋　Ｈ２膜厚　　　　　　　　　　　５
００人 このＮ型非単結晶半導体としては、多量のＨ２ガスに希
釈し、かつＲｆパワーを高くに微結晶化させ、電気抵抗
の低い膜を使用した。Substrate temperature 250″C reaction pressure
0.05TorrRf power (13,56M
H,) 150W gas used 5iH
n + PH3+ H2 film thickness 5
This N-type non-single crystal semiconductor was diluted with a large amount of H2 gas, microcrystallized with high Rf power, and had a low electrical resistance.

次にＲｆスパッタリング法により、ゲイト絶縁膜（６）
を７００人形成し、その後ソースドレインのコンタクト
用穴（７）、　（８）をフォトリソグラフィー技術によ
り形成し、第１図（Ｄ）の状態を得た。Next, a gate insulating film (6) is formed by Rf sputtering method.
After that, the source/drain contact holes (7) and (8) were formed by photolithography to obtain the state shown in FIG. 1(D).

このゲイト絶縁膜の作製条件を以下に示す。The conditions for manufacturing this gate insulating film are shown below.

ターゲット　　　　　５ｉＯｚ　　　９９．９９％反応
ガス　　　　　　０□　　１００％反応圧力　　　　　
　　　　０．５ＰａＲｆパワー　　　　　　　　　５０
０Ｗ基板温度　　　　　　　　　１００″Ｃ基板ターゲ
ツト間距離　　　１５０ｍｍこのゲイト絶縁膜の特性を
以下に示す。Target 5iOz 99.99% reaction gas 0□ 100% reaction pressure
0.5PaRf power 50
0W Substrate temperature 100''C Distance between substrate targets 150mm The characteristics of this gate insulating film are shown below.

１／１１０ＨＦ　ｙチング速度　　６７ｎＩＩＩ／ｍｉ
ｎ絶縁耐圧　　　　　　　　９．１ＭＶ／ｃｍ界面準位
　　　　　２．５Ｘ１０”ｅＶ〜’　ｃｎ＋−”次に、
ゲイト電極（９）、ソース電極（１０）　、　　ドレイ
ン（１１）電極をＡＩにより形成し、薄膜トランジスタ
を完成させた。1/110HF y-ching speed 67nIII/mi
n Dielectric strength voltage 9.1MV/cm Interface state 2.5X10"eV~'cn+-"Next,
A gate electrode (9), a source electrode (10), and a drain (11) electrode were formed using AI to complete a thin film transistor.

このような薄膜トランジスタのスレショルド電圧（ｖｔ
ｈ）は１ｖ以下とすることができ、Ａｒ１０Ｏ％で形成
された同様の素子のｖｔｈが１Ｖ以下にはならなかった
。The threshold voltage (vt
h) could be made below 1V, and vth of a similar element made of 100% Ar did not fall below 1V.

また、ゲイト電圧を一定時間かけ続けた後のｖｔｈの変
化率は、熱酸化によって形成されたゲイト絶縁膜の変化
率と、はぼ同様であり、１０００時間後にわずか０．３
程度しか変化しておらず、ゲイト絶縁膜（６）と非単結
晶半導体（２）界面及び、ゲイト絶縁膜中に局在準位が
ほとんど形成されていないことがわかる。In addition, the rate of change in vth after applying the gate voltage for a certain period of time is almost the same as that of a gate insulating film formed by thermal oxidation, and is only 0.3 after 1000 hours.
It can be seen that there is only a slight change, and that almost no localized levels are formed at the interface between the gate insulating film (6) and the non-single crystal semiconductor (2) and in the gate insulating film.

また、この本発明の薄膜トランジスタの移動度は１００
ｃｍ２／Ｖ−Ｓが得られた。Further, the mobility of the thin film transistor of the present invention is 100
cm2/V-S was obtained.

本実施例においては、ゲイト絶縁膜形成時のＡｒガスの
割合を０としたが、約２０％以下の割合でＡｒガスが存
在する条件下でゲイト絶縁膜を作製するなら薄膜トラン
ジスタの特性上特に問題は生じなかった。In this example, the ratio of Ar gas when forming the gate insulating film was set to 0, but if the gate insulating film is formed under conditions where Ar gas is present at a ratio of about 20% or less, there is a particular problem in terms of the characteristics of the thin film transistor. did not occur.

ただし、Ａｒの割合をＯとした方がより特性のよい薄膜
トランジスタを得ることができた。However, when the proportion of Ar was set to O, a thin film transistor with better characteristics could be obtained.

また計ガスを２０％以下の割合で混合する場合には、タ
ーゲットと基板との距離を＾ｒガス０％で作製する場合
より長くすることで、はぼ同様の膜質のゲイト絶縁膜を
得ることが可能である。Also, when mixing gas at a ratio of 20% or less, the distance between the target and the substrate is made longer than when fabricating with 0% gas, thereby obtaining a gate insulating film with similar film quality. is possible.

さらにＡｒガス２０％以下の割合で混合して形成したゲ
イト絶縁膜に対し、エキシマレーザ光を照射し、フラッ
シュアニールを施し、膜中に取り込れたＡｒを除去し、
膜中の固定電荷の発生原因を取り除くことも可能であっ
た。Furthermore, the gate insulating film formed by mixing Ar gas at a ratio of 20% or less is irradiated with excimer laser light and flash annealed to remove Ar taken into the film.
It was also possible to eliminate the cause of fixed charges in the film.

この時、エキシマレーザ光より膜に与えるエネルギー量
を多くし、ゲイト絶縁膜のアニールと同時にその下の半
導体層の結晶化を行なうこともでき、作製工程数を減ら
す上で非常に有効な手段であった。At this time, it is possible to increase the amount of energy applied to the film than excimer laser light and simultaneously annealing the gate insulating film and crystallizing the underlying semiconductor layer, which is an extremely effective means of reducing the number of manufacturing steps. there were.

本実施例において、薄膜トランジスタを作製するプロセ
スにて使用した真空装置の排気手段としては全てオイル
等の排気系からの逆拡散のないターボ分子ポンプを使用
し、ゲイト絶縁膜及びその他の半導体層の膜特性に影響
を及ぼさないようにした。In this example, the exhaust means for the vacuum equipment used in the process of manufacturing thin film transistors was a turbo molecular pump that does not back-diffuse oil etc. from the exhaust system, and the gate insulating film and other semiconductor layers were I tried not to affect the characteristics.

「効果」 本発明方法により、低温プロセスのみで非常に特性の良
い薄膜トランジスタを容易に形成することができた。"Effects" According to the method of the present invention, a thin film transistor with very good characteristics could be easily formed using only a low temperature process.

またゲイト絶縁膜中に存在する固定電荷の原因を減らす
ことができたので、長期的な使用において特性変化の少
ない信頼性の良い薄膜トランジスタを提供することが可
能となった。Furthermore, since the cause of fixed charges existing in the gate insulating film can be reduced, it has become possible to provide a highly reliable thin film transistor with little change in characteristics during long-term use.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の作製工程を示す。 第２図は一般的な薄膜トランジスタの概略図を示す。 第３図はゲイト絶縁膜作製時におけるＡｒガスの割合と
界面準位密度の関係を示す。 第４図はゲイト絶縁膜作製時におけるＡｒガスの割合と
フラットバンド電圧のズレ量との関係を示す。FIG. 1 shows the manufacturing process of the present invention. FIG. 2 shows a schematic diagram of a typical thin film transistor. FIG. 3 shows the relationship between the proportion of Ar gas and the interface state density during the fabrication of the gate insulating film. FIG. 4 shows the relationship between the proportion of Ar gas and the amount of deviation in flat band voltage when forming the gate insulating film.

Claims (1)

【特許請求の範囲】 １、薄膜トランジスタを作製する工程においてゲイト絶
縁膜の作製を酸化性気体が不活性気体より多い雰囲気下
でスパッタリング法によって形成されることを特徴とす
る薄膜トランジスタの作製方法。 ２、特許請求の範囲第１項において、前記不活性気体は
２０体積％以下の割合で存在する雰囲気下でゲイト絶縁
膜がスパッタリング法により形成されたことを特徴とす
る薄膜トランジスタの作製方法。[Claims] 1. A method for manufacturing a thin film transistor, characterized in that in the step of manufacturing the thin film transistor, a gate insulating film is formed by sputtering in an atmosphere containing more oxidizing gas than inert gas. 2. The method of manufacturing a thin film transistor according to claim 1, wherein the gate insulating film is formed by sputtering in an atmosphere in which the inert gas is present in a proportion of 20% by volume or less.
JP2026824A 1990-02-06 1990-02-06 Method for manufacturing thin film transistor Expired - Fee Related JP2585118B2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2026824A JP2585118B2 (en) 1990-02-06 1990-02-06 Method for manufacturing thin film transistor
EP91101533A EP0445535B1 (en) 1990-02-06 1991-02-05 Method of forming an oxide film
DE69107101T DE69107101T2 (en) 1990-02-06 1991-02-05 Method of making an oxide film.
KR1019910001992A KR950010282B1 (en) 1990-02-06 1991-02-06 Method of forming an oxide film
US07/966,607 US6586346B1 (en) 1990-02-06 1992-10-26 Method of forming an oxide film
US10/459,430 US6960812B2 (en) 1990-02-06 2003-06-12 Method of forming an oxide film
US11/229,651 US7301211B2 (en) 1990-02-06 2005-09-20 Method of forming an oxide film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2026824A JP2585118B2 (en) 1990-02-06 1990-02-06 Method for manufacturing thin film transistor

Publications (2)

Publication Number Publication Date
JPH03231472A true JPH03231472A (en) 1991-10-15
JP2585118B2 JP2585118B2 (en) 1997-02-26

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