JPH03220720A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH03220720A JPH03220720A JP1493290A JP1493290A JPH03220720A JP H03220720 A JPH03220720 A JP H03220720A JP 1493290 A JP1493290 A JP 1493290A JP 1493290 A JP1493290 A JP 1493290A JP H03220720 A JPH03220720 A JP H03220720A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- gas
- semiconductor device
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000007789 gas Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 9
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 6
- 229910052757 nitrogen Inorganic materials 0.000 claims 3
- 238000005229 chemical vapour deposition Methods 0.000 claims 2
- -1 hydrogen compound Chemical class 0.000 claims 2
- 150000001875 compounds Chemical class 0.000 claims 1
- 230000005672 electromagnetic field Effects 0.000 claims 1
- 239000001257 hydrogen Substances 0.000 claims 1
- 229910052739 hydrogen Inorganic materials 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract description 3
- 239000010953 base metal Substances 0.000 abstract description 2
- 239000012495 reaction gas Substances 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、Ｇ ａ Ａ ｓデバイスのＡｕ系オーミック
電極上のコンタクト埋め込み金属の構造とその製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure of a contact buried metal on an Au-based ohmic electrode of a GaAs device and a method for manufacturing the same.
Ｓｉデバイスの高集積化が進むにつれ、配線技術として
、例えば、特開昭５９−７２１３２に記載されているよ
うに、金属の選択ＣＶＤを用いて、コンタクト孔を選択
的に埋め込む技術が必須になりつつある。選択ＣＶ Ｄ
に用いる金属として、Ｗ。As the integration of Si devices progresses, a technology for selectively filling contact holes using metal selective CVD has become essential as a wiring technology, for example, as described in JP-A-59-72132. It's coming. Selection CV D
W as the metal used for.
（２）
ＡＱ、Ｃｕ等が検討されているが、なかでもＷが最も実
用化に近い。(2) AQ, Cu, etc. are being considered, but W is the closest to practical use among them.
従来技術を用いて、第２図に示すように、半導体基板２
０上に具備されたＡ、 ｕ系電極２１上の絶縁膜２２に
形成されたコンタクト孔２３をＷ膜２４で理め込み、該
Ｗ膜２４上に、Ｓｊ ＵＬＳＩの配線として最も実績の
あるＡＱ膜２５を積層すると、Ａｕ系電極２１中のＡｕ
が、Ｗｌ］’ｆｉ２４を通して、ＡＱ膜２５まで拡散し
、Ａ ｕ ／ Ａ Ｑの合金反応が起こり、配線の信頼
性が低下するという問題が生じた。Using the conventional technique, as shown in FIG.
The contact hole 23 formed in the insulating film 22 on the A, U-based electrode 21 provided on the 0 is insulated with a W film 24, and the AQ, which has the most proven track record as Sj ULSI wiring, is placed on the W film 24. When the film 25 is stacked, the Au in the Au-based electrode 21
However, it diffused to the AQ film 25 through the Wl]'fi 24, causing an alloy reaction of A u /A Q, resulting in a problem that the reliability of the wiring was reduced.
本発明の目的は、上述したような、選択ＷＣＶＤによる
コンタクト孔埋め込み技術において、下地金属の拡散を
著しく低減させることである。An object of the present invention is to significantly reduce the diffusion of underlying metal in the contact hole filling technique using selective WCVD as described above.
ｃｉａｔ題を解決するための手段〕
上記目的を遠戚するために本発明においては選択ｗ−Ｃ
ＶＤでコレクタ孔を埋め込む際に、少なくとも一部をＷ
Ｎ膜化する。Means for solving the problem] In order to achieve the above object, in the present invention, the selection w-C
When filling the collector hole with VD, at least a portion is filled with W.
Forms into N film.
（３）
コンタクト孔を選択的に理め込んだＷ膜において、その
一部分をＷＮ膜化した膜は、Ａｕ等に対するバリア特性
が良好であり、上述した例のように、下地電極材（Ａｕ
）が配線材（ＡＱ）まで拡散することを箸しく低減でき
る。(3) In a W film in which contact holes are selectively embedded, a film in which part of the WN film is formed has good barrier properties against Au, etc.
) can be significantly reduced from diffusing into the wiring material (AQ).
第１実施例
本発明の一実施例を第１図の工程概略間により説明する
。First Embodiment An embodiment of the present invention will be explained with reference to the process outline shown in FIG.
半導体基板１０ 、、ｈにリフトオフ法により形成され
たＡｕ系電極１１上の絶縁膜１２に、通常のりソグラフ
イ技術及びエツチング技術を用いてコンタクト孔１３を
形成した（第１ＩＭ（ａ））。このとき、Ａｕ系電極１
１の最−ｈ層には、ひき続き行うＷ−ＣＶＤの下地材料
となりうるｐｔ （５００λ厚図示略）を用いた。A contact hole 13 was formed in the insulating film 12 on the Au-based electrode 11 formed on the semiconductor substrate 10, . At this time, Au-based electrode 1
For the h-most layer of No. 1, PT (500λ thickness, not shown), which can serve as a base material for the subsequent W-CVD, was used.
上記試料をコードルウオール型減圧ＣＶ Ｉ）装置を用
いて、前記Ａｕ系電極りに選択的にＷ膜（厚さ１００Ｏ
Ａ）１４を堆積した（第１同（ｂ））。The above sample was selectively coated with a W film (thickness 100O
A) 14 was deposited (No. 1 (b)).
ＣＶＤ条件は、全圧０．１５Ｔｏｒｒ基板温度３２０（
４）
’Ｃ，Ｗ Ｆ、 １０ｓｅｃｍ、 Ｓ ｉ Ｈ４６ｓ
ｅｃｍである。ひき続き、上記ＣＶＤ装置のリアクタに
２．４５ＧＨｚのマイクロ波により励起されたＮ、ガス
５０ｓｅｃｍを前記反応ガスに加えた。これにより、第
１図（ｃ）に示すように、ＷＮ膜（２０００Ａ厚）工５
を形成した。次に前記Ｎ２ ガスをリアクタへ流すのを
止めて、Ｗ膜（５０００Ａ厚）１６を堆積した（第工図
（ｄ））。The CVD conditions were a total pressure of 0.15 Torr and a substrate temperature of 320 (
4) 'C, W F, 10sec, S i H46s
It is ecm. Subsequently, 50 seconds of N gas excited by a 2.45 GHz microwave was added to the reaction gas in the reactor of the CVD apparatus. As a result, as shown in FIG. 1(c), the WN film (2000A thickness)
was formed. Next, the flow of the N2 gas to the reactor was stopped, and a W film (5000A thick) 16 was deposited (FIG. (d)).
最後に、該Ｗ膜１６の少なくとも一部を覆うようにＡｕ
膜（７０００入厚）１７を形成した（第１図（ｅ））。Finally, Au is applied so as to cover at least a portion of the W film 16.
A film (7000 mm thick) 17 was formed (FIG. 1(e)).
ここでは、ＷＮ膜の形成をマイクロ波励起したＮ２ ガ
スの導入、しゃ断により、行ったが、Ｎ２ガスを常時導
入しておき、マイクロ波のＯＮ。Here, the WN film was formed by introducing and shutting off N2 gas excited by microwaves, but N2 gas was constantly introduced and the microwave was turned on.
ＯＦＦにより、ＷＮ膜厚を制御できる。By turning it off, the WN film thickness can be controlled.
また、本実施例ではＷＮ膜↓５をＷ膜１４とＷ膜１６の
間に介在させているが、Ｗ膜１４及びＷ膜１６をもＷＮ
膜に置きかえることによりバリア特性を向上させること
が可能であることは言うまでもない。Further, in this embodiment, the WN film ↓5 is interposed between the W film 14 and the W film 16, but the W film 14 and the W film 16 are also
It goes without saying that the barrier properties can be improved by replacing it with a film.
（５）
また、本実施例においてＷＮ膜１５の成膜時に流したＮ
２流量は、５０ｓｅｃｍであるが、少なくともＷＦ６ガ
スの数％以上を流せば、Ｗ Ｎ １１％の成膜は可能で
ある。一方、Ｎ２ の流量の上限は、 ＣＶＤの全ガス
圧が０ 、５ Ｔｏｒｒを超えると、ＣＶＤの選択性が
低下するので、０ 、５ Ｔｏｒｒ以下にするのが好ま
しい。(5) In addition, in this example, the N
2. The flow rate is 50 sec, but if at least several percent of the WF6 gas is flowed, it is possible to form a film with W N of 11%. On the other hand, the upper limit of the flow rate of N2 is preferably set to 0.5 Torr or less, since if the total gas pressure in CVD exceeds 0.5 Torr, the selectivity of CVD will decrease.
第２実施例
第１実施例において、ＷＮ膜１５を形成する際に、マイ
クロ波で励起したＮ２ ガスを導入したが、本実施例で
は、１３．５６ＭＨｚ の高周波により励起したＮ２
ガスを導入した。Second Embodiment In the first embodiment, N2 gas excited by microwaves was introduced when forming the WN film 15, but in this embodiment, N2 gas excited by a high frequency of 13.56 MHz was introduced.
introduced gas.
ここでは、高周波によるプラズマ励起を用いたが、光線
、熱線等のエネルギー線を用いて、Ｎ。Here, plasma excitation by high frequency was used, but energy rays such as light rays and heat rays were used to excite N.
ガスを励起することが可能であることは言うまでもない
。It goes without saying that it is possible to excite the gas.
第３実施例
第３図を用いて、本発明をＧ ａ Ａ ｓ Ｆ Ｅ Ｔ
のコンタクト孔埋め込みに適用した例を説明する。Third Embodiment Using FIG. 3, the present invention will be described.
An example in which this method is applied to contact hole filling will be explained.
Ｇ ａ Ａ ａ Ｆ Ｅ Ｔの基本構造は、半絶縁性Ｇ
ａ Ａ ｓ基（６）
板３０に、Ｓｉのイオン打込みにより形成した能動層３
１とゲート電極３２及びソース、ドレイン電極３３．３
４よりなる。ゲート電極３２は、Ｔ ｉ ／ Ｐ ｔ
／ Ａ ｕのＡｕ系電極或いは、ＷＳｉ等の高融点金属
よりなる。また、ソース、ドレイン電極３３，３４は、
Ａ ｕ Ｇ ｅ ／ Ｎ ｉ ／ Ａ ｕのＡｕ系電極
よりなる。これらの各電極の最上層に、選択Ｗ−ＣＶＤ
の下地金属、例えばｐｔ（図示時）を具備させることに
より、絶縁膜３５に形成したコンタクト孔３６を選択的
にＷ膜３７で埋め込むことができる。また、実施例１〜
２に記載した手法により、引き続きＷＮ膜３８及びＷ膜
３９を堆積して、コンタクト孔３６を設め込んだ。The basic structure of G a A a F E T is a semi-insulating G
a A s group (6) Active layer 3 formed on the plate 30 by Si ion implantation
1 and gate electrode 32 and source and drain electrodes 33.3
Consists of 4. The gate electrode 32 has Ti/Pt
/ Au made of an Au-based electrode or a high melting point metal such as WSi. Further, the source and drain electrodes 33 and 34 are
It consists of an Au-based electrode of AuGe/Ni/Au. Selective W-CVD is applied to the top layer of each of these electrodes.
By providing a base metal such as PT (as shown), the contact hole 36 formed in the insulating film 35 can be selectively filled with the W film 37. In addition, Example 1~
2, a WN film 38 and a W film 39 were subsequently deposited to form a contact hole 36.
然る後に、各電極に対して、ＡＱ配線３１０を形成した
。After that, AQ wiring 310 was formed for each electrode.
本実施例によれば、Ａｕ系電極に対して、ＡＱ配線を適
用することが可能である。従って、Ｇ ａ Ａ ｓ Ｆ
Ｅ ＴにおいてもＳ ｉ Ｕ Ｌ Ｓ Ｉと同程度の集
積化が図れる。According to this embodiment, it is possible to apply AQ wiring to Au-based electrodes. Therefore, G a A s F
ET can achieve the same level of integration as S i U L S I.
第４実施例
（７）
本発明をＧ ａ Ａ ｓ系へテロ接合バイポーラトラン
ジスタのコンタクト孔埋め込みに適用した例を第４同の
素子断面図を用いて説明する。素子の基板構造は、半絶
縁性Ｇ ａ Ａ ｓ基板４０上にｎ生型Ｇ ａ Ａ ｓ
サブコレクタ層４１．ｎ−型Ｇ ａ Ａ ｓコレクタ層
４２．Ｐ＋型Ｇ ａ Ａ ｓベース層４３．ｎ型Ａ Ｑ
Ｇ ａ Ａ ｓエミッタ層４４．ｎ生型Ｇ ａ Ａ
ｓサブエミッタ層４５が積層され、サブコレクタ層４１
、ベース層４３．サブエミツタ層４５上に各各Ａ ｕ
Ｇ ｅ系のコレクタ電極４６．ＡｕＺｕ系のベース電極
４７．ＡｕＧｅ系のエミッタ電極４８を具備している。Fourth Embodiment (7) An example in which the present invention is applied to filling a contact hole of a GaAs-based heterojunction bipolar transistor will be described using a fourth cross-sectional view of the same device. The substrate structure of the device is an n-type GaAs substrate on a semi-insulating GaAs substrate 40.
Sub-collector layer 41. n-type GaAs collector layer 42. P+ type GaAs base layer 43. n-type A Q
GaAs emitter layer 44. n live type G a A
s sub-emitter layer 45 is laminated, and sub-collector layer 41
, base layer 43. Each A u on the sub-emitter layer 45
Ge-based collector electrode 46. AuZu-based base electrode 47. An AuGe-based emitter electrode 48 is provided.
全ての電極の最上層は、Ｈ２２膜の起こりやすい金属膜
、例えばＰｔ、Ｍｏ、Ｗ膜を堆積しである。上記素子を
絶縁膜４９で被覆した後、各電極上にコンタクト孔を形
成し、然る後に、実施例１〜２に述べた本発明により、
前記コンタクト孔を選択的にＷ４１０／ＷＮ４１１／Ｗ
４１２膜で埋め込んである。ＷＮＮ膜上１１下地のＡｕ
系電極４６，４７，４８からのＡｕの拡散を抑制できる
ので、配線材料としてＡＱ配線（８）
４１３が適用できる。これにより、Ｇ ａ Ａ ｓ系へ
テロ接合バイポーラトランジスタの高集積化が可能にな
る。The top layer of all electrodes is a deposited metal film, such as a Pt, Mo, or W film, which is likely to form an H22 film. After covering the above element with an insulating film 49, contact holes are formed on each electrode, and then, according to the present invention described in Examples 1 and 2,
Selectively fill the contact hole with W410/WN411/W.
412 membrane. 11 Au underlayer on WNN film
Since diffusion of Au from the system electrodes 46, 47, and 48 can be suppressed, AQ wiring (8) 413 can be used as the wiring material. This enables highly integrated GaAs-based heterojunction bipolar transistors.
本発明によれば、Ａｕ系電極上のコンタクト孔を選択的
に埋め込んだ金属により、前記Ａｕ系電極からのＡｕ拡
散を低減できるので、金属を埋め込んだコンタクト孔上
に直接ＡＱ配線を適用できる。ＡＱ配線は、微細加工性
及び加工精度に優れており、Ａｕ系電極を有するＧ ａ
Ａ ｓデバイスの高集積化が可能になる。According to the present invention, since the metal selectively filling the contact hole on the Au-based electrode can reduce Au diffusion from the Au-based electrode, AQ wiring can be applied directly over the contact hole filled with metal. AQ wiring has excellent microfabricability and processing accuracy, and has Ga
High integration of As devices becomes possible.
第１図は本発明の第１実施例の半導体装置の製造工程の
概略を示す断面図、第２図は従来法の電極構造を示す断
面図、第３図は本発明の第３実施例の半導体装置の断面
図、第４図は本発明の第４実施例の半導体装置の断面図
。
１０・・・半導体基板、１１・・・Ａｕ系電極、１２・
・・絶縁膜、１３・・・コンタクト孔、１４・・・Ｗ膜
、１５・・・ＷＮ膜、工６・・・Ｗ膜、１７・・・Ａｕ
膜。
（９）
１１８−FIG. 1 is a cross-sectional view showing an outline of the manufacturing process of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view showing an electrode structure of a conventional method, and FIG. FIG. 4 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. DESCRIPTION OF SYMBOLS 10... Semiconductor substrate, 11... Au-based electrode, 12.
...Insulating film, 13...Contact hole, 14...W film, 15...WN film, 6...W film, 17...Au
film. (9) 118-
Claims (1)
の金属面の少なくとも一部が露出するように開孔部が形
成された絶縁膜と、該開孔部に埋め込まれたＷを主成分
とする金属を有してなり、且つ上記Ｗを主成分とする金
属の少なくとも一部に窒素元素を含む金属層が存在する
ことを特徴とする半導体装置。 ２、上述した少なくとも一部に窒素元素を含む金属層を
有するＷを主成分とする金属膜の製法が、Ｗのハロゲン
化ガス、還元性ガスＮを含むガス、を用いた化学気相成
長法であることを特徴とする請求項１に記載した半導体
装置の製造方法。 ３、上記Ｎを含むガスが、Ｎ＿２ガスであり、電磁場に
より励起して、化学気相成長法により、前記窒素元素を
含む金属層を形成することを特徴とする請求項２に記載
した半導体装置の製造方法。 ４、上記Ｗのハロゲン化ガスがＷＦ＿６であり、還元性
ガスが、Ｈ＿２、ＳｉＨ＿４、Ｓｉ＿３Ｈ＿６等の水素
化合物であることを特徴とする請求項２乃至３のいずれ
かに記載した半導体装置の製造方法。 ５、上記半導体層が、ＧａＡｓ等の化合物半導体であり
、上記第１の金属が、Ｐｔ、Ｗ、Ｍｏ、Ｇｅ等のＨ＿２
の吸着しやすい金属であることを特徴とする請求項１記
載の半導体装置。[Claims] 1. A semiconductor substrate, a first metal on the substrate, and a first metal on the substrate;
an insulating film in which an opening is formed so that at least a part of the metal surface of the insulating film is exposed; and a metal containing W as a main component embedded in the opening; A semiconductor device characterized in that a metal layer containing a nitrogen element exists in at least a part of the metal. 2. The above-mentioned method for producing a metal film mainly composed of W and having a metal layer containing nitrogen element at least in part is a chemical vapor deposition method using a halogenated W gas and a gas containing a reducing gas N. 2. The method of manufacturing a semiconductor device according to claim 1. 3. The semiconductor device according to claim 2, wherein the gas containing N is N_2 gas, and the metal layer containing the nitrogen element is formed by chemical vapor deposition by exciting it with an electromagnetic field. manufacturing method. 4. The method for manufacturing a semiconductor device according to any one of claims 2 to 3, wherein the halogenated gas of W is WF_6, and the reducing gas is a hydrogen compound such as H_2, SiH_4, Si_3H_6. . 5. The semiconductor layer is a compound semiconductor such as GaAs, and the first metal is H_2 such as Pt, W, Mo, Ge, etc.
2. The semiconductor device according to claim 1, wherein the semiconductor device is made of a metal that is easily adsorbed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1493290A JPH03220720A (en) | 1990-01-26 | 1990-01-26 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1493290A JPH03220720A (en) | 1990-01-26 | 1990-01-26 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03220720A true JPH03220720A (en) | 1991-09-27 |
Family
ID=11874741
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1493290A Pending JPH03220720A (en) | 1990-01-26 | 1990-01-26 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03220720A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0841690A1 (en) * | 1996-11-12 | 1998-05-13 | Samsung Electronics Co., Ltd. | Tungsten nitride (WNx) layer manufacturing method and metal wiring manufacturing method |
-
1990
- 1990-01-26 JP JP1493290A patent/JPH03220720A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0841690A1 (en) * | 1996-11-12 | 1998-05-13 | Samsung Electronics Co., Ltd. | Tungsten nitride (WNx) layer manufacturing method and metal wiring manufacturing method |
| US6087257A (en) * | 1996-11-12 | 2000-07-11 | Samsung Electronics Co., Ltd. | Methods of fabricating a selectively deposited tungsten nitride layer and metal wiring using a tungsten nitride layer |
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