JPH03219667A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH03219667A JPH03219667A JP2014691A JP1469190A JPH03219667A JP H03219667 A JPH03219667 A JP H03219667A JP 2014691 A JP2014691 A JP 2014691A JP 1469190 A JP1469190 A JP 1469190A JP H03219667 A JPH03219667 A JP H03219667A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- channel fet
- substrate
- film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000002955 isolation Methods 0.000 claims description 31
- 238000000059 patterning Methods 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 abstract 6
- 238000000034 method Methods 0.000 description 13
- 239000012535 impurity Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 230000035515 penetration Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔目次〕
概要
産業上の利用分野
従来の技術
発明が解決しようとする課題
課題を解決するための手段
作用
実施例
第１の発明の構成例
第２の発明の工程例
第３の発明の構成例
第４の発明の工程例
本発明の応用例
（第１図
（第２図
（第３図
（第４図
（第５図
〔概要〕
ＣＭＯＳ回路を有する半導体装置及びその製造方法に関
し。[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Embodiments Example of Configuration of the First Invention Second Example of Processes of the Invention Configuration example of the third invention Process example of the fourth invention Application example of the invention (Fig. 1 (Fig. 2 (Fig. 3) (Fig. 4 (Fig. 5 [Summary]) Regarding the manufacturing method.
ゲートをイオン注入法を用いるより薄く、且つ不純物の
突き抜けを生じさせないで形成でき、更に、ｐ型ポリＳ
ｉゲートとｎ型ポリＳｉゲートの接続部の面積を低減し
微細なＣＭＯ５素子の提供を目的とし
く】）二基板上にｐチャネルＦＥＴとｎチャネルＦＥＴ
とを有し、該ｐチャネルＦＥＴのゲートは少なくとも一
部がｐ型多結晶珪素膜からなり、該ｎチャネルＦＥＴの
ゲートは少なくとも一部がｎ型多結晶珪素膜からなり、
該ｐチャネルＦＥＴのゲートと該ｎチャネルＦＥＴのゲ
ートが該基板上に形成された絶縁膜上で重なり、電気的
に接続されているように構成する。（２）：前記基板上
に素子分離ｗＡ縁膜を形成する工程と、該基板上の素子
形成領域にゲート絶縁膜を形成する工程と、該基板上に
一導電型多結晶珪素膜を成長しパターニングして、該素
子分離絶縁膜上を含んだ領域に一導電型チャネルＦＥＴ
のゲートを形成する工程と、該基板上に反対導電型多結
晶珪素膜を成長し、該素子分離絶縁膜上で該一導電型チ
ャネルＦＥＴのゲートと重なるようにパターニングして
反対導電型チャネルＦＥＴのゲートを形成する工程とを
有するように構成する。The gate can be formed thinner than using ion implantation and without impurity penetration;
The purpose is to reduce the area of the connection part between the i-gate and the n-type poly-Si gate and provide a fine CMO5 element]) A p-channel FET and an n-channel FET are installed on two substrates.
The gate of the p-channel FET is at least partially made of a p-type polycrystalline silicon film, and the gate of the n-channel FET is at least partially made of an n-type polycrystalline silicon film,
The gate of the p-channel FET and the gate of the n-channel FET are configured to overlap on an insulating film formed on the substrate and are electrically connected. (2): forming an element isolation wA edge film on the substrate, forming a gate insulating film in the element formation region on the substrate, and growing a polycrystalline silicon film of one conductivity type on the substrate. By patterning, a channel FET of one conductivity type is formed in a region including the top of the element isolation insulating film.
a step of forming a gate of the one conductivity type channel FET by growing an opposite conductivity type polycrystalline silicon film on the substrate and patterning it on the element isolation insulating film so as to overlap with the gate of the one conductivity type channel FET. and a step of forming a gate.
（３） ： （１）の半導体装置で、該ｐチャネルＦＥ
Ｔのゲート端と該ｎチャネルＦＥＴのゲート端が素子分
離絶縁膜上で間隔をおき且つ該間隔より広い幅を有する
被覆絶縁膜のコンタクト孔内に露出され、導電膜により
電気的に接続されているように構成する。(3): In the semiconductor device of (1), the p-channel FE
The gate end of the T and the gate end of the n-channel FET are exposed in a contact hole of a covering insulating film that is spaced apart from each other on the element isolation insulating film and has a width wider than the space, and are electrically connected by a conductive film. Configure it so that
（４） ： （２）の後半の工程で、該基板上に反対導
電型多結晶珪素膜を成長し、該素子分離絶縁膜上で該一
導電型チャネルＰＵＴのゲート端と間隔をおいて端部を
有するようにパターニングして反対導電型チャネルＦＥ
Ｔのゲートを形成する工程と、該基板上に被覆絶縁膜を
被着し、該間隔より広い幅を有する開口部を形成して、
該一導電型チャネルＦＥＥＴのゲート端と該反対導電型
チャネルＦＥＴのゲート端とを露出させる工程と、該基
板上に該開口部を覆って導電膜を形成する工程とを有す
るように構成する。(4): In the latter step of (2), a polycrystalline silicon film of the opposite conductivity type is grown on the substrate, and an end is grown on the element isolation insulating film at a distance from the gate end of the one conductivity type channel PUT. The channel FE is patterned to have an opposite conductivity type.
forming a gate of T, depositing a covering insulating film on the substrate, and forming an opening having a width wider than the interval;
The method includes the steps of exposing a gate end of the one conductivity type channel FEET and a gate end of the opposite conductivity type channel FET, and forming a conductive film on the substrate to cover the opening.
〔産業上の利用分野］
本発明はＣＭＯＳ回路を有する半導体装置及びその製造
方法に関する。[Industrial Application Field] The present invention relates to a semiconductor device having a CMOS circuit and a method for manufacturing the same.
〔従来の技術］
ＣＭＯＳ回路では、素子の微細化の要求により、ｐチャ
ネルＦＥＴの微細化が進んでいる。[Prior Art] In CMOS circuits, p-channel FETs are being increasingly miniaturized due to the demand for miniaturization of elements.
従来のｐチャネルＦＥＴは埋込チャネル型と呼ばれ、チ
ャネル部表面に基板と反対導電型の不純物（ウェルに形
成されている場合はウェルと反対導電型の不純物）が薄
く導入された構造を有する。A conventional p-channel FET is called a buried channel type, and has a structure in which an impurity of a conductivity type opposite to that of the substrate (if formed in a well, an impurity of a conductivity type opposite to that of the well) is introduced thinly into the surface of the channel part. .
埋込チャネル型ｐチャネルＦＥＴは、微細化されると、
薄い埋込チャネル層を形成することが困難となる。更に
、短チャネル効果が起こり易くなり微細ゲート長のＦＥ
Ｔの形成が困難となる。When a buried channel type p-channel FET is miniaturized,
It becomes difficult to form a thin buried channel layer. Furthermore, short channel effects are more likely to occur in FEs with fine gate lengths.
It becomes difficult to form T.
このような理由により、微細ゲート長のｐチャネルＦＥ
Ｔでは、埋込チャネル型から表面チャネル型への移行が
提案されている。For these reasons, p-channel FE with fine gate length
In T, a transition from a buried channel type to a surface channel type is proposed.
表面チャネル型では、しきい値電圧Ｖいの制御のため、
ｐ゛型の多結晶珪素（ポリＳｔ）ゲート電極を用いる。In the surface channel type, in order to control the threshold voltage V,
A p-type polycrystalline silicon (polySt) gate electrode is used.
このため、ゲートポリＳｉをｎチャネルＦＥＴではれ＋
型を、ｐチャネルＦＥＴではｐ゛型を用いる必要がある
。For this reason, the gate poly-Si is removed in an n-channel FET.
For p-channel FETs, it is necessary to use a p type.
従来はこの導電型の区分を、レジストマスクを用いたイ
オン注入により、ｎチャネルＦＥＴｅｆｆ域には燐イオ
ンを、ｐチャネルｌ’ｌＥＴ領域には硼素イオンを打ち
分けて行っていた。Conventionally, this conductivity type classification was performed by implanting phosphorus ions into the n-channel FETeff region and boron ions into the p-channel l'lET region by ion implantation using a resist mask.
さらに、第６図の等価回路図に示されるようにＣＭＯＳ
インバータの出力を次段インバータの入力に接続するに
は、ｎ型ポリＳｉゲートとｎ型ポリＳｉゲートとを接続
しなければならず、従来はこの接続を第７図のように被
覆絶縁膜のコンタクト孔を介して配線金属（例えばアル
ミニウム（＾ｌ）又はアルミニウムー珪素合金（Ａｌ−
５ｉ）等〕を用いて行っていた。Furthermore, as shown in the equivalent circuit diagram of FIG.
In order to connect the output of the inverter to the input of the next stage inverter, it is necessary to connect the n-type poly-Si gates to the n-type poly-Si gates. Conventionally, this connection was performed using a covering insulating film as shown in Figure 7. A wiring metal (e.g. aluminum (^l) or aluminum-silicon alloy (Al-
5i) etc.].
第６図の等価回路図ににおいて１通常のＦＥ前記号はｎ
チャネルＦＥＴを、塗り潰し三角を付したＦＥ前記号は
ｐチャネルＦＥＴを示す。In the equivalent circuit diagram of Figure 6, the symbol before 1 normal FE is n
The symbol in front of the FE with a filled triangle indicates a p-channel FET.
第７図（ａ）、 （ｂ）は従来例によるｎ型ポリＳｉゲ
ートとｎ型ポリＳｉゲートとの接続を説明する平面図と
断面図である。FIGS. 7(a) and 7(b) are a plan view and a cross-sectional view illustrating the connection between n-type poly-Si gates and n-type poly-Si gates according to a conventional example.
図において、１は珪素（Ｓｉ）基板、２は素子分離絶縁
膜で熱酸化二酸化珪素（ＳｉＯ□）膜、３はゲート絶縁
膜で熱酸化ＳｉＯ□膜、４はｎ型ポリＳｉゲート。In the figure, 1 is a silicon (Si) substrate, 2 is an element isolation insulating film, which is a thermally oxidized silicon dioxide (SiO□) film, 3 is a gate insulating film, which is a thermally oxidized SiO□ film, and 4 is an n-type poly-Si gate.
５はＰ型ボ’ＪＳｉゲート、６は化学気相成長法で成長
した二酸化珪素（ＣＶＤ−３ｉＯ□）膜、７はＡＩ配線
である。5 is a P-type Bo'JSi gate, 6 is a silicon dioxide (CVD-3iO□) film grown by chemical vapor deposition, and 7 is an AI wiring.
コンタクト部に要する配線幅−は。What is the wiring width required for the contact part?
Ｗ ＝ Ａ＋２Ｂ＋２ｃｌ＋＋２ｄ２ である。W = A+2B+2cl++2d2 It is.
ココで Ａ＝ Ｂ＝ ｄ＋＝ ｄｘ＝ ０．５μｍとす
ると、 Ｗ ＝ ３．５μｍとなる。If A=B=d+=dx=0.5μm here, then W=3.5μm.
従来例においては通常、ゲートのドープにイオン注入が
用いられるが、ゲート電極が薄くなるとイオンの突き抜
けを生ずる。そのため低加速エネルギーを用いるが、低
加速エネルギーの値は装置的にも限界がある。さらに、
注入分布がガウス分布やポアソン分布のためイオンの突
き抜けを防止できるポリＳｉの膜厚にも限界があり、あ
まり薄くすることはできなかった。In conventional examples, ion implantation is usually used to dope the gate, but as the gate electrode becomes thinner, ion penetration occurs. Therefore, low acceleration energy is used, but the value of low acceleration energy has a limit in terms of equipment. moreover,
Since the implantation distribution is Gaussian distribution or Poisson distribution, there is a limit to the thickness of the poly-Si film that can prevent ion penetration, and it has not been possible to make it very thin.
更に、ｎ型ポリＳｉゲートとｎ型ポリＳｉゲートとの接
続のため、コンタクト孔を２個（前段インバータの出力
部のコンタクト孔を含めると３個）設けなければならず
、接続部分に必要な面積が大きくなり、デバイスの微細
化を阻害するという欠点があった。Furthermore, in order to connect the n-type poly-Si gate to the n-type poly-Si gate, two contact holes (three if you include the contact hole for the output section of the front-stage inverter) must be provided, and the This has the disadvantage that the area becomes large, which hinders device miniaturization.
本発明はＰ型ポリＳｉゲートのＰチャネルＦＥＴとｎ型
ポリＳｉゲートのｎチャネルＦＥＴとを共に表面チャネ
ル型ＦＥＴとして、同一基板上にゲート厚をイオン注入
法を用いるより薄く、且つ不純物の突き抜けを生じさせ
ないで形成でき、更に、Ｐ型ポ’ＪＳｉゲートとｎ型ポ
リＳｉゲートの接続部の面積を低減し微細なＣＭＯ３素
子の提供を目的とする。The present invention uses a P-channel FET with a P-type poly-Si gate and an n-channel FET with an n-type poly-Si gate as surface channel FETs on the same substrate, making the gate thickness thinner than that using ion implantation, and allowing impurity penetration. The purpose of the present invention is to provide a fine CMO3 element which can be formed without causing any problems, and which further reduces the area of the connecting portion between the P-type poly-Si gate and the n-type poly-Si gate.
上記！ｉＨの解決は。 the above! iH's solution.
（１）基板上にｐチャネルＦＥＴとｎチャネルＦＥＴと
を有し、咳ｐチャネルＦＥＴのゲートは少なくとも一部
がｐ型多結晶珪素膜からなり、該ｎチャネルＦＥＴのゲ
ートは少なくとも一部がｎ型多結晶珪素膜からなり、該
ｐチャネルＦＥＴのゲートと該ｎチャネルＦＥＴのゲー
トが該基板上に形成された絶縁膜上で重なり、電気的に
接続されている半導体装置、或いは。(1) A p-channel FET and an n-channel FET are provided on the substrate, the gate of the p-channel FET is at least partially made of a p-type polycrystalline silicon film, and the gate of the n-channel FET is at least partially made of an n-channel FET. A semiconductor device made of a type polycrystalline silicon film, in which the gate of the p-channel FET and the gate of the n-channel FET overlap and are electrically connected on an insulating film formed on the substrate, or
（２）前記基板上に素子分離絶縁膜を形成する工程と、
該基板上の素子形成領域にゲート絶縁膜を形成する工程
と、該基板上に一導電型多結晶珪素膜を成長しパターニ
ングして、該素子分離絶縁膜上を含んだ領域に一導電型
チャネルＦＢＴのゲートを形成する工程と、該基板上に
反対導電型多結晶珪素膜を成長し、該素子分離絶縁膜上
で該一導電型チャネルＦＥＴのゲートと重なるようにパ
ターニングして反対導電型チャネルＦＥＴのゲートを形
成する工程とを有する半導体装置の製造方法、或いは（
３）基板上にｐチャネルＦＥＴとｎチャネルＦＥＴとこ
れらのＦＥＴを分離する素子分離絶縁膜と、これらのＦ
ＥＴを覆う被覆絶縁膜とを有し、該ｐチャネル ＦＥＴ
のゲートは少なくとも一部がｐ型多結晶珪素膜からなり
、該ｎチャネルＰＵＴのゲートは少なくとも一部がｎ型
多結晶珪素膜からなり、該ｐチャネルＦＥＴのゲート端
と該ｎチャネルＦＥＴのゲート端が素子分離絶縁膜上で
間隔をおき且つ該間隔より広い幅を有する被覆絶縁膜の
コンタクト孔内に露出され、導電膜により電気的に接続
されている半導体装置、或いは。(2) forming an element isolation insulating film on the substrate;
A step of forming a gate insulating film in the element formation region on the substrate, growing and patterning a polycrystalline silicon film of one conductivity type on the substrate, and forming a channel of one conductivity type in the region including the element isolation insulating film. A step of forming a gate of an FBT, and growing a polycrystalline silicon film of an opposite conductivity type on the substrate, and patterning it on the element isolation insulating film so as to overlap the gate of the channel FET of one conductivity type to form a channel of the opposite conductivity type. A method for manufacturing a semiconductor device comprising a step of forming a gate of an FET, or (
3) A p-channel FET, an n-channel FET, an element isolation insulating film that separates these FETs, and these FETs on the substrate.
and a covering insulating film covering the p-channel FET.
The gate of the n-channel PUT is at least partially made of a p-type polycrystalline silicon film, and the gate of the n-channel PUT is at least partially made of an n-type polycrystalline silicon film, and the gate end of the p-channel FET and the gate of the n-channel FET are A semiconductor device, or a semiconductor device whose ends are exposed in a contact hole of a covering insulating film that is spaced apart on an element isolation insulating film and has a width wider than the space, and electrically connected by a conductive film.
（４）前記基板上に素子分離絶縁膜を形成する工程と、
該基板上の素子形成領域にゲート絶縁膜を形成する工程
と、該基板上に一導電型多結晶珪素膜を成長しパターニ
ングして、該素子分離絶縁膜上を含んだ領域に一導電型
チャネルＦＥＴのゲートを形成する工程と、該基板上に
反対導電型多結晶珪素膜を成長し、該素子分離絶縁膜上
で該一導電型チャネルＦＥＴのゲート端と間隔をおいて
端部を有するようにパターニングして反対導電型チャネ
ルＦＥＴのゲートを形成する工程と、該基板上に被覆絶
縁膜を被着し、該間隔より広い幅を有する開口部を形成
して、該一導電型チャネルＦＥＴのゲート端と該反対導
電型チャネルＦＥＴのゲート端とを露出させる工程と、
該基板上に該開口部を覆って導電膜を形成する工程とを
有する半導体装置の製造方法により達成される。(4) forming an element isolation insulating film on the substrate;
A step of forming a gate insulating film in the element formation region on the substrate, growing and patterning a polycrystalline silicon film of one conductivity type on the substrate, and forming a channel of one conductivity type in the region including the element isolation insulating film. A step of forming a gate of the FET, and growing a polycrystalline silicon film of opposite conductivity type on the substrate so that the film has an end portion spaced apart from the gate end of the one conductivity type channel FET on the element isolation insulating film. forming the gate of the channel FET of the opposite conductivity type by patterning the substrate to form the gate of the channel FET of the one conductivity type; depositing a covering insulating film on the substrate and forming an opening having a width wider than the interval; exposing a gate end and a gate end of the opposite conductivity type channel FET;
This is achieved by a method for manufacturing a semiconductor device including the step of forming a conductive film on the substrate to cover the opening.
［作用］
本発明によれば、ゲートの形成に化学気相成長でポリＳ
ｔ成膜時にドープするドープ） ＣＶＤ法を用いること
により、不純物の突き抜けを防止し、微細ＦＥＴの薄い
ポリＳｉゲートの形成を可能とし、更にｐ型ポリＳｔゲ
ートとｎ型ポリＳｉゲートとの接続を配線を介さず素子
分離絶縁膜上で両者を重ね合わせて直接とるか、或いは
間隔を開けて同一コンタクト孔内で配線を介してとるよ
うにして接続部の小面積化をはかったものである。[Function] According to the present invention, polyS is formed by chemical vapor deposition to form the gate.
By using the CVD method (doping used during film formation), it is possible to prevent penetration of impurities, enable the formation of a thin poly-Si gate for a micro FET, and also to connect the p-type poly-St gate and the n-type poly-Si gate. The area of the connection part is reduced by either directly overlapping the two on the element isolation insulating film without using wiring, or by separating them and connecting them via wiring in the same contact hole. .
［実施例］
第１図（ａ）、 （ｂ）は第１の発明の一実施例を説明
する断面図である。[Embodiment] FIGS. 1(a) and 1(b) are sectional views illustrating an embodiment of the first invention.
図において、１はＳｔ基板、２は素子分離絶縁膜で熱酸
化ＳｉＯ□膜、３はゲート絶縁膜で熱酸化５ｉ（ｈ膜、
４はｎ型ポリＳｉゲート ５はｐ型ポリＳｉゲート、６
は絶縁膜でＣＶＤ−５ｉｎ、膜である。In the figure, 1 is a St substrate, 2 is an element isolation insulating film, which is a thermally oxidized SiO□ film, and 3 is a gate insulating film, which is a thermally oxidized 5i (h film,
4 is an n-type poly-Si gate, 5 is a p-type poly-Si gate, 6
is an insulating film and is a CVD-5in film.
この例では、０．５μｍルールのレイアウトで。In this example, the layout is based on the 0.5 μm rule.
素子分離絶縁膜上でコンタクトに必要な最小幅−は。What is the minimum width required for a contact on the element isolation insulating film?
Ｗ ＝ ２ｄｔ＋ｄ、＝ １．２．！７ ｍである。こ
れに対して従来例の場合には、接続はコンタクト孔を介
するため前記のように３．５μｍの幅が必要である。W=2dt+d,=1.2. ! It is 7 m. On the other hand, in the case of the conventional example, since the connection is made through a contact hole, a width of 3.5 μm is required as described above.
実施例において、ｐ型ポリＳｉゲートとｎ型ポリＳｉゲ
ートの重ね合わせにおいて、いずれを上にするかはどち
らでもよく、パターン幅の違い、ドープする不純物の種
類と拡散係数、エツチングの選択比等の条件を考慮して
決定すればよい。In the example, when a p-type poly-Si gate and an n-type poly-Si gate are stacked, it does not matter which one is placed on top, and there are various factors such as the difference in pattern width, the type and diffusion coefficient of doping impurities, etching selectivity, etc. It may be determined by taking into account the following conditions.
重ね合わせ部が、第１図（ａ）はｐ型ポリＳｉゲートが
上、第１図（ｂ）はｎ型ポリＳｉゲートが上の例である
。FIG. 1(a) shows an example in which the overlapping portion is a p-type poly-Si gate on top, and FIG. 1(b) is an example in which an n-type poly-Si gate is on the top.
第２図（ａ）〜（ｄ）は第２の発明の一実施例による工
程を説明する断面図である。FIGS. 2(a) to 2(d) are sectional views illustrating steps according to an embodiment of the second invention.
第２図（ａ）において、窒化珪素膜を耐酸化マスクにし
た部分酸化法により、基板１上に素子分離絶縁膜として
厚さ４０００人の熱酸化ＳｉＯ２膜２を形成する。In FIG. 2(a), a thermally oxidized SiO2 film 2 with a thickness of 4000 nm is formed on a substrate 1 as an element isolation insulating film by a partial oxidation method using a silicon nitride film as an oxidation-resistant mask.
第２図（ｂ）において、基板１上にゲート絶縁膜として
厚さ１００人の熱酸化Ｓｉ０ｇ膜３を形成する。In FIG. 2(b), a thermally oxidized Si0g film 3 having a thickness of 100 nm is formed on a substrate 1 as a gate insulating film.
次に、基板１上にドープトＣｖＤ法により、厚さ１００
０人のｎ゛型ポリＳｉ膜を成長し、パターニングしてｎ
型ポリＳｉゲート４を形成する。Next, a doped CvD method is applied to the substrate 1 to a thickness of 100 mm.
An n-type poly-Si film of 0 is grown and patterned to
A type poly-Si gate 4 is formed.
ドープトＣｖＤの条件は、成長ガスとしてモノシラン（
Ｓｉｌ１４）、キャリアガスとして水素（１，ドーピン
グガスとしてフォスヒン（ＰＨ，３）又はアルシン（Ａ
ｒｔ１３）を用い、ガス圧力は２０ Ｔｏｒｒ、基板温
度は６００’Ｃである。The conditions for doped CvD are monosilane (
Sil14), hydrogen (1) as a carrier gas, phoshine (PH,3) or arsine (A) as a doping gas.
rt13), the gas pressure was 20 Torr, and the substrate temperature was 600'C.
第２図（Ｃ）において、ｎ型ポリＳｉゲート４を覆って
基板上にドープトＣｖＤ法により、厚さ１０００人のｐ
゛型ポリＳｉ膜５′を成長する。In FIG. 2(C), a p-type film with a thickness of 1000 nm is deposited on the substrate by the doped CvD method, covering the n-type poly-Si gate 4.
A type poly-Si film 5' is grown.
ドープ） ＣＶＤの条件は、成長ガスとしてＳｉｎ。Dope) The CVD conditions were Sin as the growth gas.
キャリアガスとしてＨ２＋ ドーピングガスとして弗
化硼素（ＢＦ、）又はジボラン（Ｂ２１１４）を用い、
ガス圧力は２０ Ｔｏｒｒ＋基板温度は６００’Ｃであ
る。Using H2+ as a carrier gas and boron fluoride (BF, ) or diborane (B2114) as a doping gas,
Gas pressure is 20 Torr + substrate temperature is 600'C.
第２図（ｄ）において、ｐ゛型ポリＳｔ膜をパターニン
グしてｎ型ポリＳｉゲート５を形成する。In FIG. 2(d), an n-type poly-Si gate 5 is formed by patterning the p-type poly-St film.
このとき１ Ｐ型ポリＳｔゲート５はｎ型ポリＳｉゲー
ト４に重ね合わすようにパターニングする。At this time, the 1P type polySt gate 5 is patterned so as to overlap the n type polySi gate 4.
以上で接続部の形成工程を終わるが、或いは下層のポリ
Ｓｉゲート４をパターニングして形成後。This completes the process of forming the connection portion, or after patterning and forming the lower layer poly-Si gate 4.
上層の反対導電型ポリＳｉ膜５′を成長前にその下のゲ
ート酸化膜３を一旦除去して再酸化してもよい。この場
合はｐ型ポリＳｔゲートとｎ型ポリＳｉゲートの重ね合
わせ部において１上層のポリＳｉの酸化膜が形成される
ことになるが、この酸化膜を１００Å以下に薄くすれば
トンネル電流が流れ導通状態が形成される。このトンネ
ル′を流はｐ型ポリＳｔゲートとｎ型ポリＳｉゲートが
同電位になりさえすればよいので、電流値（約１０−’
Ａ）自体は小さくても構わない。Before growing the upper poly-Si film 5' of the opposite conductivity type, the underlying gate oxide film 3 may be removed and reoxidized. In this case, an upper layer of poly-Si oxide film will be formed at the overlapping portion of the p-type poly-St gate and the n-type poly-Si gate, but if this oxide film is thinned to 100 Å or less, tunnel current will flow. A conductive state is formed. The current value (approximately 10-'
A) itself may be small.
上層のポリＳｉ膜５′をパターニングするにはエツチン
グ終点の決め方が問題となるが次のようにすればよい。In patterning the upper poly-Si film 5', there is a problem in determining the end point of etching, which can be done as follows.
まず、２種類のポリＳｉ膜が直に接する場合には上層の
ポリＳｉ膜がエツチングされる時間からエツチングの終
点を決める。次に２種類のポリＳｉ膜が薄い酸化膜（あ
るいは他の絶縁膜）を介して接する場合には、この酸化
膜でエツチング終点を検出する。First, when two types of poly-Si films are in direct contact with each other, the end point of etching is determined from the time it takes for the upper poly-Si film to be etched. Next, when two types of poly-Si films are in contact with each other via a thin oxide film (or other insulating film), the etching end point is detected through this oxide film.
実施例においては、ｐ型ポリＳｔゲートとｎ型ポリＳｉ
ゲートをドープトポリＳｉで形成された場合について説
明したが１ポリサイド（ポリＳｉとシリサイドの複合膜
）、メタルとポリＳｔの複合膜のゲート電極に対しても
本発明は適用可能である。In the example, a p-type polySt gate and an n-type polySi gate are used.
Although the case where the gate is formed of doped poly-Si has been described, the present invention is also applicable to gate electrodes of 1-polycide (composite film of poly-Si and silicide) and composite film of metal and poly-St.
従来のイオン注入法は突き抜けを防ぐためゲート厚が最
小で２０００人程度であるが、実施例はゲート厚が１０
００人であり、素子の微細化に対応することができる。In the conventional ion implantation method, the minimum gate thickness is about 2000 to prevent penetration, but in this example, the gate thickness is 1000.
00 people, and can respond to miniaturization of elements.
次に、第３，４の発明について説明する。Next, the third and fourth inventions will be explained.
第３図（ａ）、 （ｂ）は第３の発明の一実施例を説明
する断面図と平面図である。FIGS. 3(a) and 3(b) are a sectional view and a plan view illustrating an embodiment of the third invention.
図において、１はＳｔ基板、２は素子分離絶縁膜で熱酸
化ＳｉＯ２膜、３はゲート絶縁膜で熱酸化５ｉＯ１膜、
４はｎ型ポリＳｉゲート、５はｐ型ポリＳｉゲート ６
は被覆絶縁膜でＣＣＶＤ−５ｉｎ膜、７は導電膜でＡＩ
配線である。In the figure, 1 is an St substrate, 2 is an element isolation insulating film, which is a thermally oxidized SiO2 film, 3 is a gate insulating film, which is a thermally oxidized 5iO1 film,
4 is an n-type poly-Si gate, 5 is a p-type poly-Si gate 6
7 is a coating insulating film, which is CCVD-5in film, and 7 is a conductive film, which is AI.
It's the wiring.
この例の特徴は、ｐチャネルＦＥＴのゲート端とｎチャ
ネルＦＥＴのゲート端が素子分離絶縁膜２上で間隔をお
き且つ該間隔より広い幅を有する被覆絶縁膜６のコンタ
クト孔内に露出され、導電膜７により電気的に接続され
ていることである。The feature of this example is that the gate end of the p-channel FET and the gate end of the n-channel FET are exposed in the contact hole of the covering insulating film 6 which is spaced apart on the element isolation insulating film 2 and has a width wider than the space, They are electrically connected by the conductive film 7.
コンタクト部に要する配線幅−は、従来例によると −−Ａ＋２Ｂ＋２ｄｌ＋２ｄ２ であるが、実施例によると 一王Ａ＋２ｄｉ＋２ｄｚ となり、配線幅−はコンタクト孔２個分だけ減少する。According to the conventional example, the wiring width required for the contact part is --A+2B+2dl+2d2 However, according to the example Ichiou A+2di+2dz Therefore, the wiring width - is reduced by two contact holes.
この結果、コンタクト部の素子分離領域を微細化するこ
とができる。As a result, the element isolation region of the contact portion can be miniaturized.
第４図（ａ）〜（ｆ）は第４の発明の一実施例による工
程を説明する断面図である。FIGS. 4(a) to 4(f) are sectional views illustrating steps according to an embodiment of the fourth invention.
第４図（ａ）において、窒化珪素膜を耐酸化マスクにし
た部分酸化法により、基板ｌ上に素子分離絶縁膜として
厚さ４０００人の熱酸化ＳｉＯア膜２を形成する。In FIG. 4(a), a thermally oxidized SiO film 2 with a thickness of 4000 nm is formed on a substrate 1 as an element isolation insulating film by a partial oxidation method using a silicon nitride film as an oxidation-resistant mask.
第４図（ｂ）において、基板１上にゲート絶縁膜として
厚さ１００人の熱酸化５ｔａ２膜３を形成する。In FIG. 4(b), a thermally oxidized 5ta2 film 3 having a thickness of 100 nm is formed on a substrate 1 as a gate insulating film.
次に、基板１上にドープトＣＶＤ法により、厚さ１００
０人のｎ゛型ポリＳｉ膜を成長し、パターニングしてｎ
型ポリＳｉゲート４を形成する。Next, a doped CVD method is applied to the substrate 1 to a thickness of 100 mm.
An n-type poly-Si film of 0 is grown and patterned to
A type poly-Si gate 4 is formed.
第４図（Ｃ）において、ｎ型ポリＳｉゲート４を覆って
基板上にドープｌ−ＣＶＤ法により、厚さ１０００人の
ｐ゛型ポリＳｉ膜５′を成長する。In FIG. 4C, a p-type poly-Si film 5' having a thickness of 1000 wafers is grown on the substrate covering the n-type poly-Si gate 4 by the doped l-CVD method.
第４図（ｄ）において、ｐ゛型ポリ５ｉｌｌをパターニ
ングしてｎ型ポリＳｉゲート５を形成する。In FIG. 4(d), an n-type poly-Si gate 5 is formed by patterning the p-type poly 5ill.
このとき、ｎ型ポリＳｉゲート５はｎ型ポリＳｌゲート
４と間隔を開ける。At this time, the n-type poly-Si gate 5 is spaced apart from the n-type poly-Sl gate 4.
第４図（ｅ）において、基板上に厚さ１０００人のＣＶ
Ｄ−３ｉ（ｈ膜６を成長し２両ゲートの間隔より両側に
それぞれ０．５μｍずつ大きい幅の開口部を形成する。In Fig. 4(e), a CV with a thickness of 1000 people is placed on the substrate.
D-3i (h film 6 is grown and openings each having a width 0.5 μm larger than the gap between the two gates are formed on both sides.
第４図げ）において、 ＣＶＤ−５ｉＯｚ膜６の開口部
を覆って厚さ４０００人のＡＩ配線７を形成する。In FIG. 4), an AI wiring 7 with a thickness of 4000 layers is formed covering the opening of the CVD-5iOz film 6.
この場合、 ＡＩ配線７とｎ型ポリＳｉゲート５又はｎ
型ポリＳｉゲート４との重なりを０．５μｍ以上とれば
接続の安定性は十分であることを信転性試験で確認して
いる。In this case, the AI wiring 7 and the n-type poly-Si gate 5 or n
It has been confirmed through a reliability test that the connection stability is sufficient if the overlap with the type poly-Si gate 4 is 0.5 μm or more.
以上で接続部の形成工程を終わる。This completes the process of forming the connection portion.
第５図は本発明の詳細な説明するＣＭＯＳ集積回路の一
部を示す平面図である。FIG. 5 is a plan view showing a part of a CMOS integrated circuit for explaining the present invention in detail.
このレイアウトは０．５μｍの設計ルールで行われ、各
部の寸法は次のようである。This layout was performed using a design rule of 0.5 μm, and the dimensions of each part are as follows.
ｎチャネルＦＥＴのゲート長＝０．５μｍ。Gate length of n-channel FET = 0.5 μm.
ｐチャネルＦＥＴのゲート長＝０．５μｍｐ−ｎゲート
間隔＝０．５μｍ。Gate length of p-channel FET = 0.5 μm p-n gate spacing = 0.5 μm.
ゲート電極端一素子分離領域端＝０．５μｍ。Gate electrode end, element isolation region end = 0.5 μm.
コンタクト孔＝０．５μｍ角 素子分離領域端−コンタクト孔＝０．５μｍ。Contact hole = 0.5μm square Element isolation region end-contact hole = 0.5 μm.
ゲート端一コンタクト孔＝０．５μｍ。Gate end - contact hole = 0.5 μm.
配線幅＝０．５μｍ。Wiring width = 0.5 μm.
配線−コンタクト孔＝０．３μｍ。Wiring-contact hole = 0.3 μm.
配線−ｎゲート端一０．５μｍ。Wiring - n gate end - 0.5 μm.
配線−ｐゲート端一０．５μｍ
図中＊ ｖＣＣは電源線、 ＧＮＤは接地線、Ｃはコ
ンタクト部である。Wiring - p gate end - 0.5 μm * In the figure, vCC is a power supply line, GND is a grounding line, and C is a contact section.
ｎ型ポリＳｉゲート＠掻４とｎ型ポリＳｉゲート電極５
とは第１発明の構造で端部が重なって接続されている。N-type poly-Si gate @ 4 and n-type poly-Si gate electrode 5
and have the structure of the first invention, in which the ends are overlapped and connected.
（発明の効果）
以上説明したように本発明によれば、ｎ型ポリＳｉゲー
トのｐチャネルＦＥＴとｎ型ポリＳｉゲートのｎチャネ
ルＦＥＴとを共に表面チャネル型ＦＥＴとして、同一基
板上にゲート厚をイオン注入法を用いるより薄り、且つ
不純物の突き抜けなく形成でき。(Effects of the Invention) As described above, according to the present invention, both a p-channel FET with an n-type poly-Si gate and an n-channel FET with an n-type poly-Si gate are formed as surface channel FETs on the same substrate with a gate thickness. It is thinner than using ion implantation and can be formed without impurities penetrating.
更に、ｎ型ポリＳｉゲートとｎ型ポリＳｉゲートの接続
部の面積を大幅に低減して微細なＣＭＯＳ回路の設計が
できるようになった。Furthermore, it has become possible to design a fine CMOS circuit by significantly reducing the area of the connection portion between the n-type poly-Si gates and the n-type poly-Si gates.
又、換言すれば接続部の面積の低減により、実効的なコ
ンタクト面積を大きくとることができ素子の微細化と安
定化に効果が大きい。In other words, by reducing the area of the connecting portion, the effective contact area can be increased, which is highly effective in miniaturizing and stabilizing the element.
第１図（ａ）、 （ｂ）は第１の発明の一実施例を説明
する断面図。
第２図（ａ）〜（ｄ）は第２の発明の一実施例による工
程を説明する断面図
第３図（ａ）、 （ｂ）は第３の発明の一実施例を説明
する断面図と平面図。
第４図（ａ）〜（ｆ）は第４の発明の一実施例による工
程を説明する断面図。
第５図は本発明の詳細な説明するＣＭＯＳ集積回路の一
部を示す平面図。
第６図はＣＭＯＳインバータの等価回路図。
↓面図である。
図において。
１はＳｉ基板。
２は素子分離絶縁膜で熱酸化Ｓｉ０ｇ膜３はゲート絶縁
膜で熱酸化ＳｉＯ□膜。
４はｎ型ポリＳｉゲート。
５はｎ型ポリＳｉゲート
６は絶縁膜テＣＶＤ−３ｉＯｚ膜。
７は導電膜でＡＩ配線
（１））
平面図
第５づご日月の 實 方色イク・］
勇
図
箋
臂明の賞方ａ分・ｌ／ｌ哨面図
第 １ 図
第２発日す ユニ木型、と 客ｔ ′ａｌｌｌ −
４う 謄□’ｉｐ円第
図
第４衾日目のエーネＬと各地ヨ月 すう−１ｄｂ図第
凹
第
６
図
（ト）千面区
境釆争１０区
第
図FIGS. 1(a) and 1(b) are sectional views illustrating an embodiment of the first invention. FIGS. 2(a) to 2(d) are cross-sectional views explaining steps according to an embodiment of the second invention. FIGS. 3(a) and 3(b) are cross-sectional views explaining an embodiment of the third invention. and floor plan. FIGS. 4(a) to 4(f) are cross-sectional views illustrating steps according to an embodiment of the fourth invention. FIG. 5 is a plan view showing a part of a CMOS integrated circuit for explaining the present invention in detail. FIG. 6 is an equivalent circuit diagram of a CMOS inverter. ↓This is a side view. In fig. 1 is a Si substrate. 2 is an element isolation insulating film, and a thermally oxidized Si0g film 3 is a gate insulating film, which is a thermally oxidized SiO□ film. 4 is an n-type poly-Si gate. 5 is an n-type poly-Si gate 6 is an insulating film CVD-3iOz film. 7 is a conductive film with AI wiring (1)) Plan view 5th sun and moon actual direction Iku] Isamu Zushin's award direction a minute / l / l sentinel view 1st figure 2 date of release Uni wooden mold, and customer t'all -
4 U □'ip yen diagram 4th class day Aene L and various Yotsuki Su-1db diagram concavity 6 (g) Senmen ward boundary dispute 10 ward diagram
Claims (4)
を有し、 該ｐチャネルＦＥＴのゲートは少なくとも一部がｐ型多
結晶珪素膜からなり、 該ｎチャネルＦＥＴのゲートは少なくとも一部がｎ型多
結晶珪素膜からなり、 該ｐチャネルＦＥＴのゲートと該ｎチャネルＦＥＴのゲ
ートが該基板上に形成された絶縁膜上で重なり、電気的
に接続されていることを特徴とする半導体装置。(1) A p-channel FET and an n-channel FET are provided on the substrate, the gate of the p-channel FET is at least partially made of a p-type polycrystalline silicon film, and the gate of the n-channel FET is at least partially made of an n-channel FET. 1. A semiconductor device comprising a type polycrystalline silicon film, wherein the gate of the p-channel FET and the gate of the n-channel FET overlap and are electrically connected on an insulating film formed on the substrate.
と、 該基板上に一導電型多結晶珪素膜を成長しパターニング
して、該素子分離絶縁膜上を含んだ領域に一導電型チャ
ネルＦＥＴのゲートを形成する工程と、 該基板上に反対導電型多結晶珪素膜を成長し、該素子分
離絶縁膜上で該一導電型チャネルＦＥＴのゲートと重な
るようにパターニングして反対導電型チャネルＦＥＴの
ゲートを形成する工程とを有することを特徴とする請求
項（１）記載の半導体装置の製造方法。(2) forming an element isolation insulating film on the substrate; forming a gate insulating film in an element formation region on the substrate; growing and patterning a polycrystalline silicon film of one conductivity type on the substrate; forming a gate of a channel FET of one conductivity type in a region including the top of the element isolation insulating film; growing a polycrystalline silicon film of the opposite conductivity type on the substrate; 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a gate of a channel FET of an opposite conductivity type by patterning the gate so as to overlap a gate of a channel FET of a conductivity type.
これらのＦＥＴを分離する素子分離絶縁膜と、これらの
ＦＥＴを覆う被覆絶縁膜とを有し、 該ｐチャネルＦＥＴのゲートは少なくとも一部がｐ型多
結晶珪素膜からなり、 該ｎチャネルＦＥＴのゲートは少なくとも一部がｎ型多
結晶珪素膜からなり、 該ｐチャネルＦＥＴのゲート端と該ｎチャネルＦＥＴの
ゲート端が素子分離絶縁膜上で間隔をおき且つ該間隔よ
り広い幅を有する被覆絶縁膜のコンタクト孔内に露出さ
れ、導電膜により電気的に接続されていることを特徴と
する半導体装置。(3) A p-channel FET, an n-channel FET, an element isolation insulating film for separating these FETs, and a covering insulating film covering these FETs are provided on the substrate, and at least a portion of the gate of the p-channel FET is provided. The gate of the n-channel FET is made of a p-type polycrystalline silicon film, and at least a portion of the gate of the n-channel FET is made of an n-type polycrystalline silicon film, and the gate end of the p-channel FET and the gate end of the n-channel FET are on an element isolation insulating film. What is claimed is: 1. A semiconductor device characterized in that the semiconductor device is exposed in a contact hole of a covering insulating film having an interval of , and a width wider than the interval, and is electrically connected by a conductive film.
と、 該基板上に一導電型多結晶珪素膜を成長しパターニング
して、該素子分離絶縁膜上を含んだ領域に一導電型チャ
ネルＦＥＴのゲートを形成する工程と、 該基板上に反対導電型多結晶珪素膜を成長し、該素子分
離絶縁膜上で該一導電型チャネルＦＥＴのゲート端と間
隔をおいて端部を有するようにパターニングして反対導
電型チャネルＦＥＴのゲートを形成する工程と、 該基板上に被覆絶縁膜を被着し、該間隔より広い幅を有
する開口部を形成して、該一導電型チャネルＦＥＴのゲ
ート端と該反対導電型チャネルＦＥＴのゲート端とを露
出させる工程と、 該基板上に該開口部を覆って導電膜を形成する工程とを
有することを特徴とする請求項（３）記載の半導体装置
の製造方法。(4) forming an element isolation insulating film on the substrate; forming a gate insulating film in an element formation region on the substrate; growing and patterning a polycrystalline silicon film of one conductivity type on the substrate; forming a gate of a channel FET of one conductivity type in a region including the top of the element isolation insulating film; growing a polycrystalline silicon film of the opposite conductivity type on the substrate; forming a gate of an opposite conductivity type channel FET by patterning the substrate so as to have an end spaced apart from the gate end of the conductivity type channel FET; depositing a covering insulating film on the substrate; forming an opening having a width to expose a gate end of the one conductivity type channel FET and a gate end of the opposite conductivity type channel FET; and forming a conductive film on the substrate to cover the opening. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014691A JPH03219667A (en) | 1990-01-24 | 1990-01-24 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014691A JPH03219667A (en) | 1990-01-24 | 1990-01-24 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03219667A true JPH03219667A (en) | 1991-09-27 |
Family
ID=11868218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014691A Pending JPH03219667A (en) | 1990-01-24 | 1990-01-24 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03219667A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0883852A (en) * | 1994-06-08 | 1996-03-26 | Hyundai Electron Ind Co Ltd | Semiconductor element and its preparation |
| JPH08264661A (en) * | 1995-03-27 | 1996-10-11 | Nec Corp | Semiconductor device and manufacture thereof |
-
1990
- 1990-01-24 JP JP2014691A patent/JPH03219667A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0883852A (en) * | 1994-06-08 | 1996-03-26 | Hyundai Electron Ind Co Ltd | Semiconductor element and its preparation |
| US6261882B1 (en) | 1994-06-08 | 2001-07-17 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating a semiconductor device |
| JPH08264661A (en) * | 1995-03-27 | 1996-10-11 | Nec Corp | Semiconductor device and manufacture thereof |
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