JPH03212993A - Manufacture of multilayer ceramic circuit board and method for formation of via hole - Google Patents
Manufacture of multilayer ceramic circuit board and method for formation of via holeInfo
- Publication number
- JPH03212993A JPH03212993A JP901890A JP901890A JPH03212993A JP H03212993 A JPH03212993 A JP H03212993A JP 901890 A JP901890 A JP 901890A JP 901890 A JP901890 A JP 901890A JP H03212993 A JPH03212993 A JP H03212993A
- Authority
- JP
- Japan
- Prior art keywords
- powder
- hole
- circuit board
- ceramic
- multilayer ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 22
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000843 powder Substances 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000004020 conductor Substances 0.000 claims abstract description 14
- 239000011230 binding agent Substances 0.000 claims abstract description 12
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000010949 copper Substances 0.000 claims description 25
- 238000010304 firing Methods 0.000 claims description 24
- 238000005553 drilling Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 claims description 2
- 239000011812 mixed powder Substances 0.000 claims description 2
- 229910052863 mullite Inorganic materials 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 239000002245 particle Substances 0.000 abstract description 10
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 abstract description 8
- 229920002799 BoPET Polymers 0.000 abstract description 8
- 239000005041 Mylar™ Substances 0.000 abstract description 8
- 239000011521 glass Substances 0.000 abstract description 5
- NIQCNGHVCWTJSM-UHFFFAOYSA-N Dimethyl phthalate Chemical compound COC(=O)C1=CC=CC=C1C(=O)OC NIQCNGHVCWTJSM-UHFFFAOYSA-N 0.000 abstract description 4
- 239000000203 mixture Substances 0.000 abstract description 4
- 239000012298 atmosphere Substances 0.000 abstract description 3
- FBSAITBEAPNWJG-UHFFFAOYSA-N dimethyl phthalate Natural products CC(=O)OC1=CC=CC=C1OC(C)=O FBSAITBEAPNWJG-UHFFFAOYSA-N 0.000 abstract description 2
- 229960001826 dimethylphthalate Drugs 0.000 abstract description 2
- 239000004014 plasticizer Substances 0.000 abstract description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 abstract description 2
- 239000004926 polymethyl methacrylate Substances 0.000 abstract description 2
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 239000002241 glass-ceramic Substances 0.000 description 11
- 238000005245 sintering Methods 0.000 description 7
- 239000012299 nitrogen atmosphere Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000005388 borosilicate glass Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000008018 melting Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- WHOPEPSOPUIRQQ-UHFFFAOYSA-N oxoaluminum Chemical compound O1[Al]O[Al]1 WHOPEPSOPUIRQQ-UHFFFAOYSA-N 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
多層セラミック回路基板のビア形成方法に関し、ボアが
なく、低抵抗のビアを形成することを目的とし、
セラミックグリーンシートのビア形成位置を穴開けして
スルーホールを形成する工程と、金属粉にセラミック粉
末を加えてなる導体ペースト或いは金属粉にセラミック
粉を加えた粉末を前記スル−ホールに充填する工程と、
前記グリーンシート上に導体ペーストを印刷し、導体パ
ターンを形成する工程と、該グリーンシートを位置合わ
せして積層し、一体化する工程と、該積層体をバインダ
抜きした後、焼成する工程と、を含むことを特徴として
多層セラミック回路基板のビア形成方法を構成する。[Detailed Description of the Invention] [Summary] Regarding a via formation method for a multilayer ceramic circuit board, the purpose is to form a via with no bore and low resistance. and a step of filling the through-hole with a conductive paste made by adding ceramic powder to metal powder or a powder made by adding ceramic powder to metal powder,
A step of printing a conductor paste on the green sheet to form a conductor pattern, a step of aligning and stacking the green sheets and integrating them, and a step of firing the laminate after removing the binder, A method for forming vias in a multilayer ceramic circuit board is characterized by comprising:
〔産業上の利用分野］
本発明は多層セラミック回路基板のビア形成方法に関す
る。[Industrial Field of Application] The present invention relates to a method for forming vias in multilayer ceramic circuit boards.
大量の情報を迅速に処理する必要から情報処理装置は小
型大容量化が行われており、この装置の主体を占める半
導体装置は単位素子の小型化による集積化が行われてＬ
ＳＩやＶＬＳＩが実用化されている。Due to the need to quickly process large amounts of information, information processing devices are becoming smaller and larger in capacity, and the semiconductor devices that make up the main component of these devices are becoming more integrated by making unit elements smaller.
SI and VLSI have been put into practical use.
そして、これらの集積回路はチップのま−で複数個をセ
ラミックスよりなるチップ搭載用基板（インターポーザ
）に搭載してＬＳＩ モジールを作り、これを取替え単
位として印刷配線基板に装着する実装形態が採られてい
る。These integrated circuits are mounted on a ceramic chip mounting substrate (interposer) to form an LSI module, which is then mounted on a printed circuit board as a replacement unit. ing.
また、フリップチップタイプの半導体集積回路は総てセ
ラミック回路基板に装着されている。Furthermore, all flip-chip type semiconductor integrated circuits are mounted on ceramic circuit boards.
このように、半導体集積回路はセラミック回路基板上に
装着されているが、これらの回路基板は総て多層化が行
われ、２０層程度のものまで実用化されており、各層の
電子回路の接続は、各層を穴開けして設けたビア（Ｖｉ
ａ）により行われている。In this way, semiconductor integrated circuits are mounted on ceramic circuit boards, but all of these circuit boards are multi-layered, and up to about 20 layers have been put into practical use. is a via (Vi) provided by drilling holes in each layer.
This is done according to a).
〔従来の技術］
セラミック回路基板としてはアルミナを主成分とするア
ルミナセラミック回路基板と、硼硅酸ガラスを主成分と
するガラスセラミック回路基板とがあり、それぞれ用い
られている。[Prior Art] As ceramic circuit boards, there are an alumina ceramic circuit board whose main component is alumina and a glass ceramic circuit board whose main component is borosilicate glass, and each is used.
こ−で、多層回路基板の製造方法としては、それぞれの
グリーンシートについて、ビア形成位置を穴開けしてス
ルーホールを形成した後、この穴に導体ペーストを充填
して穴埋めを行う。In this method of manufacturing a multilayer circuit board, a through hole is formed by drilling a hole at a via formation position in each green sheet, and then the hole is filled with a conductive paste to fill the hole.
次に、それぞれのグリーンシートについて、穴埋め位置
を含み、導体ペーストをスクリーン印刷して電子回路を
パターン形成し、乾燥させる。Each green sheet is then screen printed with a conductive paste to pattern an electronic circuit, including fill-in locations, and allowed to dry.
次に、このグリーンシートを位置合わせして積層した後
に加圧して一体化し、この積層体を加熱してバインダ抜
きをした後に焼成することにより多層セラミック回路基
板が製造されている。Next, a multilayer ceramic circuit board is manufactured by aligning and stacking the green sheets, pressurizing them to integrate them, heating the stack to remove the binder, and then firing the stack.
こ−で、アルミナの融点は２０１５°Ｃと高いために焼
結温度としては１６００°Ｃ程度が必要であり、そのた
めにビア形成材料および導体線路の形成材料としてタン
グステン（Ｗ）やモリブデン（ＭＯ）など高融点金属し
か使用できない。Because the melting point of alumina is as high as 2015°C, the sintering temperature needs to be about 1600°C, and for this reason, tungsten (W) and molybdenum (MO) are used as the material for forming vias and conductor lines. Only high-melting point metals such as metals can be used.
また、体積抵抗率はＷが４．９Ω・ｍ、Ｍｏが５．０Ω
−ｍ（測温０°Ｃ）と銅（Ｃｕ）の１．５５Ω−ｍ（測
温０ ’Ｃ）に較べると、遥かに大きく電力損失が問題
となる。In addition, the volume resistivity is 4.9Ω・m for W and 5.0Ω for Mo.
-m (temperature measured at 0°C) and 1.55Ω-m (temperature measured at 0'C) of copper (Cu), the power loss is much larger and becomes a problem.
また、アルミナ（ＡｆｚＯ：＋）の誘電率が８〜１０と
大きいために信号の漏洩（Ｃｒｏｓｓ−ｔａｌｋ）が生
じ易く、また信号の遅延時間（τ）も大きくなる。Furthermore, since the dielectric constant of alumina (AfzO:+) is as large as 8 to 10, signal leakage (cross-talk) is likely to occur, and the signal delay time (τ) also increases.
そこで、これに代わるものとしてアルミナに較べて融点
が９００°Ｃ以下と低く、また誘電率が４．１〜４．８
と小さい硼硅酸ガラスを主体とするガラスセラミックス
が注目され、Ｗの代わりにＣｕを用いるガラスセラミッ
クス基板が普及しつ＼ある。Therefore, as an alternative to alumina, it has a lower melting point of 900°C or less and a dielectric constant of 4.1 to 4.8.
Glass ceramics mainly composed of small borosilicate glasses have attracted attention, and glass ceramic substrates using Cu instead of W are becoming popular.
さて、従来のビア形成法は第６図に示すようにポリエチ
レンテレフタレート（以下一般名称マイラー）シート１
を通して多数のスルーホール２が穴開けしであるグリー
ンシート３をマイラーシート１を上にし、吸引紙４を介
して排気装置を備えた印刷台５の上に置く。Now, the conventional via forming method is as shown in Fig. 6.
A green sheet 3, in which a number of through holes 2 are punched through, is placed on a printing table 5 equipped with an exhaust device with the Mylar sheet 1 facing up, with a suction paper 4 interposed therebetween.
次に、マイラーシート１の上に導体ペーストを置き、真
空ポンプを動作させながら、スキージを摺動することに
より、導体ペーストはマイラーシート１を通って吸引さ
れ、スルーホール２に充填される。Next, the conductive paste is placed on the Mylar sheet 1, and by sliding the squeegee while operating the vacuum pump, the conductive paste is sucked through the Mylar sheet 1 and filled into the through holes 2.
次に、マイラーシート１を剥がし、グリーンシート３の
上に導体線路をパターン形成し、乾燥させた後、多数の
グリーンシート３を位置合わせして積層加圧して一体化
した後、加熱してグリーンシート３に含まれているバイ
ンダを除去する。Next, the Mylar sheet 1 is peeled off, a conductor line is patterned on the green sheet 3, and after drying, a large number of green sheets 3 are aligned and laminated and pressed to integrate, and then heated to form a green The binder contained in the sheet 3 is removed.
次に、高温焼成してセラミックスおよび導体金属を焼結
することにより、多層セラミック回路基板は完成し、同
時にビアも形成されている。Next, the multilayer ceramic circuit board is completed by high-temperature firing to sinter the ceramic and conductive metal, and at the same time, vias are also formed.
また、発明者等は導体ペーストを使用する代わりに金属
粉を直接にスルーホールに充填する方法を提案している
。The inventors have also proposed a method of directly filling through holes with metal powder instead of using conductor paste.
（特願昭６３−１６９５１８．昭和６３年７月７日出願
）然し、高温焼成に当たっては、
■ 導体ペーストを構成する金属とグリーンシートを構
成するセラミックスとは焼成温度が異なる。(Patent Application No. 169518, filed on July 7, 1988) However, in high-temperature firing, (1) The firing temperature of the metal constituting the conductor paste and the ceramic constituting the green sheet are different.
■ 焼成の過程で導体ペーストの有機成分が分解する。■ The organic components of the conductor paste decompose during the firing process.
■ 焼成の過程で金属の過焼成が起こる。■ Over-firing of the metal occurs during the firing process.
などが原因してビアの中にボア（Ｐｏｒｅ）が生じ、ビ
アの抵抗が増大すると共に、断線が起こり易いと云う問
題がある。Due to such factors, a bore is generated in the via, which increases the resistance of the via and also increases the possibility of wire breakage.
［発明が解決しようとする課題〕
多層セラミック回路基板に形成されている電子回路は、
セラミック層を穴開けして設けた径１００μｍ程度のビ
アにより回路接続されている。[Problem to be solved by the invention] The electronic circuit formed on the multilayer ceramic circuit board is
The circuit is connected through vias with a diameter of about 100 μm, which are provided by drilling holes in the ceramic layer.
然し、このビアにはボアが生じ易く、そのために抵抗の
増大や断線が起こり、製造歩留まりが低いことが問題で
、この解決が課題である。However, the problem is that bores are likely to form in these vias, resulting in increased resistance and disconnection, resulting in low manufacturing yields, and solving this problem is an issue.
［課題を解決するための手段］
上記の課題はセラミックグリーンシートのビア形成位置
を穴開けしてスルーホールを形成する工程と、金属粉に
セラミック粉末を加えてなる導体ペースト或いは金属粉
とセラミック粉との混合粉末をスルーホールに充填する
工程と、このグリーンシート上に導体ペーストを印刷し
、導体パターンを形成する工程と、グリーンシートを位
置合わせして積層し、一体化する工程と、積層体をバイ
ンダ抜きした後、焼成する工程と、を含むことを特徴と
して多層セラミック回路基板のビア形成方法を構成する
ことにより解決することができる。[Means for solving the problem] The above problem involves the process of forming a through hole by drilling the via formation position of a ceramic green sheet, and the process of forming a conductor paste made by adding ceramic powder to metal powder or metal powder and ceramic powder. A process of filling the through holes with a mixed powder of This problem can be solved by configuring a method for forming vias in a multilayer ceramic circuit board, which includes a step of removing the binder and then firing the method.
〔作用］
ビアにボアが生ずる原因は先に記したように、■ 導体
ペーストを構成する金属とグリーンシートを構成するセ
ラミックスとは焼成温度が異なる。[Function] As mentioned above, the reasons for the formation of bores in vias are as follows: (1) The firing temperatures of the metal constituting the conductor paste and the ceramics constituting the green sheet are different.
■ 焼成の過程で導体ペーストの有機成分が分解する。■ The organic components of the conductor paste decompose during the firing process.
■ 焼成の過程で金属の過焼成が起こる。■ Over-firing of the metal occurs during the firing process.
が考えられるが、これをガラスセラミック多層回路基板
について説明すると、
■については、ガラスセラミックスの焼結温度は９００
〜１０００°Ｃであるのに対し、Ｃｕの焼結温度は４０
０〜７００°Ｃであり、そのためビアが先に焼結し収縮
することから基板とビアとの間に隙間ができることから
ボアが生じる。However, to explain this regarding a glass ceramic multilayer circuit board, regarding (2), the sintering temperature of glass ceramics is 900°C.
~1000°C, whereas the sintering temperature for Cu is 40°C.
0 to 700°C, and therefore, the vias sinter and shrink first, creating a gap between the substrate and the via, resulting in a bore.
■については、導体ペーストは粘性をもたせるためにバ
インダの含有量が多く、そのために焼成過程でビアにボ
アが発生し易い。Regarding (2), the conductive paste contains a large amount of binder to give it viscosity, and therefore, bores are likely to occur in the vias during the firing process.
■についてはＣｕの焼結は４００〜７００ ’Ｃで起こ
るに拘らず９００〜１０００”Ｃに加熱されるため焼結
が非常に進行するが、融点（１０８４，５°Ｃ）以下の
ため、多孔質でボアの多い状態になる。As for (2), although sintering of Cu occurs at 400-700'C, it is heated to 900-1000'C, so sintering progresses very much, but since it is below the melting point (1084,5°C), it becomes porous. Due to the quality, it becomes a state with many bores.
以上のことから焼成後のビアは基板の壁面との間にボア
があり、またビア自体にボアがある状態となる。From the above, the via after firing has a bore between it and the wall surface of the substrate, and the via itself has a bore.
発明者は金属粉末（Ｃｕ粉末）に微量なセラミック粉末
を加えることにより金属粉末（Ｃｕ粉末）の焼結を抑制
でき、これによりボアの発生が無くなることを見出した
。The inventor has discovered that by adding a small amount of ceramic powder to the metal powder (Cu powder), sintering of the metal powder (Cu powder) can be suppressed, thereby eliminating the occurrence of bores.
以下、ボアの発生についての影響因子を少なくする見地
から導体ペーストを用いず、平均粒径１μｍのＣｕ粉に
平均粒径０．３μｍのＡＡ２０３粉を添加した場合につ
いて本発明を説明する。Hereinafter, the present invention will be described in the case where AA203 powder with an average particle size of 0.3 μm is added to Cu powder with an average particle size of 1 μm without using a conductor paste from the viewpoint of reducing factors affecting the occurrence of bores.
まず、Ｃｕ粉末に添加量を変えてＡｌｔｏ３粉を混合し
ボールミルで２４時間混合した後、５Ｘ５５Ｘ３ｍｍの
圧粉成形体を作った。First, Alto3 powder was mixed with Cu powder in different amounts and mixed in a ball mill for 24 hours, and then a powder compact of 5 x 55 x 3 mm was made.
また、次の組成の原料を用い、混練した後に成形してア
ルミナ系のガラスセラミックスよりなる圧粉成形体を作
った。Further, raw materials having the following composition were kneaded and then molded to produce a powder compact made of alumina-based glass ceramics.
セラミック粉末： １１ｅｚ０３粉 ・・・３０重
量部、ガラス粉末： 硼珪酸ガラス粉 ・・・５０〃第
１図は湿潤した窒素（Ｎ２）雰囲気中で焼成した場合の
焼成温度と収縮率との関係を示すもので、試料としては
次の５種類をとった。Ceramic powder: 11ez03 powder...30 parts by weight, Glass powder: Borosilicate glass powder...50 Figure 1 shows the relationship between firing temperature and shrinkage rate when fired in a moist nitrogen (N2) atmosphere. The following five types of samples were taken.
Ｃｕ粉のみの圧粉成形体、
Ｃｕ粉に３％のＡ Ｑ ２０３粉を混ぜた圧粉成形体、
Ｃｕ粉に５％のへ２□０３粉を混ぜた圧粉成形体、Ｃｕ
粉に１０％のＡ ｆ ２０３粉を混ぜた圧粉成形体、ガ
ラスセラミックスからなる圧粉成形体、同図の結果から
、Ｃｕ粉のみの圧粉成形体７は焼結の進行によって収縮
率は約６００°Ｃまで増加し、約７００°Ｃを越えると
過焼成状態となり収縮率は減少してゆく。A compact made of Cu powder only, a compact made of Cu powder mixed with 3% AQ 203 powder,
Powder compact made by mixing Cu powder with 5% He2□03 powder, Cu
From the results shown in the same figure, the shrinkage rate of powder compact 7 made only of Cu powder decreases due to the progress of sintering. The temperature increases to about 600°C, and when the temperature exceeds about 700°C, an overfired state occurs and the shrinkage rate decreases.
一方、ガラスセラミックスからなる圧粉成形体８は図に
示すように温度が上がるに従って収縮率は増加してゆく
、この相違がビアにボアができる原因である。On the other hand, as shown in the figure, the shrinkage rate of the powder compact 8 made of glass ceramics increases as the temperature rises, and this difference is the cause of the formation of bores in the vias.
然し、Ｃｕ粉に３％のＡ ｌ ｚｏｆｆ粉を混ぜた圧粉
成形体９はガラスセラミックス８に似た特性を示し、温
度と共に収縮率は増加するが、８００ ’Ｃを過ぎると
Ｃｕの過焼成効果が現れて収縮率は減少してゆく、そし
て、Ａｆｚ（ｈの添加量が５％より１０％に増すに従っ
て収縮率の値は減少してゆき、またＣｕの過焼成効果が
現れる温度も高温側に移行する。However, the green compact 9, which is a mixture of Cu powder and 3% Alzoff powder, exhibits properties similar to those of glass ceramics 8, and the shrinkage rate increases with temperature, but when the temperature exceeds 800'C, over-firing of Cu occurs. As the effect appears, the shrinkage rate decreases, and as the amount of Afz(h added increases from 5% to 10%, the shrinkage rate value decreases, and the temperature at which the Cu overfiring effect appears also increases. move to the side.
次に、第２図はＣｕ粉に対するＡ ｆｆｉ ２０３粉の
添加量と抵抗率との関係であって、５％程度の添加では
抵抗率の変化は認められない。Next, FIG. 2 shows the relationship between the amount of Affi 203 powder added to the Cu powder and the resistivity, and no change in resistivity is observed when about 5% is added.
然し、八〇２０３の粒径が０．３μｍの場合１０と粒径
が３．５ μｍの場合１１と比較すると、粒径が小さな
Ａ ｌ ２０．粉を使う程、比表面積が大きくなるため
添加の影響が早く現れ、抵抗率が増加する。However, compared to 10 when the particle size of 80203 is 0.3 μm and 11 when the particle size is 3.5 μm, the particle size of Al 20. The more powder you use, the larger the specific surface area becomes, so the effects of the addition appear more quickly and the resistivity increases.
また、第３図はＡｌ２ｚ（ｈ＊’ｉ）の添加量を１０容
量％と固定し、粒径を変えた場合の影響であって、第２
図の場合と同様に粒径が小さなへ２□０．粉を使う程、
比表面積が大きくなるため抵抗率が増加する。In addition, Figure 3 shows the effect when the amount of Al2z(h*'i) added is fixed at 10% by volume and the particle size is changed.
As in the case of the figure, the particle size is smaller than 2□0. The more powder you use,
As the specific surface area increases, the resistivity increases.
以上のように、適量のＡ Ｉ２ ｚｏｉ粉の添加により
抵抗率を無添加の場合と殆ど変えることなく収縮率をガ
ラスセラミックスに近かずけることができ、そのためボ
アの発生を無くすることができる。As described above, by adding an appropriate amount of A I2 zoi powder, the shrinkage rate can be brought close to that of glass ceramics without changing the resistivity from the case without the addition, and therefore, the occurrence of bores can be eliminated.
実施例１： （Ａｌ２Ｏ２粉を添加した場合）セラミッ
ク粉末： Ａ Ｅ ｚｏｚ粉 ・・・３０重量部、
ガラス粉末： 硼硅酸ガラス粉 ・・・５０〃バインダ
： ポリメチルメタクリレート・・・１２重量部、
可塑剤： ジメチルフタレート ・・・５ 〃からなる
混合物１重量部に対してアセトンを３重量部加え、混練
した後にアセトンを蒸発させて作ったスラリーをドクタ
ブレード法で、マイラーシートの上に３００ μｍの厚
さに成形し、グリーンシートを作った。Example 1: Ceramic powder (when Al2O2 powder is added): AE zoz powder...30 parts by weight,
Glass powder: Borosilicate glass powder...50 Binder: Polymethyl methacrylate...12 parts by weight Plasticizer: Dimethyl phthalate...5 Add 3 parts by weight of acetone to 1 part by weight of the mixture. After kneading, a slurry made by evaporating acetone was formed onto a Mylar sheet to a thickness of 300 μm using a doctor blade method to make a green sheet.
そして、このグリーンシートにマイラーシートを付けた
ま−、ドリルを用いて直径１００μｍのスルーホールを
形成した。Then, a mylar sheet was attached to this green sheet, and a through hole with a diameter of 100 μm was formed using a drill.
一方、導体ペーストとしてはＣｕ粉に対して平均粒径が
０．３μｍのＡ Ｉ！、２０３粉を５％混合したものを
用意し、第６図に示す装置を用いてスルーホールの充填
を行った。On the other hand, as a conductive paste, AI! has an average particle size of 0.3 μm compared to Cu powder. , 203 powder at a concentration of 5% was prepared, and through-holes were filled using the apparatus shown in FIG.
そして、湿潤したＮ２雰囲気中で８００°Ｃで４時間に
亙ってバインダ抜きを行い、更にＮ２雰囲気中で１００
０°Ｃ，４時間の焼成を行った結果、ボアのない良好な
ビアを形成することができた。Then, the binder was removed at 800°C for 4 hours in a humid N2 atmosphere, and then at 100°C in a N2 atmosphere.
As a result of firing at 0° C. for 4 hours, a good via without a bore could be formed.
実施例２ ＜、３Ａｌｚ（ｈ ・２５ｉＯｚ）を添加
シフ’、： 場合第４図は第１図に示したと同じ要領で
ムライト（３Ａ １ｚｏ３・２５ｉＯｚ）を１容量％、
２容量％および５容量％添加した５Ｘ５５Ｘ５ｍｍの圧
粉成形体について、焼成温度を変えて収縮率を測定した
結果であり、１容量％添加のもの１２は過焼成の影響が
現れ、２容量％添加のもの１３はガラスセラミックス８
に近似し、また５容量％添加のもの１４は過焼成の影響
が更に高温側にずれてくる。Example 2 <, 3Alz (h 25 iOz) added Schiff': In the case of FIG. 4, 1% by volume of mullite (3A 1zo3 25 iOz) was added in the same manner as shown in FIG.
These are the results of measuring the shrinkage rate by changing the firing temperature for compacted compacts of 5 x 55 x 5 mm with 2 volume % and 5 volume % added, and 12 with 1 volume % added was affected by over-firing, and 2 volume % added Item 13 is glass ceramic 8
In addition, in the case of 5% by volume addition No. 14, the influence of overfiring is further shifted to the high temperature side.
この第４図の結果から３Ａ ｌ ｚｏａ ・２５ｉＯ
ｚをＣｕＬ対して２容量％添加した導体ペーストを用意
し第６図に示す装置を用いてスルーホールの充填を行っ
た。From the results shown in Figure 4, 3A l zoa ・25iO
A conductive paste containing 2% by volume of Z added to CuL was prepared, and through holes were filled using the apparatus shown in FIG.
そして、湿潤したＮ２雰囲気中で８００ ’Ｃで４時間
に亙ってバインダ抜きを行い、更にＮ２雰囲気中でｌ０
００°Ｃ，４時間の焼成を行った結果、ボアのない良好
なビアを形成することができた。Then, the binder was removed at 800'C for 4 hours in a humid N2 atmosphere, and then at 10°C in a N2 atmosphere.
As a result of firing at 00°C for 4 hours, it was possible to form a good via without a bore.
実施例３ ： （ＳｉＯ□ガラスを添加した場合）第
５図は第１図に示したと同じ要領でシリカガラス（Ｓｉ
Ｏｚ）を１容量％、２容量％および５容量％添加した５
ｘ５５Ｘ５ｍｍの圧粉成形体について、焼成温度を変え
て収縮率を測定した結果であり、１容量％添加のもの１
５は過燐酸の影響が現れ、２容量％添加のもの１６より
も５容量％添加のもの１７のほうが過燐酸の影響が高温
側にずれてくる。Example 3: (When adding SiO□ glass) Figure 5 shows the addition of silica glass (Si
Oz) added at 1%, 2% and 5% by volume.
This is the result of measuring the shrinkage rate by changing the firing temperature for compacted compacts of x55 x 5 mm.
In No. 5, the influence of superphosphoric acid appears, and the influence of superphosphoric acid shifts toward the higher temperature side in No. 17, which has 5% by volume addition, than No. 16, which has added 2% by volume.
この第５図の結果から５ｉＯｔをＣｕに対して２容量％
添加した導体ペーストを用意し第６図に示す装置を用い
てスルーホールの充填を行った。From the results shown in Figure 5, 5iOt is 2% by volume relative to Cu.
The added conductive paste was prepared and through-holes were filled using the apparatus shown in FIG.
そして、湿潤したＮ２雰囲気中で８００″Ｃで４時間に
亙ってバインダ抜きを行い、更にＮ２雰囲気中で１００
０°Ｃ，４時間の焼成を行った結果、ボアのない良好な
ビアを形成することができた。Then, the binder was removed at 800"C for 4 hours in a humid N2 atmosphere, and then at 100"C in a N2 atmosphere.
As a result of firing at 0° C. for 4 hours, a good via without a bore could be formed.
［発明の効果］
以上記したように本発明の実施により多層セラミック回
路基板の製造にあたってボアがなく、また抵抗率が従来
と殆ど変わらないビアを作ることができる。[Effects of the Invention] As described above, by carrying out the present invention, it is possible to create a via without a bore and with almost the same resistivity as the conventional method when manufacturing a multilayer ceramic circuit board.
第１図はＣｕ粉末にへ〇２０．粉末を添加した場合の収
縮率の変化特性。
第２図はＡｆ２０．粉の添加量と抵抗率との関係図、
第３図は添加した八２□０．の粒径と抵抗率との関係図
、
第４図はＣｕ粉末に３Ａ ｌ ｚｏｓ ・２ ＳｉＯ
□粉末を添加した場合の収縮率の変化特性、
第５図はＣｕ粉末にＳｉ０ｇガラス粉末を添加した場合
の収縮率の変化特性、
第６図はビア充填法を説明する斜視図、である。
図
畔において、
１はマイラーシート、 ２はスルーホール、３はグ
リーンシート、
７はＣｕ粉末のみの圧粉成形体、
８はガラスセラミックスの圧粉成形体、である。Figure 1 shows Cu powder.〇20. Characteristics of changes in shrinkage rate when powder is added. Figure 2 shows Af20. Figure 3 shows the relationship between the amount of powder added and the resistivity. Figure 4 shows the relationship between particle size and resistivity of 3A lzos 2 SiO in Cu powder.
□Characteristics of change in shrinkage rate when powder is added. Figure 5 is a change in shrinkage rate when SiOg glass powder is added to Cu powder. Figure 6 is a perspective view illustrating the via filling method. In the figure, 1 is a mylar sheet, 2 is a through hole, 3 is a green sheet, 7 is a powder compact made only of Cu powder, and 8 is a powder compact made of glass ceramics.
Claims (4)
けしてスルーホールを形成する工程と、金属粉にセラミ
ック粉末を加えてなる導体ペーストを前記スルーホール
に充填してビアを形成する工程と、 前記グリーンシート上に導体ペーストを印刷し、導体パ
ターンを形成する工程と、 該グリーンシートを位置合わせして積層し、一体化する
工程と、 該積層体をバインダ抜きした後、焼成する工程と、 を含むことを特徴とする多層セラミック回路基板の製造
方法。(1) a step of forming a through hole by drilling a hole in a ceramic green sheet at a via formation position; a step of filling the through hole with a conductive paste made by adding ceramic powder to metal powder to form a via; A step of printing a conductive paste on a green sheet to form a conductor pattern, a step of positioning and stacking the green sheets and integrating them, and a step of firing the laminate after removing the binder. A method of manufacturing a multilayer ceramic circuit board, comprising:
形成において、 金属粉とセラミック粉末との混合粉末を直接にスルーホ
ールに充填することを特徴とする多層セラミック回路基
板のビア形成方法。(2) A method for forming a via in a multilayer ceramic circuit board, characterized in that in forming the via in the production of the multilayer ceramic circuit board, the through holes are directly filled with a mixed powder of metal powder and ceramic powder.
２記載の多層セラミック回路基板のビア形成方法。(3) The method for forming vias in a multilayer ceramic circuit board according to claim 2, wherein the metal powder is made of copper.
カのうちの何れか一つからなることを特徴とする請求項
２記載の多層セラミック回路基板のビア形成方法。(4) The method for forming vias in a multilayer ceramic circuit board according to claim 2, wherein the ceramic powder is made of any one of alumina, mullite, and silica.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP901890A JPH03212993A (en) | 1990-01-18 | 1990-01-18 | Manufacture of multilayer ceramic circuit board and method for formation of via hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP901890A JPH03212993A (en) | 1990-01-18 | 1990-01-18 | Manufacture of multilayer ceramic circuit board and method for formation of via hole |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03212993A true JPH03212993A (en) | 1991-09-18 |
Family
ID=11708918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP901890A Pending JPH03212993A (en) | 1990-01-18 | 1990-01-18 | Manufacture of multilayer ceramic circuit board and method for formation of via hole |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03212993A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5287620A (en) * | 1991-06-18 | 1994-02-22 | Fujitsu Limited | Process of producing multiple-layer glass-ceramic circuit board |
| JP2006080248A (en) * | 2004-09-09 | 2006-03-23 | Kyocera Corp | Ceramic electronic component and manufacturing method therefor |
-
1990
- 1990-01-18 JP JP901890A patent/JPH03212993A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5287620A (en) * | 1991-06-18 | 1994-02-22 | Fujitsu Limited | Process of producing multiple-layer glass-ceramic circuit board |
| JP2006080248A (en) * | 2004-09-09 | 2006-03-23 | Kyocera Corp | Ceramic electronic component and manufacturing method therefor |
| JP4518885B2 (en) * | 2004-09-09 | 2010-08-04 | 京セラ株式会社 | Ceramic electronic component and method for manufacturing the same |
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