JPH0320918B2 - - Google Patents

Description

【発明の詳細な説明】 産業上の利用分野 本発明は電子回路に用いるコンデンサ内蔵セラ
ミツク多層基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a ceramic multilayer substrate with built-in capacitors used in electronic circuits.

従来の構成とその問題点 電子回路の高密度化、多機能化に伴い３次元構
造による基板の多層配線化、コンデンサ等の機能
付加への要求が強くなつてきている。Conventional configurations and their problems With the increasing density and multifunctionality of electronic circuits, there is an increasing demand for multilayer wiring on boards with three-dimensional structures and for adding functions such as capacitors.

以下、従来のコンデンサ内蔵セラミツク多層基
板の例を第１図，第２図に示し、その問題点につ
いて述べてみる。 Examples of conventional ceramic multilayer substrates with built-in capacitors are shown in FIGS. 1 and 2, and their problems will be discussed below.

第１図はセラミツク生シート多層法による基板
の例である。厚さ0.1〜0.5mmのセラミツク生シー
ト１の表面にスクリーン印刷等により内部配線電
極２、コンデンサ容量電極３を形成し、乾燥後、
各セラミツク生シート１を相互の位置関係を合わ
せ、必要枚数積み重ねた後温間プレスにより一体
化させ、その後に焼成してコンデンサ内蔵セラミ
ツク多層基板を得る。上記生シート多層法による
基板の問題点は、内部配線電極２とコンデンサ容
量電極３とを同一セラミツク生シート上に形成し
ていることから、コンデンサ用電極間のセラミツ
ク層が厚いため大容量のコンデンサを得ることが
できない。コンデンサ容量を大きくしようとすれ
ば内部配線電極間のセラミツク層を薄くしなけれ
ばならず、その結果、内部配線電極間に浮遊容量
が発生する。 FIG. 1 is an example of a substrate produced by the ceramic raw sheet multilayer method. Internal wiring electrodes 2 and capacitor capacitance electrodes 3 are formed on the surface of a raw ceramic sheet 1 with a thickness of 0.1 to 0.5 mm by screen printing or the like, and after drying,
After aligning the respective raw ceramic sheets 1 with each other and stacking the required number of sheets, they are integrated by warm pressing, and then fired to obtain a ceramic multilayer substrate with a built-in capacitor. The problem with the substrate using the raw sheet multilayer method described above is that the internal wiring electrodes 2 and capacitor capacitance electrodes 3 are formed on the same raw ceramic sheet. can't get it. In order to increase the capacitance of the capacitor, the ceramic layer between the internal wiring electrodes must be made thinner, and as a result, stray capacitance occurs between the internal wiring electrodes.

次に第２図は印刷多層法による基板の例であ
る。導通用スルーホール４を設けたセラミツク生
シート５の表面にスクリーン印刷法によりセラミ
ツク層６、コンデンサ容量電極７、内部配線電極
８を形成し、その後に焼成してコンデンサ内蔵セ
ラミツク多層基板を得る。上記印刷多層法による
基板の問題点は、多数回層印刷していく程、基板
表面の平滑性が悪くなり、基板表面に厚幕抵抗９
を印刷法等で形成する場合、抵抗値の精度が非常
に悪くなる。つまり、コンデンサ容量を増大する
ために多層化を狙つても、実際５層程度が限界で
あり、大容量のコンデンサを得ることができな
い。又、大容量のコンデンサを得るために高誘電
率のセラミツク材料を用いる場合、印刷法による
セラミツク層一層の厚みは約40μｍと非常に薄い
ため、内部配線電極間に浮遊容量が発生する。さ
らに第２図のように電極層が基板一部に片奇つて
いるため焼成時に曲りが発生する。以上の様に従
来法によるコンデンサ内蔵セラミツク多層基板
は、コンデンサ容量が小さい、基板の形状精度が
悪い等の問題点がある。 Next, FIG. 2 shows an example of a substrate produced by the printed multilayer method. A ceramic layer 6, a capacitor capacitance electrode 7, and an internal wiring electrode 8 are formed on the surface of a raw ceramic sheet 5 provided with through holes 4 for conduction by screen printing, and then fired to obtain a ceramic multilayer substrate with a built-in capacitor. The problem with the substrate produced by the above printing multilayer method is that the more layers are printed, the smoother the surface of the substrate becomes.
When forming the resistor by a printing method or the like, the accuracy of the resistance value becomes very poor. In other words, even if multi-layering is aimed at increasing capacitor capacity, the actual limit is about five layers, making it impossible to obtain a large-capacity capacitor. Furthermore, when a ceramic material with a high dielectric constant is used to obtain a large capacity capacitor, since the thickness of a single ceramic layer formed by printing is very thin, approximately 40 μm, stray capacitance occurs between internal wiring electrodes. Furthermore, as shown in FIG. 2, since the electrode layer is uneven on a part of the substrate, bending occurs during firing. As described above, the conventional ceramic multilayer substrate with built-in capacitors has problems such as a small capacitor capacity and poor precision in the shape of the substrate.

発明の目的 本発明はこのような従来の欠点を除去するもの
であり、大容量のコンデンサを内蔵でき、基板の
形状精度が良好なコンデンサ内蔵セラミツク多層
基板を提供することを目的とする。OBJECTS OF THE INVENTION The present invention eliminates these conventional drawbacks, and aims to provide a capacitor-embedded ceramic multilayer substrate that can accommodate a large-capacity capacitor and has good shape accuracy.

発明の構成 本発明のコンデンサ内蔵セラミツク多層基板
は、コンデンサ容量発生部の有効セラミツク層が
薄くかつ基板厚さ方向のほぼ中央部に形成してお
り、そのコンデンサ容量発生部の上下面に等しい
厚さでかつコンデンサ容量発生有効セラミツク層
よりも厚い内部配線用セラミツク層が形成してあ
るため、コンデンサ容量を非常に大きく得ること
ができ、かつ基板形状精度の非常に良いものであ
る。Structure of the Invention In the ceramic multilayer board with a built-in capacitor of the present invention, the effective ceramic layer of the capacitor capacitance generating portion is thin and formed approximately at the center in the thickness direction of the substrate, and has a thickness equal to the top and bottom surfaces of the capacitor capacitance generating portion. Since the ceramic layer for internal wiring is thicker and thicker than the capacitor capacitance generating effective ceramic layer, a very large capacitor capacitance can be obtained and the substrate shape precision is very good.

実施例の説明 以下、本発明の一実施例を図面を参照して説明
する。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

第３図に示すように本発明のコンデンサ内蔵セ
ラミツク多層基板は厚さ約30μｍのコンデンサ有
効セラミツク層１１とコンデンサ容量電極１２と
を複数層積層したコンデンサ容量発生部１３と、
そのコンデンサ容量発生部１３の上下に厚さ約
100μｍの内部配線用セラミツク層１４と内部配
線電極１５とを複数層、上下層同厚みに積層した
内部配線層１６とから成る。この様に基板内部を
コンデンサ容量発生部１３と、内部配線層とに分
けることにより、コンデンサの大容量化を目的と
して、コンデンサ有効セラミツク層１１を非常に
薄くしても、内部配線用セラミツク層１４を厚く
することで浮遊容量の発生を抑えることができ
る。又、上下の配線層にセラミツクシートを用い
れば基板表面の平滑性は非常に良好である。さら
に上下の配線層の厚みを同一にすれば焼成時の基
板の曲りは防止でき非常に平坦な基板を得ること
ができる。 As shown in FIG. 3, the capacitor-embedded ceramic multilayer substrate of the present invention includes a capacitor capacitance generating section 13 in which a capacitor effective ceramic layer 11 with a thickness of about 30 μm and a capacitor capacitor electrode 12 are laminated in multiple layers;
There is approximately a thickness above and below the capacitor capacity generating portion 13.
It consists of an internal wiring layer 16 in which a ceramic layer 14 for internal wiring with a thickness of 100 μm and a plurality of internal wiring electrodes 15 are laminated to have the same thickness on the upper and lower layers. By dividing the inside of the board into the capacitor capacitance generating section 13 and the internal wiring layer in this way, even if the capacitor effective ceramic layer 11 is made very thin for the purpose of increasing the capacitance of the capacitor, the internal wiring ceramic layer 14 The generation of stray capacitance can be suppressed by increasing the thickness of the capacitor. Furthermore, if ceramic sheets are used for the upper and lower wiring layers, the smoothness of the substrate surface will be very good. Furthermore, by making the thicknesses of the upper and lower wiring layers the same, bending of the substrate during firing can be prevented and a very flat substrate can be obtained.

発明の効果 以上の様に、本発明のコンデンサ内蔵セラミツ
ク多層基板は基板内部をコンデンサ容量発生部
と、内部配線層とに分け、さらに内部配線層をコ
ンデンサ容量発生部との上下に等しい厚みで形成
することにより、大容量のコンデンサを内蔵し、
かつ浮遊容量が抑えられ、基板表面が平滑で曲り
がない非常に良好なものであり、電子回路の高密
度化多機能化に非常に有効である。Effects of the Invention As described above, the ceramic multilayer board with a built-in capacitor of the present invention divides the inside of the board into a capacitor capacitance generating section and an internal wiring layer, and furthermore, the internal wiring layer is formed with equal thickness above and below the capacitor capacitance generating section. By doing so, it has a built-in large capacity capacitor,
In addition, the stray capacitance is suppressed, and the substrate surface is smooth and has no bends, making it extremely effective for increasing the density and multifunctionality of electronic circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図は従来のコンデンサ内蔵セラミ
ツク多層基板の断面図、第３図は本発明の一実施
例におけるコンデンサ内蔵セラミツク多層基板の
断面図である。 ９……厚膜抵抗、１０……チツプコンデンサ、
１１……コンデンサ容量有効セラミツク層、１３
……コンデンサ容量発生部、１４……内部配線用
セラミツク層。 1 and 2 are cross-sectional views of a conventional ceramic multilayer board with a built-in capacitor, and FIG. 3 is a cross-sectional view of a ceramic multilayer board with a built-in capacitor according to an embodiment of the present invention. 9... Thick film resistor, 10... Chip capacitor,
11... Capacitance effective ceramic layer, 13
... Capacitor capacitance generating section, 14 ... Ceramic layer for internal wiring.

Claims (1)

【特許請求の範囲】[Claims] １ コンデンサ容量発生部の各有効セラミツク層
が薄くかつ基板厚さ方向のほぼ中央部に形成し、
前記コンデンサ容量発生部の上下面に等しい厚さ
でかつコンデンサ容量有効セラミツク層よりも厚
い内部配線用セラミツク層が形成してあるコンデ
ンサ内蔵セラミツク多層基板。1 Each effective ceramic layer of the capacitor capacitance generating section is thin and formed approximately at the center in the thickness direction of the substrate,
A ceramic multilayer board with a built-in capacitor, in which a ceramic layer for internal wiring is formed on the upper and lower surfaces of the capacitor capacitance generating portion, and is thicker than the capacitor capacitance effective ceramic layer.