JPH0320047A - Semicondcutor device - Google Patents
Semicondcutor deviceInfo
- Publication number
- JPH0320047A JPH0320047A JP15546689A JP15546689A JPH0320047A JP H0320047 A JPH0320047 A JP H0320047A JP 15546689 A JP15546689 A JP 15546689A JP 15546689 A JP15546689 A JP 15546689A JP H0320047 A JPH0320047 A JP H0320047A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- drain
- source
- region
- ion implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 230000005669 field effect Effects 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000012535 impurity Substances 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 5
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 108091006146 Channels Proteins 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置に関し、更に詳しくは接合型電界
効果トランジスタ（以下、ＪＰＥＴと略す）に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and more particularly to a junction field effect transistor (hereinafter abbreviated as JPET).
従来の技術
近年，低周波増幅回路やアナログスイッチング回路では
、ノイズ低減のためＪＦ冨τが利用されている。2. Description of the Related Art In recent years, JF τ has been used for noise reduction in low frequency amplifier circuits and analog switching circuits.
第３図は，従来のＪＰＥＴの断面を示すものである。１
はソース・ドレイン電極２２は熱酸化膜（Ｓｉｎ２）
， ａｉｊｃ １１ ８法ニヨル酸化膜（Ｓｉｎ２）
，ａｌｒｉソース・ドレイン高濃度Ｎ型不純物領域、６
はゲート高濃度Ｐ型不純物領域、６ぱＰ型バックゲート
基板、７はＮ型チャネル領域，８は高濃度Ｐ型分離領域
である。FIG. 3 shows a cross section of a conventional JPET. 1
The source/drain electrode 22 is a thermal oxide film (Sin2)
, aijc 11 8 method nitrogen oxide film (Sin2)
, alri source/drain high concentration N-type impurity region, 6
6 is a gate high concentration P type impurity region, 6 is a P type back gate substrate, 7 is an N type channel region, and 8 is a high concentration P type isolation region.
発明が解決しようとする課題
上記従来の構成では，ゲート・ソース（ドレイン）間の
距離Ｌ。（Ｌ．，）が小さくなったとき、静電破壊耐圧
（以下、サージ耐圧と略す）も小さくなシ，素子の取υ
扱い上のトラブルや装着した電子装置の品質トラブルが
生じる。Problems to be Solved by the Invention In the above conventional configuration, the distance L between the gate and source (drain). When (L.,) becomes smaller, the electrostatic breakdown voltage (hereinafter abbreviated as surge voltage) also becomes smaller, and the element
This may cause handling problems or quality problems with the electronic devices installed.
サージ耐圧を大きくするには従来、次の方法があった。Conventionally, the following methods have been used to increase surge resistance.
■ Ｌ（｝＃（ＬＧＤ）を大きくして、ゲート・ソース
（ドレイン）間のシリース抵抗（以下、ｒ８ と称す）
を大きくする。しかし，チップサイズ，素子の大きさが
大きくなってしまう。■ Increase L(}#(LGD) to increase the series resistance between the gate and source (drain) (hereinafter referred to as r8)
Make it bigger. However, the chip size and element size become large.
■ 外付抵抗としてポリシリコン抵抗や，拡散抵抗を用
いることによクサージ耐圧を大きくする。■ Increase the quasage breakdown voltage by using a polysilicon resistor or a diffused resistor as an external resistor.
一方、拡散工程数が多く複雑になると共に、抵抗部分の
面積が加わり、チップ面積が大きくなる。On the other hand, the number of diffusion steps is large, making it complicated, and the area of the resistor portion is added, increasing the chip area.
■ チャネル領域の比抵抗を大きくすることによクサー
ジ耐圧を大きくする。しかし、ＪＦＩＣＴの諸特性（カ
ットオフ電圧，ゲート・ソース（ドレイン）耐圧等）を
変えないようにするためには、チップサイズ金大きくし
なければならないＯ
従来の方法では以上のような欠点を有していた。■ Increase the quasage breakdown voltage by increasing the specific resistance of the channel region. However, in order not to change the various characteristics of JFICT (cutoff voltage, gate-source (drain) breakdown voltage, etc.), the chip size must be increased. Was.
本発明の目的は、上記従来の問題点を解決するもので、
チップサイズ，諸特性を変えずにサージ耐圧の大きなＪ
ＦＥＴを提供するものである。The purpose of the present invention is to solve the above conventional problems,
J with large surge withstand voltage without changing chip size and various characteristics
FET is provided.
課題を解決するための手段
この目的を達成するために本発明のＪ Ｆ Ｅ ＴＦｉ
、ゲート・ソース（ドレイン）間に、ゲート形成時に選
択的にイオン注入処理を施して、フローティングゲート
を形成したものである。Means for Solving the Problems To achieve this object, the J F E TFi of the invention
, a floating gate is formed between the gate and source (drain) by selectively performing ion implantation treatment during gate formation.
作用
この発明によってＪＦＫＴのｒ８が大きくなるため，サ
ージ耐圧は大きくなる。Effect: Since the present invention increases r8 of the JFKT, the surge withstand voltage increases.
実施例
第１図は本発明の一実施例にかけるＪＦＥＴの要部断面
図である。このＪＦＩＣＴで符号１〜８で表わした各部
の構成は、第３図に示した従来例の場合と同じであク、
これらに加えてゲート・ソース（ドレイン）間にフロー
ティングゲート領域９を形成することによジ、サージ耐
圧を大きくすることができる。Embodiment FIG. 1 is a sectional view of a main part of a JFET according to an embodiment of the present invention. The configuration of each part represented by numerals 1 to 8 in this JFICT is the same as that of the conventional example shown in FIG.
In addition to these, by forming the floating gate region 9 between the gate and source (drain), surge and surge breakdown voltage can be increased.
第２図（ａ）〜（Ｃｌは上記実施例のＪＦＫＴの製造工
程を示す工程断面図である。１ず同図（１１のように膜
厚約ｓｏｏｏ人の熱酸化膜（Ｓ１０。）２をマスクとし
てボロンイオン注入’ｉ７Ｘ１０ ａｎ ．６０１
ＣｅＶの条件で選択的に施して、０２訃よびウェット０
２雰囲気中で拡散して，高濃度Ｐ型分離領域８ｆＪ：形
成する。さらに同図（ｂ）のように，所望ゲート形成部
分をフォトレジスＩｅマスクトシてエッチングし，熱酸
化膜２をマスクとしてボロンイオン注入’ｅ５Ｘ１０
ａｎ ．５０ＫｅＶの条件で選択的に施し、ゲート
高濃度Ｐ型不純物領域６とフローティングゲート領域９
を形成する。そして最終的には，ｃｖｎ法による酸化膜
（Ｓｉｎ２） ３Ｔｈ約６０００人蒸着し、これに選択
的に窓開けしたのが同図（Ｃｌであジ、このソース・ド
レインコンタクト窓にリンイオン注入ｉ５Ｘ１０ ａ
ｎ ．５０ＫｅＶで施した後、ソース・ドレイン電極
１を形成したものが第１図示の構造である。Figures 2(a) to (Cl are process cross-sectional views showing the manufacturing process of JFKT in the above example. 1) As shown in Figure 2, a thermal oxide film (S10) 2 with a film thickness of approximately Boron ion implantation as a mask 'i7X10 an .601
Selectively applied under CeV conditions to achieve 0.02 death and wet 0.
2 to form a high concentration P-type isolation region 8fJ:. Further, as shown in the same figure (b), the desired gate formation area is etched using a photoresist Ie mask, and boron ions are implanted using the thermal oxide film 2 as a mask.
an. The gate high concentration P-type impurity region 6 and the floating gate region 9 are selectively applied under the condition of 50 KeV.
form. Finally, approximately 6,000 oxide films (Sin2) 3Th were deposited using the CVN method, and windows were selectively opened in this (as shown in the figure).
n. The structure shown in FIG. 1 is obtained by forming source/drain electrodes 1 after applying at 50 KeV.
以上のように本実施例によれば、ゲート・ソース（ドレ
イン）間に、選択的にイオン注入処理を施して、７ロー
ティング・ゲート領域を形成することによク、サージ耐
圧が従来よりも２００Ｖ以上も大きくなった。As described above, according to this embodiment, by selectively performing ion implantation between the gate and source (drain) to form seven loading gate regions, the surge withstand voltage is higher than that of the conventional one. The voltage increased by more than 200V.
発明の効果
本発明によれば、ゲート・ソース（ドレイン）間に、選
択的にイオン注入処理を処して，フローティング・ゲー
ト領域を形成することにょジ、チップサイズ，諸特性を
変えずにサージ耐圧を大きくできる。Effects of the Invention According to the present invention, by selectively performing ion implantation between the gate and the source (drain) to form a floating gate region, the surge withstand voltage can be improved without changing the chip size or various characteristics. can be made larger.
第１図は本発明の一実施例におけるＪＦＥＴの要部断面
図、第２図（ａ）〜（Ｃ）は同実施例を製造する工程順
断面図、第３図は従来例装置の断面図である。
１・・・・・・ソース・ドレイン電極、２・・・・−・
熱酸化膜（Ｓｉｎ２）、３ −−−−−− Ｃ Ｖ Ｄ
法Ｋ ヨル酸化膜（Ｓｉｎ２）、４・・・・・・ソー
ス・ドレイン高濃度Ｎ型不純物領域、６・・・・・・ゲ
ート高濃度Ｐ型不純物領域、６・・・・・・Ｐ型バック
ゲート基板、７・・・・・・Ｎ型チャネル領域、８・・
・・・・高濃度Ｐ型分離領域、９・山・・フローティン
グ・ゲート領域。FIG. 1 is a sectional view of the main parts of a JFET according to an embodiment of the present invention, FIGS. 2(a) to (C) are sectional views in the order of steps for manufacturing the same embodiment, and FIG. 3 is a sectional view of a conventional device. It is. 1... Source/drain electrode, 2...-
Thermal oxide film (Sin2), 3 ------- C V D
Method K Dioxide film (Sin2), 4...Source/drain high concentration N type impurity region, 6...Gate high concentration P type impurity region, 6...P type Back gate substrate, 7...N-type channel region, 8...
...High concentration P-type isolation region, 9. Mountain...Floating gate region.
Claims (2)
、ゲート・ドレイン間にダイオードを設けた半導体装置
。(1) A semiconductor device in which a diode is provided between the gate and source and between the gate and drain of a junction field effect transistor.
された構造をしており、ゲートと同時にイオン注入処理
を選択的に行って形成されたフローティングゲート構造
を有した請求項１記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the diode has a structure in which the gate, source and drain are separated, and has a floating gate structure formed by selectively performing an ion implantation process at the same time as the gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15546689A JPH0320047A (en) | 1989-06-16 | 1989-06-16 | Semicondcutor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15546689A JPH0320047A (en) | 1989-06-16 | 1989-06-16 | Semicondcutor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0320047A true JPH0320047A (en) | 1991-01-29 |
Family
ID=15606669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15546689A Pending JPH0320047A (en) | 1989-06-16 | 1989-06-16 | Semicondcutor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0320047A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009043923A (en) * | 2007-08-08 | 2009-02-26 | Sanyo Electric Co Ltd | Semiconductor device, and manufacturing method of the same |
| JP2013509731A (en) * | 2009-11-02 | 2013-03-14 | アナログ デバイシス， インコーポレイテッド | Junction field effect transistor and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54133081A (en) * | 1978-04-06 | 1979-10-16 | Matsushita Electric Ind Co Ltd | Junction type field effect transistor |
| JPS6298674A (en) * | 1985-10-25 | 1987-05-08 | Hitachi Ltd | Gallium arsenide semiconductor device |
-
1989
- 1989-06-16 JP JP15546689A patent/JPH0320047A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54133081A (en) * | 1978-04-06 | 1979-10-16 | Matsushita Electric Ind Co Ltd | Junction type field effect transistor |
| JPS6298674A (en) * | 1985-10-25 | 1987-05-08 | Hitachi Ltd | Gallium arsenide semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009043923A (en) * | 2007-08-08 | 2009-02-26 | Sanyo Electric Co Ltd | Semiconductor device, and manufacturing method of the same |
| JP2013509731A (en) * | 2009-11-02 | 2013-03-14 | アナログ デバイシス， インコーポレイテッド | Junction field effect transistor and manufacturing method thereof |
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