JPH03194954A - Semiconductor device and electronic device mounted with the semiconductor device - Google Patents
Semiconductor device and electronic device mounted with the semiconductor deviceInfo
- Publication number
- JPH03194954A JPH03194954A JP1334137A JP33413789A JPH03194954A JP H03194954 A JPH03194954 A JP H03194954A JP 1334137 A JP1334137 A JP 1334137A JP 33413789 A JP33413789 A JP 33413789A JP H03194954 A JPH03194954 A JP H03194954A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- sealed
- heat sink
- semiconductor device
- semiconductor pellet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 341
- 239000011347 resin Substances 0.000 claims abstract description 155
- 229920005989 resin Polymers 0.000 claims abstract description 155
- 238000007789 sealing Methods 0.000 claims abstract description 137
- 239000008188 pellet Substances 0.000 claims abstract description 134
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 16
- 238000003860 storage Methods 0.000 claims description 13
- 239000003822 epoxy resin Substances 0.000 claims description 7
- 229920000647 polyepoxide Polymers 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 4
- 238000003825 pressing Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 8
- 230000005855 radiation Effects 0.000 abstract description 2
- 230000002265 prevention Effects 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 34
- 230000015654 memory Effects 0.000 description 32
- 238000000034 method Methods 0.000 description 24
- 230000000694 effects Effects 0.000 description 16
- 239000010949 copper Substances 0.000 description 14
- 239000010410 layer Substances 0.000 description 11
- 230000002093 peripheral effect Effects 0.000 description 10
- 101150076031 RAS1 gene Proteins 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 238000004806 packaging method and process Methods 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 229920002379 silicone rubber Polymers 0.000 description 5
- 239000004945 silicone rubber Substances 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000012966 insertion method Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 102100030218 Matrix metalloproteinase-19 Human genes 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 101001003186 Oryza sativa subsp. japonica Alpha-amylase/subtilisin inhibitor Proteins 0.000 description 2
- 101150045048 Ras85D gene Proteins 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 102100031584 Cell division cycle-associated 7-like protein Human genes 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 101000777638 Homo sapiens Cell division cycle-associated 7-like protein Proteins 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- UGKDIUIOSMUOAW-UHFFFAOYSA-N iron nickel Chemical compound [Fe].[Ni] UGKDIUIOSMUOAW-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000013022 venting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野〕
本発明は、樹脂封止型半導体装置及びそれを実装した電
子装置に適用して有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a technique that is effective when applied to a resin-sealed semiconductor device and an electronic device in which the same is mounted.
大型高速コンピュータ、パーソナルコンピュータ等の記
憶装置は半導体記憶装置で構成される。Storage devices such as large-scale high-speed computers and personal computers are composed of semiconductor storage devices.
特に、大容量化が目的とされる半導体記憶装置にはＤＲ
ＡＭ（旦ｙｎａｍｉｃ Ｒａｎｄｏｍ八ｃｅｅへｓ Ｍ
ｅｍｏｒｙ）が使用される。In particular, DR is required for semiconductor storage devices whose purpose is to increase capacity.
AM (Dan dynamic Random 8cee M
emory) is used.
前記ＤＲＡＭは、−殻内に、大容量の記憶装置を構成す
るために多数個使用されるので、比較的コストが安い樹
脂封止型半導体装置で構成される。Since a large number of DRAMs are used in a shell to construct a large-capacity storage device, the DRAM is constructed of a relatively inexpensive resin-sealed semiconductor device.
樹脂封止型半導体装置は、その実装形式に基づき、ＤＩ
Ｐ（旦ｕａｌ工ｎ−１ｉｎｅ Ｐ ａｃｋａｇｅ）、Ｓ
ＯＰ（Ｓｍａｌｌ ０ ｕｔ−１ｉｎｅ Ｐ ａｃｋａ
ｇｅ）或はＺ Ｉ Ｐ （Ｚｉｇｚａｇ Ｉ ｎ−１ｉ
ｎｅ Ｐ ａｃｋａｇｅ）構造等で構成される。Resin-sealed semiconductor devices have DI based on their mounting format.
P (Danual engineering n-1ine package), S
OP (Small 0 ut-1ine Packa
ge) or Z I P (Zigzag I n-1i
nePackage) structure, etc.
前記樹脂封止型半導体装置は、インナーリードに外部端
子（ポンディングパッド）が電気的に接続された半導体
ペレットを樹脂（レジン）で気密封止したものが、基本
的な構造である。前記半導体ペレットはタブ上に搭載さ
れ、半導体ペレットの外部端子、インナーリードの夫々
はボンディングワイヤを介して電気的に接続される。樹
脂は前記半導体ペレット、ボンディングワイヤ、タブ及
びインナーリードを被覆する。インナーリードにはアウ
ターリード（外部ピン）が一体に構成され（電気的に接
続され）、このアウターリードは樹脂の外部に突出され
る。The basic structure of the resin-sealed semiconductor device is that a semiconductor pellet, in which an external terminal (ponding pad) is electrically connected to an inner lead, is hermetically sealed with resin. The semiconductor pellet is mounted on a tab, and external terminals and inner leads of the semiconductor pellet are electrically connected via bonding wires. The resin covers the semiconductor pellet, bonding wire, tab, and inner lead. An outer lead (external pin) is integrally configured (electrically connected) to the inner lead, and this outer lead is projected to the outside of the resin.
この種の樹脂封止型半導体装置は、メモリボード（実装
基板）上に複数個実装され、コンピュータに記憶装置（
メモリモジュール）として組込まれる。Multiple resin-sealed semiconductor devices of this type are mounted on a memory board (mounting board), and are installed in a computer as a storage device (
memory module).
メモリボードへの樹脂封止型半導体装置（ＤＲＡＭ）の
実装に際しては１個の樹脂封止型半導体装置の実装面積
（サイズ）が実装密度を左右する。記憶装置の大容量化
（又は小型化）を図るためには実装密度を高くすること
が要求される。When mounting a resin-sealed semiconductor device (DRAM) on a memory board, the mounting area (size) of one resin-sealed semiconductor device determines the packaging density. In order to increase the capacity (or reduce the size) of a storage device, it is required to increase the packaging density.
このような技術課題を解決するには、特開昭６３−５２
４９８号公報に記載される技術を適用することが有効で
ある。前記公報に記載される技術は、モジュール基板上
にその実装面に対して垂直方向に複数個の樹脂封止型半
導体装置を積層する技術である２、つまり、この技術が
適用された場合、メモリボード上での高さ方向を利用し
て実装密度を高めることができるので、記憶装置の大容
量化を図ることができる。In order to solve such technical problems, it is necessary to
It is effective to apply the technique described in Publication No. 498. The technology described in the above publication is a technology in which a plurality of resin-sealed semiconductor devices are stacked on a module board in a direction perpendicular to its mounting surface2.In other words, when this technology is applied, the memory Since the mounting density can be increased by utilizing the height direction on the board, it is possible to increase the capacity of the storage device.
前述の樹脂封止型半導体装置及びそれをメモリボード上
に実装した記憶装置について、本発明者は下記の問題点
が生じることを見出した。The inventors of the present invention have found that the following problems occur with the resin-sealed semiconductor device and the storage device in which it is mounted on a memory board.
（１）メモリボード上に複数個の樹脂封止型半導体装置
を積層する組立作業において、上下夫々の樹脂封止型半
導体装置間、アウターリード間の位置合せ作業等が追加
される。各位置合せ作業は作業能率を高める目的で治具
を使用する。位置合せ作業の終了後、半田等の接合剤を
使用し、メモリボード上に樹脂封止型半導体装置を複数
個積層する（実装する）。このように、前記組立作業に
位置合せ作業等の余分な作業工程が追加されるので、組
立作業が長くなる。また、作業工程が追加されると、例
えばＤＩＰ構造を採用する樹脂封止型半導体装置ではア
ウターリード°の折れ曲り等の損傷が生じる確率が高く
なり、この結果、組立作業における歩留りが低下する。(1) In the assembly work of stacking a plurality of resin-sealed semiconductor devices on a memory board, alignment work is added between the upper and lower resin-sealed semiconductor devices and between outer leads. Each positioning task uses a jig to increase work efficiency. After the alignment work is completed, a plurality of resin-sealed semiconductor devices are stacked (mounted) on the memory board using a bonding agent such as solder. In this way, extra work steps such as positioning work are added to the assembly work, which lengthens the assembly work. Further, when additional work steps are added, for example, in a resin-sealed semiconductor device employing a DIP structure, the probability of damage such as bending of the outer lead increases, resulting in a decrease in yield in the assembly work.
（２）メモリボード上に複数個の樹脂封止型半導体装置
を積層した場合、積層されたうちの中段又は下段に積層
された樹脂封止型半導体装置は、その周囲を他の樹脂封
止型半導体装置で覆われる。(2) When multiple resin-sealed semiconductor devices are stacked on a memory board, the resin-sealed semiconductor device stacked in the middle or lower layer of the stack is surrounded by other resin-sealed semiconductor devices. Covered with semiconductor devices.
つまり、前記中段又は下段に積層された樹脂封止型半導
体装置は外部雰囲気と接触できる表面積が少なくなる。In other words, the resin-sealed semiconductor devices stacked in the middle or lower layer have a smaller surface area that can come into contact with the external atmosphere.
このため、半導体ペレットの動作で発生する熱の放熱経
路において、熱抵抗が増大するので、樹脂封止型半導体
装置の放熱効率が低下する。For this reason, thermal resistance increases in the heat dissipation path for heat generated by the operation of the semiconductor pellet, and the heat dissipation efficiency of the resin-sealed semiconductor device decreases.
（３）前記樹脂封止型半導体装置は半導体ペレットの素
子形成面及びそれと対向する裏面（タブ倒）を含む全表
面を樹脂封止部で被覆する。通常、樹脂封止部は、高温
度でモールド後に冷却して硬化させるので、熱収縮に基
づく反りを低減するために、樹脂封止部の半導体ペレッ
トの素子形成面上での厚さに対して裏面側をほぼ同等の
厚さで構成する。このため、樹脂封止部の裏面側の厚さ
に律則され、樹脂封止部の全体の厚さが厚くなるので。(3) In the resin-sealed semiconductor device, the entire surface of the semiconductor pellet, including the element-forming surface and the back surface (tab-down) facing the semiconductor pellet, is covered with a resin-sealed portion. Normally, the resin encapsulation part is molded at high temperature and then cooled and hardened, so in order to reduce warpage due to thermal contraction, the thickness of the resin encapsulation part on the element formation surface of the semiconductor pellet must be The back side is constructed with approximately the same thickness. For this reason, the thickness of the resin-sealed portion on the back side is limited, and the overall thickness of the resin-sealed portion becomes thick.
メモリボード上の高さ方向において、実装密度を高める
ことに限界がある。There is a limit to increasing the mounting density in the height direction on the memory board.
（４）また、前記樹脂封止部の裏面側の厚さを薄くした
場合、前述のように、樹脂封止部に反りを生じ、樹脂封
止部の割れ、樹脂封止部と半導体ペレットとの間に剥離
等が生じる。前記割れ、剥離等は、樹脂封止部の外部と
半導体ペレットとの間の水分の伝達経路として作用し、
樹脂封止型半導体装置の耐湿性を低下する。(4) Furthermore, if the thickness of the back side of the resin sealing part is made thinner, as mentioned above, the resin sealing part may warp, the resin sealing part may crack, and the resin sealing part may become separated from the semiconductor pellet. Peeling etc. occur during this period. The cracks, peeling, etc. act as a moisture transmission path between the outside of the resin sealing part and the semiconductor pellet,
Decreases the moisture resistance of resin-sealed semiconductor devices.
（５）また、ＳＯＰ構造等の面実装方式を採用する樹脂
封止型半導体装置において、前記樹脂封止部の反りは、
メモリボードの端子とアウターリードとの接触不良を一
部に引き起こす。つまり、樹脂封止型半導体装置は実装
不良となる。(5) Furthermore, in a resin-sealed semiconductor device that employs a surface-mounting method such as an SOP structure, warpage of the resin-sealed portion may be caused by
This may cause poor contact between the memory board's terminals and the outer leads. In other words, the resin-sealed semiconductor device becomes defective in mounting.
（６）メモリボード上に複数個の樹脂封止型半導体装置
を積層した場合、上下夫々の樹脂封止型半導体装置の位
置合せにずれが生じると、上下夫々のアウターリード間
に接触不良が生じる。つまり、樹脂封止型半導体装置は
実装不良を生じる。(6) When multiple resin-sealed semiconductor devices are stacked on a memory board, if the alignment of the upper and lower resin-sealed semiconductor devices is misaligned, poor contact will occur between the upper and lower outer leads. . In other words, the resin-sealed semiconductor device causes mounting defects.
（７）また１片面のみを樹脂封止すると温度サイクルで
反りを生じ上下樹脂封止部のリードの接合部に力が加わ
り、断線につながる恐れがある。(7) Furthermore, if only one side is resin-sealed, it may warp due to temperature cycles, and force may be applied to the joints of the leads in the upper and lower resin-sealed parts, leading to wire breakage.
本発明の目的は、樹脂封止型半導体装置において、組立
作業における歩留りを向上することが可能な技術を提供
することにある。An object of the present invention is to provide a technique that can improve the yield in assembly work in a resin-sealed semiconductor device.
本発明の他の目的は、樹脂封止型半導体装置において、
放熱効率を向上することが可能な技術を提供することに
ある。Another object of the present invention is to provide a resin-sealed semiconductor device,
The objective is to provide technology that can improve heat dissipation efficiency.
本発明の他の目的は、樹脂封止型半導体装置において、
信頼性を向上することが可能な技術を提供することにあ
る。Another object of the present invention is to provide a resin-sealed semiconductor device,
The objective is to provide technology that can improve reliability.
本発明の他の目的は、樹脂封止型半導体装置を実装する
電子装置において、実装密度を向上することが可能な技
術を提供することにある。Another object of the present invention is to provide a technique that can improve the packaging density in an electronic device that mounts a resin-sealed semiconductor device.
本発明の他の目的は、樹脂封止型半導体装置を実装する
電子装置において、実装不良を防止することが可能な技
術を提供することにある。Another object of the present invention is to provide a technique that can prevent mounting defects in an electronic device in which a resin-sealed semiconductor device is mounted.
本発明の前記ならびにその他の目的と新規な特徴は１本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち１代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of one typical invention disclosed in this application is as follows.
（１）インナーリードに外部端子が電気的に接続された
半導体ペレットを樹脂封止部で封止する樹脂封止型半導
体装置において、前記半導体ペレットの素子形成面と対
向する裏面に、この裏面に比べて大きな平面々積を有す
る放熱板を設け、この放熱板の周囲の一部の領域を除き
、この放熱板の前記半導体ペレットを搭載する表面側が
前記半導体ペレットを被覆しかつ凸部を有し、放熱板の
前記表面と対向する裏面側が前記凸部と嵌合できる形状
で形成された凹部を有する樹脂封止部を設ける。この樹
脂封止型半導体装置は前記半導体ペレットの素子形成面
に対して垂直方向に複数個積層される。また、前記半導
体ペレットはＤＲＡＭ、ＳＲＡＭ、ＥＰＲＯＭ、ＥＥＰ
ＲＯＭ等の記憶装置からなる。(1) In a resin-sealed semiconductor device in which a semiconductor pellet in which an external terminal is electrically connected to an inner lead is sealed with a resin sealing part, a resin-sealed semiconductor pellet is provided on the back surface of the semiconductor pellet that faces the element formation surface. A heat sink having a relatively large planar area is provided, and except for a part of the area around the heat sink, the surface side of the heat sink on which the semiconductor pellet is mounted covers the semiconductor pellet and has a convex portion. A resin sealing portion is provided on a back side of the heat sink opposite to the front surface, the resin sealing portion having a recess formed in a shape capable of fitting with the projection. A plurality of resin-sealed semiconductor devices are stacked in a direction perpendicular to the element forming surface of the semiconductor pellet. Further, the semiconductor pellet is used for DRAM, SRAM, EPROM, EEP.
It consists of a storage device such as ROM.
（２）インナーリードに外部端子が電気的に接続された
半導体ペレットを樹脂封止部で封止する樹脂封止型半導
体装置において、前記半導体ペレットの素子形成面と対
向する裏面に、この裏面に比べて大きな平面々積を有す
る放熱板を設け、この放熱板の周囲の一部の領域を除き
、この放熱板の前記半導体ペレットを搭載する表面側が
前記半導体ペレット及び放熱板の周囲を被覆し、かつ放
熱板の前記表面と対向する裏面側が放熱板の周囲を被覆
する樹脂封止部を設ける。(2) In a resin-sealed semiconductor device in which a semiconductor pellet, in which an external terminal is electrically connected to an inner lead, is sealed with a resin sealing part, a resin-sealed semiconductor pellet is provided on the back surface of the semiconductor pellet that faces the element forming surface. A heat sink having a relatively large planar area is provided, and except for a part of the area around the heat sink, the surface side of the heat sink on which the semiconductor pellet is mounted covers the semiconductor pellet and the periphery of the heat sink, Further, a resin sealing portion is provided on the back side of the heat sink, which is opposite to the front surface, and covers the periphery of the heat sink.
（３）前記手段（２）の放熱板には、その周囲にこの放
熱板の表面側、裏面側の夫々の樹脂封止部を連結する貫
通孔を設ける２
（４）インナーリードに外部端子が電気的に接続された
半導体ペレットを樹脂封止部で封止する樹脂封止型半導
体装置において、前記半導体ペレットの素子形成面と対
向する裏面に、この裏面に比べて大きな平面々積を有す
る放熱板を設け、この放熱板の前記半導体ペレットを搭
載した表面側に前記半導体ペレットを被覆し、かつこの
半導体ペレットの素子形成面上の厚さを前記放熱板の厚
さの１．９〜６．０倍で形成した樹脂封止部を設ける。(3) The heat dissipation plate of the above means (2) is provided with a through hole around the heat dissipation plate that connects the resin sealing parts on the front side and the back side of the heat dissipation plate. (4) An external terminal is connected to the inner lead. In a resin-sealed semiconductor device in which an electrically connected semiconductor pellet is sealed with a resin sealing portion, a heat dissipation device having a back surface opposite to an element forming surface of the semiconductor pellet that has a larger planar area than the back surface. A plate is provided, and the surface side of the heat sink on which the semiconductor pellet is mounted is coated with the semiconductor pellet, and the thickness of the semiconductor pellet on the element forming surface is 1.9 to 6 times the thickness of the heat sink. A resin sealing portion formed at 0x is provided.
（５）前記手段（４）の樹脂封止部をエポキシ系樹脂で
形成し、前記放熱板をＣｕ系材料で形成する。(5) The resin sealing portion of the means (4) is formed of an epoxy resin, and the heat sink is formed of a Cu-based material.
（６）前記手段（５）の樹脂封止部の半導体ペレットの
素子形成面上の厚さは前記放熱板の厚さの３．０〜４．
０倍で形成される。(6) The thickness of the resin sealing portion of the means (5) on the element forming surface of the semiconductor pellet is 3.0 to 4.0 times the thickness of the heat sink.
Formed at 0x.
（７）インナーリードに外部端子が電気的に接続された
半導体ペレットを樹脂封止部で封止する樹脂封止型半導
体装置において、前記半導体ペレットの表面側及びこの
表面側と対向する裏面側を被覆すると共に、前記表面側
に凸部を有しかつ前記裏面側に前記凸部と嵌合できる形
状で形成された凹部を有する樹脂封止部を設け、この樹
脂封止部の表面側の凸部の周囲に裏面側の凹部の周囲ま
で引き回されたアウターリードを設け、このアウターリ
ードの前記表面側又は裏面側の一部分のリード幅を他部
分に比べて太く構成する。(7) In a resin-sealed semiconductor device in which a semiconductor pellet in which an external terminal is electrically connected to an inner lead is sealed with a resin sealing part, the front side of the semiconductor pellet and the back side opposite to this front side are At the same time, a resin sealing part having a convex part on the front side and a recess formed in a shape that can fit with the convex part on the back side is provided, and the convex part on the front side of the resin sealing part is provided. An outer lead is provided around the part to the periphery of the recess on the back side, and the lead width of a part of the outer lead on the front side or the back side is configured to be thicker than other parts.
（８）前記手段（７）のアウターリードの前記表面側又
は裏面側には、積層される他の樹脂封止型半導体装置の
アウターリードと適度な押圧力で接触できるばね性を設
ける。(8) The front or back side of the outer lead of the means (7) is provided with spring properties that allow it to come into contact with the outer leads of other stacked resin-sealed semiconductor devices with an appropriate pressing force.
［作 用〕
上述した手段（１）によれば、（Ａ）前記樹脂封止型半
導体装置の樹脂封止部の凸部及び凹部をガイドとして、
上下方向に複数個の樹脂封止型半導体装置を積層できる
。この複数個積層された樹脂封止型半導体装置は電子装
置において２次元的な（平面方向の）実装密度を高めら
れる。（Ｂ）また、前記樹脂封止型半導体装置の樹脂封
止部から放熱板を突出させ、半導体ペレットから樹脂封
止部の外部に抜ける熱放出経路を確保したので、半導体
ペレットの動作で発生する熱の放熱効率を向上できる。[Function] According to the above-mentioned means (1), (A) using the convex portions and concave portions of the resin-sealed portion of the resin-sealed semiconductor device as guides,
A plurality of resin-sealed semiconductor devices can be stacked vertically. A plurality of stacked resin-sealed semiconductor devices can increase the two-dimensional (planar direction) packaging density in an electronic device. (B) Also, since the heat sink is made to protrude from the resin sealing part of the resin sealing type semiconductor device, and a heat release path is secured from the semiconductor pellet to the outside of the resin sealing part, heat generated by the operation of the semiconductor pellet is secured. Heat dissipation efficiency can be improved.
この放熱板は、樹脂封止型半導体装置を上下方向に複数
個積層した場合でも、各段特に上段及び下段に挾まれた
中段に位置する樹脂封止型半導体装置の放熱経路を確保
し、この中段に位置する樹脂封止型半導体装置の放熱効
率を向上できる。（Ｃ）また、前記樹脂封止型半導体装
置の半導体ペレットの裏面側の大半を樹脂封止部に変え
て放熱板としたことによって、樹脂封止部の全体の厚さ
を薄くできる。この結果、複数個積層された樹脂封止型
半導体装置は電子装置において３次元的な（高さ方向の
）実装密度を高めることができる。Even when multiple resin-sealed semiconductor devices are stacked vertically, this heat dissipation plate secures a heat dissipation path for the resin-sealed semiconductor devices in each layer, especially the middle layer sandwiched between the upper and lower layers. The heat dissipation efficiency of the resin-sealed semiconductor device located in the middle can be improved. (C) Furthermore, by replacing most of the back side of the semiconductor pellet of the resin-sealed semiconductor device with a resin-sealed portion and use it as a heat sink, the overall thickness of the resin-sealed portion can be reduced. As a result, a plurality of stacked resin-sealed semiconductor devices can increase the three-dimensional (height direction) packaging density in an electronic device.
上述した手段（２）によれば、前記手段（１）の効果（
Ｂ）及び（Ｃ）の他に、前記樹脂封止型半導体装置の樹
脂封止部を放熱板の表面側から裏面側に向ってこの放熱
板の周囲に設けたので（放熱板の周囲に樹脂封止部が食
い込む構造としたので）、樹脂封止部と放熱板との界面
での剥離を低減できる。この剥離の低減は、樹脂封止部
の外部から半導体ペレットに達する水分の伝達経路を遮
断できるので、樹脂封止型半導体装置の耐湿性を向上で
きる。According to the above-mentioned means (2), the effect of the above-mentioned means (1) (
In addition to B) and (C), since the resin-sealed portion of the resin-sealed semiconductor device was provided around the heat sink from the front side to the back side of the heat sink (resin was placed around the heat sink). Since the structure is such that the sealing part bites into the resin sealing part, peeling at the interface between the resin sealing part and the heat sink can be reduced. This reduction in peeling can block the transmission path of moisture reaching the semiconductor pellet from the outside of the resin-sealed portion, thereby improving the moisture resistance of the resin-sealed semiconductor device.
上述した手段（３）によれば、前記手段（２）の効果の
他に、前記放熱板の貫通孔を通して、放熱板の表面側、
裏面側の夫々の樹脂封止部を連結し、樹脂封止部と放熱
板との接着強度をより高められるので、樹脂封止部と放
熱板との界面での剥離をより低減し、樹脂封止型半導体
装置の耐湿性をより向上できる。According to the above-mentioned means (3), in addition to the effect of the above-mentioned means (2), the surface side of the heat sink through the through hole of the heat sink,
The resin sealing parts on the back side are connected to each other, and the adhesive strength between the resin sealing part and the heat sink can be further increased, so peeling at the interface between the resin sealing part and the heat sink is further reduced, and the resin sealing Moisture resistance of the fixed type semiconductor device can be further improved.
上述した手段（４）によれば、前記手段（１）の効果（
Ｂ）及び（Ｃ）の他に、前記樹脂封止型半導体装置の樹
脂封止部、放熱板の夫々の熱膨張係数差を許容範囲内に
設定し、樹脂封止部の反りを低減できるので、実装基板
上の端子とすべてのアウターリードとの接触が確実に行
え、樹脂封止型半導体装置の実装不良を防止できる。According to the above-mentioned means (4), the effect of the above-mentioned means (1) (
In addition to B) and (C), warpage of the resin-sealed portion can be reduced by setting the difference in coefficient of thermal expansion between the resin-sealed portion and the heat sink of the resin-sealed semiconductor device within an allowable range. This ensures reliable contact between the terminals on the mounting board and all the outer leads, and prevents mounting defects in the resin-sealed semiconductor device.
また、上下パッケージのリードの接合部に力が加わるの
をおさえることができるため、断線を防止できる。Further, since force can be suppressed from being applied to the joints between the leads of the upper and lower packages, disconnection can be prevented.
上述した手段（５）によれば、前記樹脂封止部、放熱板
の夫々の線膨張係数をほぼ均一化できるので、樹脂封止
部の反りを低減し、樹脂封止型半導体装置の実装不良を
低減できると共に、樹脂封止部に比べて放熱板のヤング
率が約１桁高いので、放熱板の厚さを薄くし、樹脂封止
型半導体装置の高さ方向のサイズを縮小できる。According to the above-mentioned means (5), the coefficients of linear expansion of the resin sealing portion and the heat sink can be made almost uniform, thereby reducing warpage of the resin sealing portion and preventing mounting defects of the resin sealing type semiconductor device. In addition, since the Young's modulus of the heat sink is about one order of magnitude higher than that of the resin-sealed portion, the thickness of the heat sink can be reduced, and the size of the resin-sealed semiconductor device in the height direction can be reduced.
上述した手段（６）によれば、前記樹脂封止部、放熱板
の夫々の線熱膨張差をほとんどなくすことができる（は
ぼＯにできる）ので、より樹脂封止型半導体装置の実装
不良を低減できる。According to the above-mentioned means (6), it is possible to almost eliminate the difference in linear thermal expansion between the resin sealing portion and the heat sink (it can be reduced to O), thereby further reducing the possibility of mounting defects in the resin sealing type semiconductor device. can be reduced.
上述した手段（７）によれば、前記手段（１）の効果（
Ａ）の他に、前記樹脂封止型半導体装置のアウターリー
ドの一部分のリード幅を太くし、このアウターリードに
、上又は下方向に積層された他の樹脂封止型半導体装置
の同一機能を有するアウターリードが接触できる面積を
拡大したので、両者アウターリード間の電気的接続を確
実に行い、積層された樹脂封止型半導体装置間の電気的
接触不良を防止できる。According to the above-mentioned means (7), the effect of the above-mentioned means (1) (
In addition to A), the lead width of a portion of the outer lead of the resin-sealed semiconductor device is made thicker, and the same function of another resin-sealed semiconductor device stacked upwardly or downwardly is applied to this outer lead. Since the contact area of the outer leads is increased, the electrical connection between the two outer leads can be ensured, and poor electrical contact between the stacked resin-sealed semiconductor devices can be prevented.
上述した手段（８）によれば、前記樹脂封止型半導体装
置のアウターリードに設けたばね性で、上又は下方向に
積層された他の樹脂封止型半導体装置の同一機能を有す
るアウターリードとの電気的な接触を確実に行うことが
できるので、積層された樹脂封止型半導体装置間の電気
的接触不良を防止できる。According to the above-mentioned means (8), the spring property provided on the outer lead of the resin-sealed semiconductor device allows the outer lead to have the same function as that of another resin-sealed semiconductor device stacked upwardly or downwardly. Since electrical contact can be made reliably, poor electrical contact between stacked resin-sealed semiconductor devices can be prevented.
以下、本発明の構成について、半導体ペレットにＤＲＡ
Ｍを搭載した樹脂封止型半導体装置及びそれを実装した
電子装置に本発明を適用した実施例とともに説明する。Below, regarding the structure of the present invention, DRA is applied to semiconductor pellets.
The present invention will be described along with an example in which the present invention is applied to a resin-sealed semiconductor device equipped with M and an electronic device mounted thereon.
なお、実施例を説明するための全回において、同一機能
を有するものは同一符号を付け、その繰り返しの説明は
省略する。Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
（実施例Ｉ）
本発明の実施例Ｉである面実装方式を採用する樹脂封止
型半導体装置の基本的構造を第１図（要部断面図）、第
２図（側面図）及び第３図（平面図）で示す、第１図に
示す断面図は第３図のＩ−Ｉ切断線で切った断面図であ
る。また、第２図は第３図の■−■線から見た側面図で
ある。(Example I) The basic structure of a resin-sealed semiconductor device adopting a surface-mounting method, which is Example I of the present invention, is shown in FIG. 1 (cross-sectional view of main parts), FIG. The sectional view shown in FIG. 1 (plan view) is a sectional view taken along the line II in FIG. 3. Moreover, FIG. 2 is a side view seen from the line ■-■ in FIG. 3.
第１図乃至第３図に示すように、本実施例Ｉの樹脂封止
型半導体装置１は樹脂封止部（レジンモールド部）８の
周囲の一側面にアウターリード（外部ビン）４Ｂを複数
配列する。つまり、樹脂封止型半導体装置１は、シング
ルインラインパッケージ構造で構成され、面実装方式で
構成される。As shown in FIGS. 1 to 3, the resin-sealed semiconductor device 1 of Example I has a plurality of outer leads (external bins) 4B on one side around the resin-sealed part (resin mold part) 8. Arrange. In other words, the resin-sealed semiconductor device 1 has a single in-line package structure and is configured using a surface mounting method.
この樹脂封止型半導体装置１は、第１図に示すように、
放熱板７、半導体ペレット２、インナーリード４Ａの夫
々を順次積み重ねて構成される６前記放熱板７、半導体
ペレット２の夫々の間には絶縁性接着剤６が設けられる
。半導体ペレット２、インナーリード４Ａの夫々の間に
は絶縁性フィルム３が設けられる。This resin-sealed semiconductor device 1, as shown in FIG.
An insulating adhesive 6 is provided between each of the heat sink 7 and the semiconductor pellet 2, which are constructed by stacking the heat sink 7, the semiconductor pellet 2, and the inner lead 4A in sequence. An insulating film 3 is provided between each of the semiconductor pellet 2 and the inner lead 4A.
前記インナーリード４Ａ、アウターリード４Ｂの夫々は
、第４図（組立工程中でのリードフレームの平面図）に
示すように、同一のリードフレーム４から構成される。Each of the inner leads 4A and outer leads 4B is constructed from the same lead frame 4, as shown in FIG. 4 (a plan view of the lead frame during the assembly process).
リードフレーム４は一枚の板状で構成され、このリード
フレーム４に打抜き加工を又はエツチング加工を施すこ
とによりインナーリード４Ａ、アウターリード４Ｂ等が
形成される。つまり、インナーリード４Ａ、アウターリ
ード４Ｂの夫々は一体に成型される（電気的に接続され
る）。第４図に示すリードフレーム４は１個の樹脂封止
型半導体装置ｌを形成する一部の領域しか示していない
。通常、リードフレーム４は、複数個例えば６個の樹脂
封止型半導体装Ｍ１を形成できる領域を有する（例えば
６連フレーム）。The lead frame 4 is formed of a single plate, and the inner leads 4A, outer leads 4B, etc. are formed by punching or etching the lead frame 4. That is, the inner lead 4A and the outer lead 4B are each integrally molded (electrically connected). The lead frame 4 shown in FIG. 4 shows only a part of the area forming one resin-sealed semiconductor device l. Usually, the lead frame 4 has a region in which a plurality of, for example, six, resin-sealed semiconductor devices M1 can be formed (for example, a six-row frame).
前記インナーリード４Ａはアウターリード４Ｂ側の一端
側においてアウターリード４Ｂと一体に成型される。こ
のインナーリード４Ａの他端（ボンディング領域側）は
、樹脂封止部８の一側面から半導体ペレット２の素子形
成面上の中央部まで、樹脂封止部８内において引き回さ
れる。前記アウターリード４Ｂはその中央部分において
タイバー４Ｃに一体化され、このタイバー４０はリード
フレーム４の外枠４Ｅに一体化され支持される。また、
アウターリード４Ｂのインナーリード４Ａと一体化され
た側と反対側の端部はリードフレーム４の内枠４Ｄに一
体化され、この内枠４Ｄは外枠４Ｅに一体化され支持さ
れる。リードフレーム４の外枠４Ｅに配列された穴部４
Ｆは、リードフレーム４に半導体ペレット２を固着する
所謂ぺ何工程、ボンディング工程等において、搬送用又
は位置決め用の穴として使用される。The inner lead 4A is molded integrally with the outer lead 4B at one end on the outer lead 4B side. The other end (bonding region side) of the inner lead 4A is routed within the resin sealing part 8 from one side of the resin sealing part 8 to the center portion on the element formation surface of the semiconductor pellet 2. The outer lead 4B is integrated with a tie bar 4C at its central portion, and this tie bar 40 is integrated with and supported by the outer frame 4E of the lead frame 4. Also,
The end of the outer lead 4B opposite to the side integrated with the inner lead 4A is integrated with an inner frame 4D of the lead frame 4, and this inner frame 4D is integrated with and supported by the outer frame 4E. Holes 4 arranged in the outer frame 4E of the lead frame 4
F is used as a hole for transportation or positioning in the so-called PE process, bonding process, etc. in which the semiconductor pellet 2 is fixed to the lead frame 4.
リードフレーム４は電気伝導性、熱伝導性１機械的強度
等・に優れた例えば鉄−ニッケル（Ｆｅ−Ｎｉ）合金（
例えばＮｉの含有量は４２［％］）で形成される。この
リードフレーム４は例えば１５０［μｍ］の厚さで形成
される。リードフレーム４のうち、インナーリード４Ａ
の他端側の先端部の表面つまりボンディング領域には、
ボンダビリティを向上する例えば銀（Ａｇ）メツキ層４
ａが設けられる。また、リードフレーム４としては、前
記Ｆｅ−Ｎｉ合金の他に、それに比べて電気伝導性、熱
伝導性等に優れたＣｕ又はＣｕ系合金で形成してもよい
。The lead frame 4 is made of, for example, an iron-nickel (Fe-Ni) alloy (Fe-Ni) that has excellent electrical conductivity, thermal conductivity, mechanical strength, etc.
For example, the Ni content is 42%). This lead frame 4 is formed to have a thickness of, for example, 150 [μm]. Inner lead 4A of lead frame 4
On the surface of the tip on the other end, that is, in the bonding area,
For example, silver (Ag) plating layer 4 to improve bondability.
a is provided. In addition to the Fe--Ni alloy, the lead frame 4 may be made of Cu or a Cu-based alloy, which has superior electrical conductivity, thermal conductivity, etc. compared to the Fe--Ni alloy.
前記アウターリード４Ｂは、標準規格に基づき、各端子
に番号が付され、夫々に印加される信号が規定される。In the outer lead 4B, each terminal is numbered based on the standard, and the signals applied to each terminal are defined.
前述のように、インナーリード４Ａはアウターリード４
Ｂと一体に成型されるので。As mentioned above, the inner lead 4A is the outer lead 4.
Because it is molded integrally with B.
インナーリード４Ａに印加される信号はアウターリード
４Ｂに印加される信号と同様である。これに限定されな
いが、本実施例■の樹脂封止型半導体装置１は後述する
１ ６ ［Ｍｂｉｔｌ（又は４［Ｍｂｉｔｌ）の大容量
を有するＤＲＡＭが半導体ペレット２に搭載される。こ
のため、第１図乃至第４図中、樹脂封止型半導体装置１
は、左端から右端に向って１番端子、２番端子、・・・
２６番端子の夫々が順次配列される。つまり、樹脂封
止型半導体装置１は合計２６端子（２６ピン）で構成さ
れる。The signal applied to the inner lead 4A is similar to the signal applied to the outer lead 4B. Although not limited thereto, in the resin-sealed semiconductor device 1 of this embodiment (2), a DRAM having a large capacity of 1 6 Mbitl (or 4 Mbitl), which will be described later, is mounted on the semiconductor pellet 2. For this reason, in FIGS. 1 to 4, the resin-sealed semiconductor device 1
From the left end to the right end, terminal 1, terminal 2, etc.
Each of the 26th terminals is arranged in sequence. That is, the resin-sealed semiconductor device 1 includes a total of 26 terminals (26 pins).
例えば、前記アウターリード４Ｂに印加される信号とし
ては、制御系信号、アドレス系信号、データ系信号、電
源の夫々がある。制御系信号は、ロウアドレスストロー
ブ系信号ＲＡＳ、カラムアドレスストローブ信号ＣＡＳ
、ライトイネーブル信号ＷＥ等がある。データ系信号は
データ出力信号Ｄｏｕｔ 、データ入力信号Ｄｉｎの夫
々がある。電源は、基準電源電圧Ｖｓｓ例えば回路の接
地電位Ｏ［Ｖ］、動作電源電圧Ｖｃｃ例えば回路の動作
電圧５［Ｖ］の夫々がある。For example, the signals applied to the outer lead 4B include control system signals, address system signals, data system signals, and power supply signals. Control system signals include row address strobe system signal RAS and column address strobe signal CAS.
, write enable signal WE, etc. The data system signals include a data output signal Dout and a data input signal Din. The power supplies include a reference power supply voltage Vss, for example, a circuit ground potential O [V], and an operating power supply voltage Vcc, for example, a circuit operating voltage 5 [V].
前記アウターリード４Ｂには、第１図乃至第４図に示す
ように、樹脂封止部８の上側の表面（後述するガイド用
凸部８Ａの周囲）において接触部４ｈａが設けられる。As shown in FIGS. 1 to 4, the outer lead 4B is provided with a contact portion 4ha on the upper surface of the resin sealing portion 8 (around a guide convex portion 8A to be described later).
接触部４ｈａはそれ以外のアウターリード４Ｂに比べて
大きいリード幅で構成される。接触部４ｈａは、複数個
の樹脂封止型半導体装置１を積層した場合に、上側に積
層された樹脂封止型半導体装置１のアウターリード４Ｂ
の末端部４ｂｂに接触される（電気的に接続される）。The contact portion 4ha has a larger lead width than the other outer leads 4B. When a plurality of resin-sealed semiconductor devices 1 are stacked, the contact portion 4ha is connected to the outer lead 4B of the resin-sealed semiconductor device 1 stacked on the upper side.
is contacted (electrically connected) to the end portion 4bb of the terminal 4bb.
なお、前記接触部４Ｂａは、アウターリード４Ｂの末端
部４ｂｂに相当する位置つまり樹脂封止部８の下側の表
面（後述するガイド用凹部８Ｂの周囲）において設けて
もよい。The contact portion 4Ba may be provided at a position corresponding to the end portion 4bb of the outer lead 4B, that is, on the lower surface of the resin sealing portion 8 (around the guide recess 8B, which will be described later).
また、アウターリード４Ｂの末端部４ｂｂは、第１図に
示すように、水平面に対して所定角度θ下側に（例えば
放熱板７の裏面と平行な面に対してそれから離隔する方
向に約１〜３度の）傾きを持って構成される。つまり、
末端部４ｂｂは、複数個の樹脂封止型半導体装置１を積
層した場合、下側に積層された樹脂封止型半導体装置１
のアウターリード４Ｂの接触部４ｂａの表面を適度に押
圧するばね性を持って構成される。Further, as shown in FIG. 1, the end portion 4bb of the outer lead 4B is positioned at a predetermined angle θ below the horizontal plane (for example, approximately 1 It is constructed with an inclination of ~3 degrees). In other words,
When a plurality of resin-sealed semiconductor devices 1 are stacked, the terminal portion 4bb is located at the bottom of the stacked resin-sealed semiconductor device 1.
The contact portion 4ba of the outer lead 4B is configured to have a spring property that appropriately presses the surface of the contact portion 4ba.
前記半導体ペレット２は前記第３図及び第４図に示すよ
うに樹脂封止部８の中央部分に配置される。半導体ペレ
ット２は平面長方形状の単結晶珪素基板で形成される。The semiconductor pellet 2 is placed in the center of the resin sealing part 8, as shown in FIGS. 3 and 4. The semiconductor pellet 2 is formed of a single crystal silicon substrate having a rectangular planar shape.
半導体ペレット２の素子形成面（インナーリード４Ａに
対向する面）には前述のように１６ ［Ｍｂｉｔ］の大
容量を有するＤＲＡＭが搭載される。ＤＲＡＭはフォー
ルプツトピットライン方式（２交点方式）で構成される
。この半導体ペレット２に搭載されたＤＲＡＭの構成は
第６図（チップレイアウト図）に示す。As described above, a DRAM having a large capacity of 16 [Mbit] is mounted on the element forming surface of the semiconductor pellet 2 (the surface facing the inner lead 4A). The DRAM is constructed using a fall pit line method (two-intersection method). The structure of the DRAM mounted on this semiconductor pellet 2 is shown in FIG. 6 (chip layout diagram).
第６図に示すように、半導体ペレット２の素子形成面に
搭載されたＤＲＡＭは半導体ペレット２の素子形成面の
ほぼ全面にメモリセルアレイＭＡＲＹを配置する。この
メモリセルアレイＭＡＲＹは、同第６図中、６４個に細
分化され配置される。As shown in FIG. 6, in the DRAM mounted on the element formation surface of the semiconductor pellet 2, a memory cell array MARY is arranged almost over the entire element formation surface of the semiconductor pellet 2. As shown in FIG. 6, this memory cell array MARY is subdivided and arranged into 64 cells.
細分化された１つのメモリセルアレイＭＡＲＹは２５６
［Ｋｂｉｔｌの容量で構成される。前記６４個に細分
化されたメモリセルアレイＭＡＲＹは、第６図中、左上
の１６個、右上の１６個、左下の１６個、右下の１６個
を夫々１つのブロックとし、１６個毎に４個のブロック
を構成する。One subdivided memory cell array MARY has 256
[Constructed with a capacity of Kbitl. In the memory cell array MARY, which is subdivided into 64 cells, in FIG. Configure blocks.
前記６４個に細分化されたうちの２個のメモリセルアレ
イＭＡＲＹ間にはセンスアンプ回路ＳＡが配置される。A sense amplifier circuit SA is arranged between two of the 64 subdivided memory cell arrays MARY.
また、６４個に細分化されたメモリセルアレイＭＡＲＹ
の夫々の半導体ペレット２の中央側には直接系周辺回路
であるロウアドレスデコーダ回路ＸＤＥＣ及びワードド
ライバ回路ＷＤが配置される。In addition, the memory cell array MARY is subdivided into 64 pieces.
At the center of each semiconductor pellet 2, a row address decoder circuit XDEC and a word driver circuit WD, which are direct peripheral circuits, are arranged.
前記４個のブロックのうち、左上、左下の夫々のブロッ
ク間には直接系周辺回路であるカラムアドレスデコーダ
回路ＹＤＥＣ及び周辺回路ＭＣが配置される。同様に、
右上、右下の夫々のブロック間にはカラムアドレスデコ
ーダ回路ＹＤＥＣ及び周辺回路ＭＣが配置される。前記
周辺回路ＭＣは、間接系周辺回路であり、例えばＲＡＳ
系回路。Among the four blocks, a column address decoder circuit YDEC and a peripheral circuit MC, which are direct peripheral circuits, are arranged between the upper left and lower left blocks. Similarly,
A column address decoder circuit YDEC and a peripheral circuit MC are arranged between the upper right and lower right blocks. The peripheral circuit MC is an indirect peripheral circuit, for example, RAS.
system circuit.
ＣＡＳ系回路、アドレスバッファ回路、電源リミッタ回
路等が配置される。前記直接系周辺回路、間接系周辺回
路の夫々は基本的に相補型ＭＩＳＦＥＴとバイポーラト
ランジスタとを組合せて構成される。A CAS system circuit, an address buffer circuit, a power supply limiter circuit, etc. are arranged. Each of the direct peripheral circuit and indirect peripheral circuit is basically constructed by combining a complementary MISFET and a bipolar transistor.
前記４個のブロックのうち、左上、右上の夫々のブロッ
ク間及び左下、右下の夫々のブロック間には複数個の外
部端子（ポンディングパッド）ＢＰが配置される。つま
り、この外部端子ＢＰは、第６図中、半導体ペレット２
の中央部分を長方形状の長手方向に向って（上方から下
方に向って）複数個配置される。Among the four blocks, a plurality of external terminals (ponding pads) BP are arranged between the upper left and upper right blocks and between the lower left and lower right blocks. In other words, this external terminal BP is connected to the semiconductor pellet 2 in FIG.
A plurality of them are arranged in the longitudinal direction of the rectangular shape (from the top to the bottom).
前記６４個に細分化されたメモリセルアレイＭＡＲＹの
夫々には１ ［ｂｉｔ］の情報を保持するメモリセルが
行列状に複数配置される。メモリセルはメモリセル選択
用ＭＩＳＦＥＴと情報蓄積用容量素子との直列回路で構
成される。In each of the 64 subdivided memory cell arrays MARY, a plurality of memory cells each holding 1 [bit] of information are arranged in a matrix. The memory cell is constituted by a series circuit of a memory cell selection MISFET and an information storage capacitive element.
前記半導体ペレット１の外部端子ＢＰは、前記第１図に
示すように、インナーリード４Ａの先端側（ボンディン
グ領域）に電気的に接続される。この接続はボンディン
グワイヤ５で行われる。ボンディングワイヤ５は例えば
金（Ａｕ）ワイヤを使用する。ボンディングワイヤ５は
これに限定されないがボール・ボンディング法でボンデ
ィングされる。ボール・ボンディング法は、ボンディン
グワイヤ５の一端側に金属ボールを形成し、この金属ボ
ールを熱圧着に超音波振動を併用して外部端子ＢＰにボ
ンディングする方式である。ボンディングワイヤ５の他
端側は同様に熱圧着に超音波振動を併用してインナーリ
ード４Ａの表面（Ａｇメツキ層４ａの表面）にボンディ
ングされる。また、前記ボンディングワイヤ５としては
ＣｕワイヤやＡＱワイヤを使用してもよい。As shown in FIG. 1, the external terminal BP of the semiconductor pellet 1 is electrically connected to the tip side (bonding region) of the inner lead 4A. This connection is made with bonding wires 5. For example, a gold (Au) wire is used as the bonding wire 5. The bonding wire 5 is bonded by a ball bonding method, although the method is not limited thereto. The ball bonding method is a method in which a metal ball is formed on one end side of the bonding wire 5, and this metal ball is bonded to the external terminal BP using thermocompression bonding and ultrasonic vibration. The other end of the bonding wire 5 is similarly bonded to the surface of the inner lead 4A (the surface of the Ag plating layer 4a) using thermocompression bonding in combination with ultrasonic vibration. Further, as the bonding wire 5, a Cu wire or an AQ wire may be used.
前記インナーリード４Ａと半導体ペレット２の素子形成
面との間に設けられた絶縁性フィルム３は、主に両者間
を電気的に分離し、かつ両者間を接着する目的で形成さ
れる。絶縁性フィルム３は例えば熱硬化性樹脂であるポ
リイミド系樹脂フィルムで形成される。このポリイミド
系栢脂フィルムは例えば１００〜３００［μｍ］程度の
厚さで形成される。また、必要に応じて、絶縁性フィル
ム３の表面には接着剤層を設ける。絶縁性フィルム３は
、前記第３図又は第４図に示す半導体ペレット２の平面
形状と実質的に同様の形状で、又はインナーリード４Ａ
と半導体ペレット２との間に。The insulating film 3 provided between the inner lead 4A and the element forming surface of the semiconductor pellet 2 is formed mainly for the purpose of electrically isolating the two and adhering the two. The insulating film 3 is formed of, for example, a polyimide resin film that is a thermosetting resin. This polyimide resin film is formed to have a thickness of, for example, about 100 to 300 [μm]. Moreover, an adhesive layer is provided on the surface of the insulating film 3, if necessary. The insulating film 3 has a planar shape substantially similar to the planar shape of the semiconductor pellet 2 shown in FIG. 3 or FIG. 4, or the inner lead 4A.
and semiconductor pellet 2.
又はインナーリード４Ａのほんの一部分だけに形成する
。このように、樹脂封止型半導体装置ｌは半導体ペレッ
ト２の素子形成面上にインナーリード４Ａを引き回した
構造で構成され、この種の構造はＬ ＯＧ （Ｌｅａｄ
Ｏｎ Ｃｈｉｐ）構造と呼ばれる。Alternatively, it is formed only in a small portion of the inner lead 4A. In this way, the resin-sealed semiconductor device 1 has a structure in which the inner leads 4A are routed on the element forming surface of the semiconductor pellet 2, and this type of structure is called LOG (Lead
This is called an on-chip structure.
前記放熱板（放熱フィン）７は、前記第１図、第３図及
び第５図（部品平面図）に示すように、半導体ペレット
２の裏面（素子形成面と対向する面）に設けられる。放
熱板７は、半導体ペレット２の平面々積に比べて大きく
構成され、樹脂封止部８のほぼ全域及び樹脂封止部８の
アウターリード４Ｂが配列された側と対向する反対側に
突出して構成される６つまり、放熱板７は、樹脂封止部
８の外部に一部を突出させ（露出させ）た状態で樹脂封
止部８に封止される。また、放熱板７は、半導体ペレッ
ト２を搭載した領域部分において、半導体ペレット２を
搭載した面と対向する反対面が樹脂封止部８から露出さ
れる。The heat dissipation plate (heat dissipation fin) 7 is provided on the back surface (the surface facing the element forming surface) of the semiconductor pellet 2, as shown in FIGS. 1, 3, and 5 (component plan view). The heat dissipation plate 7 is configured to be larger than the planar area of the semiconductor pellet 2, and protrudes almost over the entire area of the resin sealing part 8 and to the opposite side of the resin sealing part 8 facing the side on which the outer leads 4B are arranged. In other words, the heat dissipation plate 7 is sealed in the resin sealing part 8 with a part thereof protruding (exposed) to the outside of the resin sealing part 8. Further, in the region where the semiconductor pellet 2 is mounted, the opposite surface of the heat sink 7 facing the surface on which the semiconductor pellet 2 is mounted is exposed from the resin sealing portion 8 .
前記放熱板７は、熱伝導性に優れ、樹脂封止部８との線
膨張係数（熱膨張係数：α）が近く、シかも機械的強度
（ヤング率又は曲げ弾性率：Ｅ）が高い材料で形成する
０例えば、放熱板７は銅（Ｃｕ：αは約１７ ｘ １０
−’［１／”Ｃ］、Ｅは約１１００００［ＭＰａ］）で
形成する。後述するが樹脂封止部８はフェノール硬化型
エポキシ系樹脂（αは約２１ Ｘ １０−’［１／’Ｃ
］、Ｅは約１４０００ＣＭＰ ａ］）で形成するので、
Ｃｕは樹脂封止部８に比べてほぼ等しい線膨張係数を有
しかつ約１桁高いヤング率を有する。前記放熱板７はＣ
ｕで形成する場合例えば約６０〜１８０［μｍ］の厚さ
で形成する。The heat dissipation plate 7 is made of a material that has excellent thermal conductivity, has a linear expansion coefficient (thermal expansion coefficient: α) close to that of the resin sealing part 8, and has high mechanical strength (Young's modulus or flexural modulus: E). For example, the heat sink 7 is made of copper (Cu: α is approximately 17 x 10
-'[1/'C], E is about 110,000 [MPa]).As will be described later, the resin sealing part 8 is made of phenol-curing epoxy resin (α is about 21 x 10-'[1/'C]).
], E is approximately 14000CMP a]), so
Cu has a coefficient of linear expansion that is approximately the same as that of the resin sealing portion 8, and a Young's modulus that is approximately one order of magnitude higher. The heat sink 7 is C
When formed with a thickness of, for example, about 60 to 180 [μm].
放熱板７は例えばＣｕ板にエツチング加工を施して又は
打抜き加工を施して形成する。本実施例■は、Ｃｕ板か
ら複数個連結した状態の放熱板７をエツチング加工で形
成し、この後、連結部分を切断し、個々の放熱板７を形
成する。第５図において、複数個の放熱板７の連結部７
Ｂは平面凹形状で構成され、この連結部７Ｂのみを切断
することにより、放熱板７の連結部７Ｂ以外の周囲に切
断によるはりが発生しない。The heat sink 7 is formed, for example, by etching or punching a Cu plate. In this embodiment (2), a plurality of connected heat sink plates 7 are formed from Cu plates by etching, and then the connected portions are cut to form individual heat sink plates 7. In FIG. 5, a connecting portion 7 of a plurality of heat sinks 7
B has a concave planar shape, and by cutting only this connecting portion 7B, no beams are generated around the heat dissipating plate 7 other than the connecting portion 7B.
この放熱板７は、半導体ペレット２の動作で発生する熱
を樹脂封止部８の内部から外部に放出する熱伝達経路の
熱抵抗を低減できる。特に、樹脂封止型半導体装置１を
複数個積層した場合において、上段及び下段の樹脂封止
型半導体装置１で挾まれた中段の樹脂封止型半導体装１
ｉ！１の熱伝達経路を確保できる。また、放熱板７は、
後述するが、樹脂封止部８の半導体ペレット２の下側を
廃止しく放熱板フに変え）、樹脂封止部８の厚さを薄く
し、樹脂封止型半導体装置１の高さ方向（半導体ペレッ
ト２の素子形成面に垂直な方向）のサイズを縮小できる
。This heat dissipation plate 7 can reduce the thermal resistance of the heat transfer path that releases heat generated by the operation of the semiconductor pellet 2 from the inside of the resin sealing part 8 to the outside. In particular, when a plurality of resin-sealed semiconductor devices 1 are stacked, the middle resin-sealed semiconductor device 1 is sandwiched between the upper and lower resin-sealed semiconductor devices 1.
i! 1 heat transfer path can be secured. Moreover, the heat sink 7 is
As will be described later, the lower side of the semiconductor pellet 2 in the resin sealing part 8 is replaced with a heat sink), the thickness of the resin sealing part 8 is made thinner, and the thickness of the resin sealing part 8 is reduced in the height direction of the resin sealing type semiconductor device 1 ( The size of the semiconductor pellet 2 in the direction perpendicular to the element formation surface can be reduced.
前記放熱板７は、第１図及び第５図に示すように、樹脂
封止部８内において、周囲に複数個の貫通穴７Ａが配置
される。貫通穴７Ａは、樹脂封止部８の平面方形状の周
囲の各辺に沿って細長い形状で形成され、半導体ペレッ
ト２の搭載面側の表面からその裏面まで貫抜ける通し穴
で構成される。As shown in FIGS. 1 and 5, the heat dissipation plate 7 has a plurality of through holes 7A arranged around the resin sealing portion 8. As shown in FIGS. The through hole 7A is formed in an elongated shape along each side of the periphery of the planar rectangular shape of the resin sealing portion 8, and is configured as a through hole that penetrates from the surface of the semiconductor pellet 2 on the mounting surface side to the back surface thereof.
この貫通穴７Ａは、放熱板７（又は樹脂封止部８）の周
囲において、放熱板７の表面側の樹脂封止部８、裏面側
の樹脂封止部８の夫々を連結させ、放熱板フ、樹脂封止
部８の夫々の接着強度を高めることができる。なお、貫
通穴７Ａの平面形状は、前述の平面形状に限定されず、
方形状、円形状、楕円形状等で形成してもよい。This through hole 7A connects each of the resin sealing part 8 on the front side of the heat sink 7 and the resin sealing part 8 on the back side of the heat sink 7 around the heat sink 7 (or resin sealing part 8). F. The adhesive strength of each of the resin sealing parts 8 can be increased. Note that the planar shape of the through hole 7A is not limited to the above-mentioned planar shape,
It may be formed in a rectangular shape, a circular shape, an elliptical shape, etc.
前記放熱板７．半導体ペレット２の夫々の間に設けられ
た絶縁性接着剤６は、基本的には非導電性を有し、両者
間の線膨張係数差に基づく応力を低減できる軟質性を有
しくＥが小さい方が良い）、かつ熱伝導性に優れたもの
が好ましい、絶縁性接着剤６としては例えばシリコーン
ゴムを使用する。The heat sink plate7. The insulating adhesive 6 provided between each of the semiconductor pellets 2 is basically non-conductive, has softness that can reduce stress due to the difference in linear expansion coefficient between the two, and has a small E. For example, silicone rubber is used as the insulating adhesive 6, which is preferably one having excellent thermal conductivity.
シリコーンゴムは、極端に厚く塗布することが難しく、
又極端に薄く塗布するとボイドが発生したり、応力緩和
能力が低下するので、例えば約１０〜３０［ｕｍｌの膜
厚で塗布される。絶縁性接着剤６は、前記第３図、第４
図又は第５図に示す半導体ペレット２の平面形状と実質
的に同様の形状でかつほぼ同等のサイズ（組立工程中に
合せが必要な場合はその分若干大きく）構成される。Silicone rubber is difficult to apply extremely thickly.
Furthermore, if applied extremely thinly, voids may occur or the stress relaxation ability will be reduced, so the film is applied to a thickness of, for example, about 10 to 30 [uml]. The insulating adhesive 6 is shown in FIGS. 3 and 4 above.
It has a substantially similar planar shape to the planar shape of the semiconductor pellet 2 shown in FIG.
前記樹脂封止部８は、前記第１図乃至第５図に示すよう
に、主に半導体ペレット２、インナーリード４Ａ、放熱
板７の一部の夫々を被覆する。つまり、樹脂封止部８は
、放熱板フの外部に突出する領域を除き、放熱板７の表
面側において、放熱板７の周囲（貫通穴７Ａよりも外周
）、放熱板７の表面上、及び半導体ペレット２の表面上
に設けられる。この樹脂封止部８の表面側には中央部分
に断面台形状のガイド用凸部８Ａが構成される。このガ
イド用凸部８Ａは、半導体ペレット２の厚さで生じる段
差形状を利用し、この段差形状にほぼ沿って樹脂封止部
８の表面形状を成型することにより形成される。樹脂封
止部８の半導体ペレット２の素子形成面上の厚さは本実
施例夏において例えば約３５０［ｕｍｌで形成され、前
記ガイド用凸部８Ａの高さは例えば約２００［ｕｍｌで
形成される。ガイド用凸部８Ａの周囲の端部は適度なテ
ーパ角を有しく例えば４５度）、このガイド用凸部８Ａ
は上側に樹脂封止型半導体装置１を積Ｍする場合、又は
上側に積層された樹脂封止型半導体装置１を取り外す場
合にスムーズな作業が行える形状で構成される。The resin sealing portion 8 mainly covers each of the semiconductor pellet 2, the inner lead 4A, and a portion of the heat sink 7, as shown in FIGS. 1 to 5. In other words, the resin sealing part 8 is formed on the surface side of the heat sink 7, around the heat sink 7 (outer circumference of the through hole 7A), on the surface of the heat sink 7, except for the area protruding to the outside of the heat sink 7. and provided on the surface of the semiconductor pellet 2. A guiding convex portion 8A having a trapezoidal cross section is formed in the center portion of the front surface side of the resin sealing portion 8. The guide convex portion 8A is formed by making use of a step shape caused by the thickness of the semiconductor pellet 2 and molding the surface shape of the resin sealing portion 8 substantially along the step shape. The thickness of the resin sealing portion 8 on the element forming surface of the semiconductor pellet 2 is, for example, approximately 350 uml in the summer of this embodiment, and the height of the guide convex portion 8A is, for example, approximately 200 uml. Ru. The peripheral edge of the guide convex portion 8A has an appropriate taper angle (for example, 45 degrees), and this guide convex portion 8A
is configured in a shape that allows smooth operation when stacking the resin-sealed semiconductor device 1 on the upper side or when removing the resin-sealed semiconductor device 1 stacked on the upper side.
また、樹脂封止部８は、同様に放熱板７の外部に突出す
る領域を除き、放熱板７の裏面側において、放熱板７の
周囲（貫通穴７Ａを覆う領域）に設けられる。つまり、
樹脂封止部８は、放熱板７の表面側から裏面側の周囲に
回し込む回し込み部８Ｃが設けられる。この樹脂封止部
８の裏面側には、中央部分に、放熱板７及び樹脂封止部
８で形成された、断面台形状のガイド用凹部８Ｂが構成
される。このガイド用凹部８Ｂは前記ガイド用凸部８Ａ
と勘合できる形状つまりガイド用凸部８Ａとほぼ同一の
形状を持って構成される。樹脂封止部８の裏面側の厚さ
は放熱板７の周囲において例えば約４００［ｕｍｌで形
成され、前記ガイド用凹部８Ｂの深さは例えば約２００
［ｕｍｌで形成される。Similarly, the resin sealing portion 8 is provided around the heat sink 7 (the area covering the through hole 7A) on the back side of the heat sink 7, except for the area protruding to the outside of the heat sink 7. In other words,
The resin sealing part 8 is provided with a winding part 8C that winds around the heat dissipation plate 7 from the front side to the back side. On the back side of the resin sealing part 8, a guide recess 8B having a trapezoidal cross section is formed in the center by the heat sink 7 and the resin sealing part 8. This guide concave portion 8B is the guide convex portion 8A.
It is configured to have a shape that can be fitted with the guide convex portion 8A, that is, a shape that is almost the same as that of the guide convex portion 8A. The thickness of the resin sealing part 8 on the back surface side is, for example, about 400 uml around the heat sink 7, and the depth of the guide recess 8B is, for example, about 200 uml.
[formed in uml.
ガイド用凹部８Ｂの周囲の端部はガイド用凸部８Ａと同
様に適度なテーパ角を有し、このガイド用凹部８Ｂは前
述と同様にスムーズな作業が行える形状で構成される。The peripheral end of the guide recess 8B has an appropriate taper angle like the guide convex part 8A, and the guide recess 8B has a shape that allows smooth operation as described above.
前記樹脂封止部８は例えばフェノール硬化型エポキシ系
樹脂で形成される。このフェノール硬化型エポキシ系樹
脂にはシリコーンゴム及びフィラーが添加される６シリ
コーンゴムは、若干量添加され、フェノール硬化型エポ
キシ系樹脂の弾性率を低減させる作用がある。フィラー
は、球形の酸化珪素粒で形成され、熱膨張率を低減させ
る作用がある。The resin sealing portion 8 is made of, for example, a phenol-curable epoxy resin. Silicone rubber and filler are added to this phenol-curable epoxy resin.6 Silicone rubber is added in a small amount and has the effect of reducing the elastic modulus of the phenol-curable epoxy resin. The filler is formed of spherical silicon oxide particles and has the effect of reducing the coefficient of thermal expansion.
このように構成される樹脂封止型半導体装置１は、樹脂
封止部８の半導体ペレット２の下側を放熱板７に変えて
樹脂封止部８の厚さを薄く構成し、しかもこの薄膜化に
基づく樹脂封止部８の反りを低減している。第７図は、
樹脂封止型半導体装置１の放熱板７の厚さと樹脂封止部
８の反り量との関係を示す。第７図において、横軸は放
熱板７の厚さｔ ３ （［ｍ ｍｌ）を示す。縦軸は樹
脂封止部８の反り量δ（［ｕｍｌ）を示す、第７図中に
示す樹脂封止型半導体装置１の模式図において、ｔｌは
半導体ペレット２の厚さであり、この厚さｔｌは４００
［ｕｍｌに設定される。ｔ２は樹脂封止部８の厚さであ
り、この厚さｔ２は３５０［ｕｍｌに設定される１本実
施例Ｉにおいては１６ ［Ｍｂｉｔ］の大容量のＤＲＡ
Ｍが半導体ペレット２に搭載され、前記第１図及び第３
図に示すように、樹脂封止部８の全体の占有面積に対す
る半導体ペレット２の占有面積の割合が大きい。この種
の樹脂封止型半導体装置１においては、樹脂封止部８の
反り量δが、樹脂封止部８の半導体ペレット２の素子形
成面上の厚さｔ２に律則される。つまり、前記反り量δ
は、半導体ペレット２の厚さｔｌ及び樹脂封止部８の半
導体ペレット２の周囲の厚さをほとんど無視することが
でき、放熱板７の厚さｔ３及び樹脂封止部８の半導体ペ
レット２の素子形成面上の厚さｔ２でほぼ一議的に規定
される。The resin-sealed semiconductor device 1 configured as described above has a structure in which the lower side of the semiconductor pellet 2 of the resin-sealed portion 8 is replaced with a heat sink 7 to reduce the thickness of the resin-sealed portion 8. This reduces the warping of the resin sealing portion 8 due to corrosion. Figure 7 shows
The relationship between the thickness of the heat sink 7 of the resin-sealed semiconductor device 1 and the amount of warpage of the resin-sealed portion 8 is shown. In FIG. 7, the horizontal axis indicates the thickness t 3 ([m ml)] of the heat sink 7. In FIG. In the schematic diagram of the resin-sealed semiconductor device 1 shown in FIG. 7, where the vertical axis indicates the amount of warpage δ ([uml) of the resin-sealed portion 8, tl is the thickness of the semiconductor pellet 2, and this thickness Satl is 400
[Set to uml. t2 is the thickness of the resin sealing part 8, and this thickness t2 is set to 350 [uml].In this embodiment I, a large capacity DRA of 16 [Mbit] is used.
M is mounted on the semiconductor pellet 2, and as shown in FIGS.
As shown in the figure, the ratio of the area occupied by the semiconductor pellet 2 to the entire area occupied by the resin sealing part 8 is large. In this type of resin-sealed semiconductor device 1, the amount of warpage δ of the resin-sealed portion 8 is determined by the thickness t2 of the resin-sealed portion 8 on the element formation surface of the semiconductor pellet 2. In other words, the amount of warpage δ
The thickness tl of the semiconductor pellet 2 and the thickness around the semiconductor pellet 2 in the resin sealing part 8 can be almost ignored, and the thickness t3 of the heat sink 7 and the thickness of the semiconductor pellet 2 in the resin sealing part 8 can be almost ignored. It is almost universally defined by the thickness t2 on the element forming surface.
第７図に示すように、約１７５［’Ｃ］の高温度でモー
ルドし、約２５［”Ｃ］の常温で冷却硬化させた樹脂封
止部８は、放熱板７の厚さｔ３が薄い場合には樹脂封止
部８の熱収縮が支配的となり、樹脂封止部８側に反りが
生じる（反り量δが負になる）。As shown in FIG. 7, the resin sealing part 8 molded at a high temperature of about 175 ['C] and cooled and hardened at room temperature of about 25 ["C] has a thin thickness t3 of the heat dissipation plate 7. In this case, thermal contraction of the resin sealing part 8 becomes dominant, and warpage occurs on the resin sealing part 8 side (the amount of warpage δ becomes negative).
逆に、樹脂封止部８は、放熱板７の厚さし３が厚い場合
には放熱板７のヤング率が支配的となり、放熱板７側に
反りが生じる（反り量δが正になる）。Conversely, when the thickness 3 of the heat dissipation plate 7 is large, the Young's modulus of the heat dissipation plate 7 becomes dominant, and warpage occurs on the heat dissipation plate 7 side (the amount of warpage δ becomes positive). ).
本実施例Ｉの樹脂封止型半導体装［１は、反り量δが±
５０［μｍ］を越えると、平担度が損なわれ、実装基板
上に実装した場合、複数本のうちの一部のアウターリー
ド４Ｂが接触しない実装不良を生じる。放熱板７を前述
のようにＣｕで形成した場合、樹脂封止部８の反り量δ
を±５０［μｍ］の範囲内に押えて平担度を確保するに
は、放熱板７の厚さｔ３は約６０〜１８０［μｍ］の厚
さになる。The resin-sealed semiconductor device of Example I [1 has a warpage amount δ of ±
If it exceeds 50 [μm], the flatness will be impaired, and when mounted on a mounting board, a mounting failure will occur in which some of the outer leads 4B do not come into contact with each other. When the heat sink 7 is made of Cu as described above, the amount of warpage δ of the resin sealing part 8 is
In order to maintain the flatness within the range of ±50 [μm], the thickness t3 of the heat sink 7 is approximately 60 to 180 [μm].
つまり、樹脂封止部８の厚さｔ２は放熱板７の厚さｔ３
の約１．９〜６．０倍に設定する必要がある。In other words, the thickness t2 of the resin sealing part 8 is the thickness t3 of the heat sink 7.
It is necessary to set the value to approximately 1.9 to 6.0 times.
また、樹脂封止部８の反り量δをほとんどなくすには（
反り量δをほぼ０にするには）、放熱板７の厚さｔ３は
約８０〜１２０［μｍ］の厚さつまり樹脂封止部８の厚
さｔ２は放熱板７の３．０〜４．０倍の厚さに設定する
必要がある。In addition, in order to almost eliminate the amount of warpage δ of the resin sealing part 8, (
In order to make the amount of warpage δ almost 0), the thickness t3 of the heat sink 7 is about 80 to 120 [μm], that is, the thickness t2 of the resin sealing part 8 is 3.0 to 4 μm of the heat sink 7. It is necessary to set the thickness to .0 times.
また、第７図に示すように、放熱板７を設けずに、半導
体ペレット２の下側を樹脂封止部８で構成した場合、反
り量δをなくすには、樹脂封止部８は半導体ペレット２
の素子形成面上の厚さｔ２と同等の厚さが下側に必要と
される。Further, as shown in FIG. 7, when the lower side of the semiconductor pellet 2 is configured with the resin sealing part 8 without providing the heat dissipation plate 7, in order to eliminate the amount of warpage δ, the resin sealing part 8 is pellet 2
A thickness equivalent to the thickness t2 on the element formation surface is required on the lower side.
また、同第７図に示すように、放熱板７をＦｅ−Ｎｉ合
金で形成した場合、Ｃｕと同様に反り量δを小さくでき
る。ところが、Ｆｅ−Ｎｉ合金は、ヤング率がＣｕに比
べて大きいために、約２００［μｍ１以上の厚さに形成
しないと１反り量δを小さくできない。換言すれば、放
熱板７は、Ｃｕで形成することにより、薄くしても充分
に反り量δを小くできるので、樹脂封止部８の厚さを薄
くできる特徴がある。Furthermore, as shown in FIG. 7, when the heat sink 7 is made of a Fe-Ni alloy, the amount of warpage δ can be reduced as in the case of Cu. However, since the Fe-Ni alloy has a larger Young's modulus than Cu, the amount of warpage δ cannot be reduced unless it is formed to a thickness of about 200 μm or more. In other words, by forming the heat dissipation plate 7 with Cu, the amount of warpage δ can be sufficiently reduced even if the heat dissipation plate 7 is made thin, so that the thickness of the resin sealing portion 8 can be made thin.
次に、前述の樹脂封止型半導体装置１の樹脂封止（レジ
ンモールド）について、第８図及び第９図（樹脂封止工
程中における金型の断面図）を用いて簡単に説明する。Next, the resin sealing (resin mold) of the resin-molded semiconductor device 1 described above will be briefly explained using FIGS. 8 and 9 (cross-sectional views of the mold during the resin sealing process).
第８図は、前記第１図と同一方向から見た樹脂封止型半
導体装置１の側面と金型の断面とを示す、第９図は、前
記第２図と同一方向から見た樹脂封止型半導体装［１の
側面と金型の断面とを示す。8 shows a side surface of the resin-sealed semiconductor device 1 and a cross section of the mold seen from the same direction as FIG. 1, and FIG. 9 shows the resin-sealed semiconductor device 1 seen from the same direction as FIG. 2. A side view of a stop-type semiconductor device [1] and a cross section of a mold are shown.
第８図及び第９図に示すように、樹脂封止型半導体装Ｉ
１の樹脂封止部８を形成する金型は下型２０及び上型２
１で構成される。下型２０は樹脂封止部８のリードフレ
ーム４よりも下側の形状を形成する。つまり、下型２０
は、半導体ペレット２及び放熱板）のすべての領域を収
納できるキャビティを有し、ガイド用凹部８Ｂを形成す
る領域２０Ｂ１回し込み部８Ｃを形成する領域２０Ｃを
有する。また、下型２０は、樹脂封止時にキャビティ内
の空気を外部に抜くエアーベンド２０Ｄが設けられる。As shown in FIGS. 8 and 9, resin-sealed semiconductor device I
The molds for forming the resin sealing part 8 of 1 are a lower mold 20 and an upper mold 2.
Consists of 1. The lower mold 20 forms the shape of the resin sealing portion 8 below the lead frame 4 . In other words, the lower mold 20
has a cavity capable of accommodating all regions of the semiconductor pellet 2 and the heat dissipation plate), and has a region 20B forming a guide recess 8B and a region 20C forming a winding portion 8C. Further, the lower mold 20 is provided with an air bend 20D for venting air inside the cavity to the outside during resin sealing.
また、樹脂封止型半導体装置１がＬＯＧ構造を採用しリ
ードフレーム４下に樹脂封止部８の大半が存在するので
、又樹脂封止部８のリードフレーム４よりも下側が上側
に比べて複雑な形状で形成されるので、第９図に示すよ
うに、下型２０にはレジンゲート（樹脂注入口）１０が
構成される。前記第４図に示すように、レジンゲート１
０は、インナーリード４Ａ及びアウターリード４Ｂ、放
熱板７の夫々が配置されない領域を利用して構成される
。Furthermore, since the resin-sealed semiconductor device 1 adopts the LOG structure and most of the resin-sealed portion 8 exists below the lead frame 4, the lower side of the resin-sealed portion 8 than the lead frame 4 is larger than the upper side. Since it is formed in a complicated shape, a resin gate (resin injection port) 10 is formed in the lower mold 20, as shown in FIG. As shown in FIG. 4, the resin gate 1
0 is configured using the area where the inner lead 4A, the outer lead 4B, and the heat sink 7 are not arranged.
上型２１は、樹脂封止部８のリードフレーム４よりも上
側の形状を形成する。つまり、上型２１は、ガイド用凸
部８Ａを形成するキャビティを有し、このガイド用凸部
８Ａを形成する領域２１Ａを有する。また、上型２１に
は、樹脂封止時に放熱板７を挟持し、かつ樹脂封止部８
の突出する放熱板７側の側面の形状を規定するレジン、
止め部２１Ｂが設けられる。The upper mold 21 forms the shape of the resin sealing portion 8 above the lead frame 4 . That is, the upper die 21 has a cavity in which the guide convex portion 8A is formed, and has a region 21A in which the guide convex portion 8A is formed. Further, the upper mold 21 holds the heat sink 7 during resin sealing, and the resin sealing portion 8
resin that defines the shape of the side surface of the protruding heat sink 7 side;
A stop portion 21B is provided.
このように構成された樹脂封止型半導体装置１は、第１
０図（記憶装置の要部断面図）に示すように、メモリボ
ード（実装基板）１１上に複数個積層した状態で実装さ
れ、メモリモジュールを構成する。The resin-sealed semiconductor device 1 configured in this way has a first
As shown in FIG. 0 (a sectional view of a main part of a storage device), a plurality of them are mounted in a stacked state on a memory board (mounting board) 11 to constitute a memory module.
本実施例■は、この積層数に限定されないが、メモリボ
ード１１の実装面に対して垂直な方向（高さ方向）に４
個の樹脂封止型半導体装置１を積層する。積層されたう
ちの最下段に位置する樹脂封止型半導体装置（ＲＡＭＩ
）１はそのアウターリード４Ｂを直接メモリボード１１
の端子１１Ａに接触させ電気的に接続する（固着される
）。２段目の樹脂封止型半導体装！（ＲＡＭ２）１はそ
のガイド用凹部８Ｂを最下段の樹脂封止型半導体装置（
ＲＡＭＩ）１のガイド用凸部８Ａに勘合させて実装する
。この実装が行われると、最下段の樹脂封止型半導体装
置１．２段目の樹脂封止型半導体装置１の夫々の同一機
能のアウターリード４Ｂが接触し電気的に接続される一
０同様に、３段目の樹脂封止型半導体装１（ＲＡＭ３）
１．４段目の樹脂封止型半導体装置（ＲＡＭ４）１の夫
々も実装される。In this embodiment (2), although the number of layers is not limited to this, there are four
The resin-sealed semiconductor devices 1 are stacked. The resin-sealed semiconductor device (RAMI) is located at the bottom of the stack.
) 1 directly connects the outer lead 4B to the memory board 11
is brought into contact with the terminal 11A and electrically connected (fixed). 2nd stage resin-sealed semiconductor package! (RAM2) 1 connects its guide recess 8B to the lowermost resin-sealed semiconductor device (
It is mounted by fitting into the guide protrusion 8A of RAMI) 1. When this mounting is performed, the outer leads 4B of the resin-sealed semiconductor device 1 and the resin-sealed semiconductor device 1 on the lowermost stage and the resin-sealed semiconductor device 1 on the second stage come into contact and are electrically connected, respectively. , the third stage resin-sealed semiconductor device 1 (RAM3)
1. Each of the resin-sealed semiconductor devices (RAM4) 1 in the fourth stage is also mounted.
第１１図（システムブロック図）に示すように、積層さ
れた４個の樹脂封止型半導体装置１は、制御系信号のロ
ウアドレスストローブ信号ＲＡＳを除き、他の制御系信
号、データ系信号、アドレス系信号、電源の夫々を共通
信号として入力する。As shown in FIG. 11 (system block diagram), the four stacked resin-sealed semiconductor devices 1 have a control system signal other than a row address strobe signal RAS, other control system signals, data system signals, Each of address system signals and power supply is input as a common signal.
つまり、積層された４個の樹脂封止型半導体装置１の夫
々の同一配列位置のアウターリード４Ｂには同一の信号
が印加される。前記ロウアドレスストローブ信号ＲＡＳ
はチップ選択信号として積層された樹脂封止型半導体装
Ｆ４１の夫々に独立に入力される。つまり、最下段の樹
脂封止型半導体装置（ＲＡＭＩ）１にはロウアドレスス
トローブ信号ＲＡＳＩ、・・・・・・、最上段の樹脂封
止型半導体装置（ＲＡＭ４）１にはロウアドレスストロ
ーブ信号ＲＡＳ４が夫々入力される。本実施例Ｉの場合
、樹脂封止型半導体装置１を４個積層するので、樹脂封
止型半導体装［１にはロウアドレスストローブ信号ＲＡ
Ｓが印加できるアウターリード４Ｂは４本配列される。That is, the same signal is applied to the outer leads 4B at the same arrangement position of each of the four stacked resin-sealed semiconductor devices 1. The row address strobe signal RAS
is input independently to each of the stacked resin-sealed semiconductor devices F41 as a chip selection signal. That is, the lowermost resin-molded semiconductor device (RAMI) 1 receives the row address strobe signal RASI, and the uppermost resin-molded semiconductor device (RAM4) 1 receives the row address strobe signal RAS4. are input respectively. In the case of this embodiment I, since four resin-sealed semiconductor devices 1 are stacked, the resin-sealed semiconductor device [1 has a row address strobe signal RA].
Four outer leads 4B to which S can be applied are arranged.
積層された樹脂封止型半導体装置１の夫々の同一位置に
配列されたアウターリード４Ｂには同一のロウアドレス
ストローブ信号ＲＡＳが印加される。４つのうちの１つ
のロウアドレスストローブ信号ＲＡＳを樹脂封止型半導
体装置１に入力する場合、該当するアウターリード４Ｂ
と一体に構成されたインナーリード４Ａと外部端子ＢＰ
との間にボンディングワイヤ５をボンディングする。実
質的に入力しない３つのロウアドレスストローブ信号Ｒ
ＡＳが印加された夫々のインナーリード４Ａにおいては
ボンディングが行われない。例えば、ロウアドレススト
ローブ信号ＲＡＳ１は積層された４個の樹脂封止型半導
体装置１の夫々のアウターリード４Ｂにはすべて印加さ
れるが、最下段の樹脂封止型半導体装置１のロウアドレ
スストローブ信号ＲＡＳＩが印加されるインナーリード
４Ａと外部端子ＢＰとの間を接続し、他の樹脂封止型半
導体装置１はそれを行わないことにより、最下段の樹脂
封止型半導体装置１のみにロウアドレスストローブ信号
ＲＡＳが入力される。The same row address strobe signal RAS is applied to the outer leads 4B arranged at the same position in each of the stacked resin-sealed semiconductor devices 1. When inputting one of the four row address strobe signals RAS to the resin-sealed semiconductor device 1, the corresponding outer lead 4B
Inner lead 4A and external terminal BP integrated with
A bonding wire 5 is bonded between. Three row address strobe signals R that are not actually input
Bonding is not performed on each inner lead 4A to which AS is applied. For example, the row address strobe signal RAS1 is applied to all the outer leads 4B of the four resin-sealed semiconductor devices 1 stacked, but the row address strobe signal RAS1 of the resin-sealed semiconductor device 1 at the bottom layer is By connecting the inner lead 4A to which RASI is applied and the external terminal BP, and not connecting the other resin-sealed semiconductor devices 1, the row address is applied only to the bottom resin-sealed semiconductor device 1. A strobe signal RAS is input.
また、前述のメモリモジュールは、カラムアドレススト
ローブ信号ＣＡＳをチップ選択信号として使用し、他の
信号を共通信号としてもよい。また、メモリモジュール
は、積層された樹脂封止型半導体装［１の夫々に独立に
データ系信号（Ｄｉｎ及びＤｏｕｔ）を入力しくチップ
選択信号とし）、制御系信号、アドレス系信号、電源の
夫々を共通信号としてもよい。Furthermore, the above-described memory module may use the column address strobe signal CAS as a chip selection signal, and use other signals as common signals. In addition, the memory module includes stacked resin-sealed semiconductor devices [each of which receives data signals (Din and Dout) independently and serves as a chip selection signal], control system signals, address system signals, and power supply signals. may be used as a common signal.
このように、（１）インナーリード４Ａに外部端子ＢＰ
が電気的に接続された半導体ペレット２を樹脂封止部８
で封止する樹脂封止型半導体装置１において、前記半導
体ペレット２の素子形成面と対向する裏面に、この裏面
に比べて大きな平面々積を有する放熱板７を設け、この
放熱板７の周囲の一部の領域を除き、この放熱板７の前
記半導体ペレット２を搭載する表面側が前記半導体ペレ
ット２を被覆しかつガイド用凸部８Ａを有し、放熱板７
の前記表面と対向する裏面側が前記ガイド用凸部８Ａと
嵌合できる形状で形成されたガイド用凹部８Ｂを有する
樹脂封止部８を設ける。この樹脂封止型半導体装置１は
前記半導体ベレット２の素子形成面に対して垂直方向に
複数個積層される。この構成により、（Ａ）前記樹脂封
止型半導体装置１の樹脂封止部８のガイド用凸部８Ａ及
びガイド用凹部８Ｂをガイドとして、上下方向に複数個
の樹脂封止型半導体装［１を積層できる。複数個積層さ
れた樹脂封止型半導体装置ｌはメモリモジュール（電子
装置）において２次元的な（平面方向の）実装密度を高
められる。（Ｂ）また、前記樹脂封止型半導体装置１の
樹脂封止部８から放熱板７を突出させ、半導体ペレット
２から樹脂封止部８の外部に抜ける熱放出経路を確保し
たので。In this way, (1) the external terminal BP is connected to the inner lead 4A.
The semiconductor pellet 2 electrically connected to the resin sealing part 8
In the resin-sealed semiconductor device 1 , a heat sink 7 having a larger planar area than the back surface is provided on the back surface of the semiconductor pellet 2 facing the element forming surface, and the area around the heat sink 7 is The surface side of the heat dissipation plate 7 on which the semiconductor pellet 2 is mounted covers the semiconductor pellet 2 and has a guiding convex portion 8A, except for a part of the region of the heat dissipation plate 7.
A resin sealing part 8 is provided, the back side of which faces the front surface thereof, having a guide recess 8B formed in a shape that can fit into the guide convex part 8A. A plurality of resin-sealed semiconductor devices 1 are stacked in a direction perpendicular to the element formation surface of the semiconductor pellet 2. With this configuration, (A) a plurality of resin-sealed semiconductor devices [1 can be stacked. A plurality of stacked resin-sealed semiconductor devices 1 can increase the two-dimensional (planar direction) packaging density in a memory module (electronic device). (B) Furthermore, the heat dissipation plate 7 is made to protrude from the resin sealing part 8 of the resin sealing type semiconductor device 1, and a heat release path from the semiconductor pellet 2 to the outside of the resin sealing part 8 is secured.
半導体ペレット２の動作で発生する熱の放熱効率を向上
できる。この放熱板７は、樹脂封止型半導体装［１を上
下方向に複数個積層した場合でも、各段特に上段及び下
段に挟まれた中段に位置する樹脂封止型半導体装置１の
放熱経路を確保し、この中段に位置する樹脂封止型半導
体装置１の放熱効率を向上できる。（Ｃ）また、前記樹
脂封止型半導体装置１の半導体ペレット２の裏面側の大
半を樹脂封止部８に変えて放熱板フとし、樹脂封止部８
の厚さを薄くできる。この結果、複数個積層された樹脂
封止型半導体装置１はメモリモジュールにおいて３次元
的な（高さ方向の）実装密度を高めることができる。The efficiency of heat dissipation of heat generated by the operation of the semiconductor pellet 2 can be improved. Even when a plurality of resin-sealed semiconductor devices [1] are stacked in the vertical direction, this heat sink 7 provides a heat radiation path for the resin-sealed semiconductor devices 1 located in each stage, especially in the middle stage sandwiched between the upper and lower stages. The heat dissipation efficiency of the resin-sealed semiconductor device 1 located in the middle can be improved. (C) Also, most of the back side of the semiconductor pellet 2 of the resin-sealed semiconductor device 1 is changed to a resin-sealed portion 8 to serve as a heat sink, and the resin-sealed portion 8
The thickness can be reduced. As a result, a plurality of stacked resin-sealed semiconductor devices 1 can increase the three-dimensional (height direction) packaging density in the memory module.
また、（２）インナーリード４Ａに外部端子ＢＰが電気
的に接続された半導体ペレット２を樹脂封止部８で封止
する樹脂封止型半導体装置１において、前記半導体ペレ
ット２の素子形成面と対向する裏面に、この裏面に比べ
て大きな平面々積を有する放熱板７を設け、この放熱板
７の周囲の一部の領域を除き、この放熱板フの前記半導
体ペレット２を搭載する表面側が前記半導体ペレット２
及び放熱板７の周囲を被覆し、かつ放熱板７の前記表面
と対向する裏面側が放熱板７の周囲を被覆する樹脂封止
部８を設ける。この構成により、前記構成（１）の効果
（Ｂ）及び（Ｃ）の他に、前記樹脂封止型半導体装置１
の樹脂封止部８を放熱板７の表面側から裏面側に向って
この放熱板７の周囲に設けたので（放熱板７の周囲に樹
脂封止部８が食い込む構造としたので）、樹脂封止部８
と放熱板７との界面での剥離を低減できる。この剥離の
低減は、樹脂封止部８の外部から半導体ペレット２に達
する水分の伝達経路を遮断できるので。(2) In the resin-sealed semiconductor device 1 in which the semiconductor pellet 2 in which the external terminal BP is electrically connected to the inner lead 4A is sealed with the resin sealing portion 8, the element forming surface of the semiconductor pellet 2 and A heat sink 7 having a larger planar area than the back surface is provided on the opposing back surface, and except for a part of the area around the heat sink 7, the front surface side of the heat sink where the semiconductor pellet 2 is mounted is The semiconductor pellet 2
A resin sealing portion 8 is provided which covers the periphery of the heat sink 7 and whose back side facing the front surface of the heat sink 7 covers the periphery of the heat sink 7. With this configuration, in addition to the effects (B) and (C) of the configuration (1), the resin-sealed semiconductor device 1
Since the resin sealing part 8 was provided around the heat sink 7 from the front side to the back side of the heat sink 7 (the resin sealing part 8 was structured to bite into the periphery of the heat sink 7), the resin Sealing part 8
Peeling at the interface between the heat dissipating plate 7 and the heat dissipating plate 7 can be reduced. This reduction in peeling is achieved because the transmission path of moisture reaching the semiconductor pellet 2 from the outside of the resin sealing portion 8 can be blocked.
樹脂封止型半導体装！１の耐湿性を向上できる。Resin-sealed semiconductor package! 1. Moisture resistance can be improved.
また、（３）前記構成（２）の放熱板７には。Moreover, (3) the heat sink 7 of the said structure (2).
その周囲にこの放熱板７の表面側、裏面側の夫々の樹脂
封止部８を連結する貫通穴７Ａを設ける。A through hole 7A is provided around the heat dissipating plate 7 to connect the resin sealing portions 8 on the front side and the back side thereof.
この構成により、前記構成（２）の効果の他に、前記放
熱板７の貫通穴７Ａを通して、放熱板７の表面側、裏面
側の夫々の樹脂封止部８を連結し。With this configuration, in addition to the effect of configuration (2), the resin sealing portions 8 on the front and back sides of the heat sink 7 are connected through the through holes 7A of the heat sink 7.
樹脂封止部８と放熱板フとの接着強度をより高められる
ので、樹脂封止部８と放熱板７との界面での剥離をより
低減し、樹脂封止型半導体装置１の耐湿性をより向上で
きる。Since the adhesive strength between the resin sealing part 8 and the heat sink plate 7 can be further increased, peeling at the interface between the resin seal part 8 and the heat sink plate 7 can be further reduced, and the moisture resistance of the resin seal type semiconductor device 1 can be improved. You can improve even more.
また、（４）インナーリード４Ａに外部端子ＢＰが電気
的に接続された半導体ペレット２を樹脂封止部８で封止
する樹脂封止型半導体装置１において、前記半導体ペレ
ット２の素子形成面と対向する裏面に、この裏面に比べ
て大きな平面々積を有する放熱板フを設け、この放熱板
フの前記半導体ペレット２を搭載した表面側に前記半導
体ペレット２を被覆し、かつこの半導体ペレット２の素
子形成面上の厚さｔ２を前記放熱板７の厚さｔ３の１．
９〜６．０倍で形成した樹脂封止部８を設ける。この構
成により、前記構成（１）の効果（Ｂ）及び（Ｃ）の他
に、前記樹脂封止型半導体装置１の樹脂封止部８、放熱
板７の夫々の熱膨張係数差を許容範囲内に設定し、樹脂
封止部８の反りを低減できるので、メモリボード１１上
の端子１１Ａとすべてのアウターリード４Ｂとの接触が
確実に行え、樹脂封止型半導体装置１の実装不良を防止
できる。(4) In the resin-sealed semiconductor device 1 in which the semiconductor pellet 2 in which the external terminal BP is electrically connected to the inner lead 4A is sealed with the resin sealing portion 8, the element forming surface of the semiconductor pellet 2 and A heat sink plate having a larger planar area than the back surface is provided on the opposing back surface, and the semiconductor pellet 2 is coated on the front side of the heat sink plate on which the semiconductor pellet 2 is mounted, and the semiconductor pellet 2 is covered with the semiconductor pellet 2. The thickness t2 on the element forming surface is 1.1 of the thickness t3 of the heat sink 7.
A resin sealing portion 8 formed at a magnification of 9 to 6.0 times is provided. With this configuration, in addition to the effects (B) and (C) of the configuration (1), the difference in the coefficient of thermal expansion between the resin sealing portion 8 and the heat sink 7 of the resin sealing semiconductor device 1 can be reduced within an allowable range. Since the warpage of the resin sealing portion 8 can be reduced, contact between the terminals 11A on the memory board 11 and all the outer leads 4B can be ensured, and mounting failures of the resin sealing type semiconductor device 1 can be prevented. can.
また、（５）前記構成（４）の樹脂封止部８をエポキシ
系樹脂で形成し、前記放熱板７をＣｕ材料で形成する。Moreover, (5) the resin sealing part 8 of the said structure (4) is formed with an epoxy resin, and the said heat sink 7 is formed with Cu material.
この構成により、前記樹脂封止部８、放熱板７の夫々の
線膨張係数をほぼ均一化できるので、樹脂封止部８の反
り量δを低減し、樹脂封止型半導体装置１の実装不良を
低減できると共に、樹脂封止部８に比べて放熱板７のヤ
ング率が約１桁高いので、放熱板７の厚さを薄くし、樹
脂封止型半導体装ｗ１の高さ方向のサイズを縮小できる
。With this configuration, the linear expansion coefficients of the resin sealing part 8 and the heat sink 7 can be made almost uniform, so that the amount of warpage δ of the resin sealing part 8 can be reduced, and the mounting failure of the resin sealing type semiconductor device 1 can be reduced. In addition, since the Young's modulus of the heat sink 7 is approximately one order of magnitude higher than that of the resin-sealed portion 8, the thickness of the heat sink 7 can be reduced, and the size in the height direction of the resin-sealed semiconductor device w1 can be reduced. Can be reduced.
また、前記構成（５）の樹脂封止部８の半導体ペレット
２の素子形成面上の厚さｔ２は前記放熱板７の厚さｔ３
の３．０〜４．０倍で形成される。Further, the thickness t2 of the resin sealing portion 8 of the structure (5) on the element forming surface of the semiconductor pellet 2 is the thickness t3 of the heat sink plate 7.
It is formed at 3.0 to 4.0 times that of
この構成により、前記樹脂封止部８．放熱板７の夫々の
線膨張係数差をほとんどなくすことができる（反り量δ
をほぼ０にできる）ので、より樹脂封止型半導体装置１
の実装不良を低減できる。With this configuration, the resin sealing portion 8. It is possible to almost eliminate the difference in the coefficient of linear expansion of each of the heat sinks 7 (the amount of warpage δ
can be reduced to almost 0), so the resin-sealed semiconductor device 1
can reduce mounting defects.
また、（７）インナーリード４Ａに外部端子ＢＰが電気
的に接続された半導体ペレット４Ａを樹脂封止部８で封
止する樹脂封止型半導体装置１において、前記半導体ペ
レット２の表面側及びこの表面側と対向する裏面側を被
覆すると共に、前記表面側にガイド用凸部８Ａを有しか
つ前記裏面側に前記ガイド用凸部８Ａと嵌合できる形状
で形成されたガイド用凹部８Ｂを有する樹脂封止部８を
設け、この樹脂封止部８の表面側のガイド用凸部８Ａの
周囲に裏面側のガイド用凹部８Ｂの周囲まで引き回され
たアウターリード４Ｂを設け、このアウターリード４Ｂ
の前記表面側又は裏面側の一部分にリード幅を他部分に
比べて太く構成した接触部４ｂａを設ける。この構成に
より、前記構成（１）の効果（Ａ）の他に、前記樹脂封
止型半導体装Ｗ１のアウターリード４Ｂの一部分のリー
ド幅を太くシ、このアウターリード４Ｂに、上又は下方
向に積層された他の樹脂封止型半導体装置ｌの同一機能
を有するアウターリード４Ｂが接触できる面積を拡大し
たので５両者アウターリート４Ｂ間の電気的接続を確実
に行い、積層された樹脂封止型半導体装＠１間の電気的
接触不良を防止できる。(7) In a resin-sealed semiconductor device 1 in which a semiconductor pellet 4A having an external terminal BP electrically connected to an inner lead 4A is sealed with a resin sealing portion 8, the surface side of the semiconductor pellet 2 and the It covers the back side opposite to the front side, has a guide convex part 8A on the front side, and has a guide concave part 8B formed in a shape that can fit with the guide convex part 8A on the back side. A resin sealing portion 8 is provided, and an outer lead 4B is provided around the guide convex portion 8A on the front side of the resin sealing portion 8 to the circumference of the guide recess 8B on the back side.
A contact portion 4ba having a larger lead width than other portions is provided on a portion of the front side or the back side of the contact portion 4ba. With this configuration, in addition to the effect (A) of the configuration (1), the lead width of a portion of the outer lead 4B of the resin-sealed semiconductor device W1 is made thicker, and the outer lead 4B is provided with an upward or downward direction. Since the area in which the outer leads 4B having the same function of other stacked resin-sealed semiconductor devices 1 can come into contact has been expanded, the electrical connection between the two outer leads 4B can be ensured, and the stacked resin-sealed semiconductor devices Electrical contact failure between semiconductor devices @1 can be prevented.
また、（８）前記構成（７）のアウターリード４Ｂの前
記表面側又は裏面側には、積層される他の樹脂封止型半
導体装置１のアウターリード４Ｂと適度な押圧力で接触
できるばね性を有する末端部４ｂｂを設ける。この構成
により、前記樹脂封止型半導体装置１のアウターリード
４Ｂに設けたばね性で、上又は下方向に積層された他の
樹脂封止型半導体装置１の同一機能を有するアウターリ
ード４Ｂとの電気的な接触を確実に行うことができるの
で、積層された樹脂封止型半導体装置１間の電気的接触
不良を防止できる。(8) The front side or the back side of the outer lead 4B of the configuration (7) has a spring property that allows it to come into contact with the outer lead 4B of another resin-sealed semiconductor device 1 to be stacked with an appropriate pressing force. A distal end portion 4bb is provided. With this configuration, the elasticity provided on the outer lead 4B of the resin-sealed semiconductor device 1 allows electrical connection with the outer lead 4B having the same function of another resin-sealed semiconductor device 1 stacked upwardly or downwardly. Since contact can be ensured, poor electrical contact between the stacked resin-sealed semiconductor devices 1 can be prevented.
（実施例■）
本実施例■は、前記実施例Ｉの樹脂封止型半導体装置の
外部ピン数を増加した、本発明の第２実施例である。(Example 2) Example 2 is a second example of the present invention in which the number of external pins of the resin-sealed semiconductor device of Example I is increased.
本発明の実施例■である面実装方式を採用する樹脂封止
型半導体装置を第１２図（要部断面図）及び第１３図（
平面図）で示す。12 (cross-sectional view of main parts) and 13 (
(plan view).
本実施例■の樹脂封止型半導体装置１は、第１２図及び
第１３図に示すように、基本的には前記実施例Ｉと同様
であるが、樹脂封止部８の対向する長辺の夫々にアウタ
ーリード４Ｂを配列する。As shown in FIGS. 12 and 13, the resin-sealed semiconductor device 1 of this embodiment (2) is basically the same as that of the above-mentioned embodiment I, but the opposite long sides of the resin-sealed portion 8 are Outer leads 4B are arranged in each of the outer leads 4B.
放熱板７は、樹脂封止部８のアウターリード４Ｂが配列
されていない領域、つまり対向する短辺から夫々突出（
露出）させる。The heat dissipation plates 7 each protrude from the region where the outer leads 4B of the resin sealing part 8 are not arranged, that is, from the opposing short sides (
expose)
このように構成される樹脂封止型半導体装置１は、前記
実施例Ｉとほぼ同様の効果を奏することができると共に
、アウターリード４Ｂの本数を増加できる（多ピン化で
きる）特徴がある。The resin-sealed semiconductor device 1 configured in this manner can provide substantially the same effects as those of the above-mentioned embodiment I, and is also characterized by being able to increase the number of outer leads 4B (capable of increasing the number of pins).
（実施例■）
本実施例■は、前記実施例Ｉの樹脂封止型半導体装置に
おいて、半導体ペレットとリードとの間の寄生容量を低
減した、本発明の第３実施例である。(Example 2) Example 2 is a third example of the present invention in which the parasitic capacitance between the semiconductor pellet and the lead in the resin-sealed semiconductor device of Example I was reduced.
本発明の実施例■である面実装方式を採用する樹脂封止
型半導体装置を第１４図（要部断面図）で示す。A resin-sealed semiconductor device employing a surface mounting method, which is Embodiment 2 of the present invention, is shown in FIG. 14 (a cross-sectional view of the main part).
本実施例■の樹脂封止型半導体装置１は、第１４図に示
すように、半導体ペレット２、インナーリード４Ａの夫
々の間に金属板７０が設けられる。As shown in FIG. 14, in the resin-sealed semiconductor device 1 of Example 2, a metal plate 70 is provided between the semiconductor pellet 2 and the inner lead 4A.
金属板７０と半導体ペレット２．インナーリード４Ａの
夫々との間は絶縁層３，６（フィルム、シリコーンゴム
等で形成される）が設けられる。前記金属板７０は、図
示しないが、電源例えば基準電源電圧Ｖｓｓがインナー
リード４Ｂからボンディングワイヤ５を介在させて供給
される。Metal plate 70 and semiconductor pellets 2. Insulating layers 3 and 6 (made of film, silicone rubber, etc.) are provided between each inner lead 4A. Although not shown, the metal plate 70 is supplied with a power source, for example, a reference power source voltage Vss, from the inner lead 4B via the bonding wire 5.
このように構成される樹脂封止型半導体装置１は、前記
実施例■とほぼ同様の効果を奏することができる。また
、この効果の他に、前記金属板７０が電界を遮蔽できる
ので、半導体ペレット２、インナーリード４Ａの夫々に
形成される寄生容量を低減できる特徴がある。この結果
、インナーリード４Ａに伝達される信号の伝達速度が速
くなり、半導体ペレット２に搭載されたＤＲＡＭの動作
速度の高速化を図ることができる。The resin-sealed semiconductor device 1 constructed in this way can produce substantially the same effects as in the embodiment (2). In addition to this effect, since the metal plate 70 can shield the electric field, there is a feature that the parasitic capacitance formed in each of the semiconductor pellet 2 and the inner lead 4A can be reduced. As a result, the transmission speed of the signal transmitted to the inner lead 4A becomes faster, and the operating speed of the DRAM mounted on the semiconductor pellet 2 can be increased.
また、前記金属板７０は容量の一方の電極を構成し、絶
縁層は誘電体膜を構成し、半導体ペレット２又はインナ
ーリード４Ａは他の電極を構成するので、電源に前記金
属板７０を構成要件とする平滑コンデンサが挿入される
。つまり、樹脂封止型半導体装＠１は電源ノイズマージ
ンを向上できる特徴がある。Further, the metal plate 70 constitutes one electrode of the capacitor, the insulating layer constitutes a dielectric film, and the semiconductor pellet 2 or the inner lead 4A constitutes the other electrode, so the metal plate 70 constitutes the power source. The required smoothing capacitor is inserted. In other words, the resin-sealed semiconductor device @1 has the characteristic of improving the power supply noise margin.
（実施例■）
本実施例■は、ピン挿入方式を採用する樹脂封止型半導
体装置に本発明を適用した１本発明の第４実施例である
。(Embodiment 2) This embodiment 2 is a fourth embodiment of the present invention in which the present invention is applied to a resin-sealed semiconductor device that employs a pin insertion method.
本発明の実施例■であるピン挿入方式を採用する樹脂封
止型半導体装置を第１５図（要部断面図）で示す。A resin-sealed semiconductor device employing a pin insertion method, which is Embodiment 2 of the present invention, is shown in FIG. 15 (a sectional view of the main part).
本実施例■の樹脂封止型半導体装置１は、第１５図に示
すように、アウターリード４Ｂを直線的に延在させたピ
ン挿入方式で構成する。この樹脂封止型半導体装置１は
、同第１５図に示すように、メモリボード１１上に複数
個積層し実装される。As shown in FIG. 15, the resin-sealed semiconductor device 1 of this embodiment (2) is constructed using a pin insertion method in which the outer leads 4B are linearly extended. As shown in FIG. 15, a plurality of resin-sealed semiconductor devices 1 are stacked and mounted on a memory board 11.
また、前記樹脂封止型半導体装置１はアウタリード４Ｂ
を千鳥状に配列したＺＩＰ構造で構成してもよい。Further, the resin-sealed semiconductor device 1 has an outer lead 4B.
It may be configured in a ZIP structure in which the images are arranged in a staggered manner.
このように構成される樹脂封止型半導体装置１は前記実
施例■とほぼ同様の効果を奏することができる。The resin-sealed semiconductor device 1 constructed in this manner can produce substantially the same effects as in the embodiment (2).
以上、本発明者によってなされた発明を、前記実施例に
基づき具体的に説明したが、本発明は、前記実施例に限
定されるものではなく、その要旨を逸脱しない範囲にお
いて種々変更可能であることは勿論である。As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.
例えば、本発明は、前記樹脂封止型半導体装置の半導体
ペレットにＳ ＲＡ Ｍ （Ｓ ｔａｔｉｃ ＲＡ Ｍ
）。For example, the present invention provides S RAM (S tatic RAM) in the semiconductor pellet of the resin-sealed semiconductor device.
).
マスクＲＯＭ、ＥＰＲＯＭ、ＥＥＰＲＯＭ等、他のメモ
リを搭載してもよい。Other memories such as mask ROM, EPROM, EEPROM, etc. may also be installed.
また、本発明は、前記樹脂封止型半導体装置において、
放熱板７の半導体ペレット２下の裏面に他の領域に比べ
て薄く樹脂封止部８を設けてもよい。The present invention also provides the resin-sealed semiconductor device, comprising:
The resin sealing portion 8 may be provided on the back surface of the heat sink 7 under the semiconductor pellet 2, which is thinner than other areas.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
樹脂封止型半導体装置において、組立作業における歩留
りを向上することができる。In a resin-sealed semiconductor device, the yield in assembly work can be improved.
樹脂封止型半導体装置において、放熱効率を向上するこ
とができる。Heat dissipation efficiency can be improved in a resin-sealed semiconductor device.
樹脂封止型半導体装置において、耐湿性を向上すること
ができる。Moisture resistance can be improved in a resin-sealed semiconductor device.
樹脂封止型半導体装置を実装する電子装置において、実
装密度を向上することができる。In an electronic device in which a resin-sealed semiconductor device is mounted, the packaging density can be improved.
樹脂封止型半導体装置を実装する電子装置において、実
装不良を防止することができる。In an electronic device in which a resin-sealed semiconductor device is mounted, mounting defects can be prevented.
第１図は、本発明の実施例■である面実装方式を採用す
る樹脂封止型半導体装置の基本的構造を示す要部断面図
、
第２図は、前記樹脂封止型半導体装置の側面図、第３図
は、前記樹脂封止型半導体装置の平面図、第４図は、前
記樹脂封止型半導体装置の組立工程中でのリードフレー
ムの平面図、
第５図は、前記樹脂封止型半導体装置の放熱板の部品平
面図、
第６図は、前記樹脂封止型半導体装置の半導体ペレット
のレイアウト図、
第７図は、前記樹脂封止型半導体装置の放熱板の厚さと
樹脂封止部の反り量との関係を示す図、第８図及び第９
図は、前記樹脂封止型半導体装置の樹脂封止工程中にお
ける金型の断面図、第１０図は、前記樹脂封止型半導体
装置を実装した記憶装置の要部断面図、
第１１図は、前記記憶装置の′システムブロワ９図、
第１２図は、本発明の実施例■である面実装方式を採用
する樹脂封止型半導体装置の要部断面図。
第１３図は、前記樹脂封止型半導体装置の平面図、
第１４図は、本発明の実施例■である面実装方式を採用
する樹脂封止型半導体装置の要部断面図、第１５図は、
本発明の実施例■であるビン挿入方式を採用する樹脂封
止型半導体装置の要部断面図である。
図中、１・・・樹脂封止型半導体装置、２・・・半導体
ペレット、４Ａ・・・インナーリード、４Ｂ・・・アウ
ターリード、４ｂａ・・・接触部、４ｂｂ・・・末端部
、５・・ボンディングワイヤ、７・・放熱板、７Ａ・・
・貫通穴、８・・・樹脂封止部、８Ａ・・・ガイド用凸
部、８Ｂ・・ガイド用四部、８Ｃ・・・回り込み部、１
０・・・レジンゲート、１１・・・メモリボード、７０
・・・金属板、ＢＰ・・・外部端子である。FIG. 1 is a sectional view of the main parts showing the basic structure of a resin-sealed semiconductor device employing a surface-mounting method, which is Embodiment (2) of the present invention. FIG. 2 is a side view of the resin-sealed semiconductor device. 3 is a plan view of the resin-sealed semiconductor device, FIG. 4 is a plan view of the lead frame during the assembly process of the resin-sealed semiconductor device, and FIG. 5 is a plan view of the resin-sealed semiconductor device. 6 is a layout diagram of the semiconductor pellet of the resin-molded semiconductor device; FIG. 7 is a plan view of the heat sink of the resin-molded semiconductor device; and FIG. 7 shows the thickness and resin of the heat sink of the resin-molded semiconductor device. Figures 8 and 9 showing the relationship with the amount of warpage of the sealing part
10 is a cross-sectional view of a mold during the resin sealing process of the resin-sealed semiconductor device, FIG. 10 is a cross-sectional view of a main part of a storage device in which the resin-sealed semiconductor device is mounted, and FIG. FIG. 12 is a sectional view of a main part of a resin-sealed semiconductor device employing a surface-mounting method, which is Embodiment 2 of the present invention. FIG. 13 is a plan view of the resin-sealed semiconductor device, FIG. 14 is a cross-sectional view of a main part of a resin-sealed semiconductor device that employs a surface-mounting method, which is Embodiment (2) of the present invention, and FIG. 15 teeth,
1 is a sectional view of a main part of a resin-sealed semiconductor device employing a bottle insertion method, which is Embodiment 2 of the present invention; FIG. In the figure, 1...Resin-sealed semiconductor device, 2...Semiconductor pellet, 4A...Inner lead, 4B...Outer lead, 4ba...Contact part, 4bb...Terminal part, 5・・Bonding wire, 7・・Heat sink, 7A・・
・Through hole, 8...Resin sealing part, 8A...Convex part for guide, 8B...Four parts for guide, 8C...Wrap around part, 1
0...Resin gate, 11...Memory board, 70
... Metal plate, BP... External terminal.
Claims (1)
導体ペレットを樹脂封止部で封止する樹脂封止型半導体
装置において、前記半導体ペレットの素子形成面と対向
する裏面に、この裏面に比べて大きな平面々積を有する
放熱板を設け、この放熱板の周囲の一部の領域を除き、
この放熱板の前記半導体ペレットを搭載する表面側が前
記半導体ペレットを被覆しかつ凸部を有し、放熱板の前
記表面と対向する裏面側が前記凸部と嵌合できる形状で
形成された凹部を有する樹脂封止部を設けたことを特徴
とする樹脂封止型半導体装置。 ２、前記樹脂封止型半導体装置は前記半導体ペレットの
素子形成面に対して垂直方向に複数個積層されたことを
特徴とする請求項１に記載の電子装置。 ３、インナーリードに外部端子が電気的に接続された半
導体ペレットを樹脂封止部で封止する樹脂封止型半導体
装置において、前記半導体ペレットの素子形成面と対向
する裏面に、この裏面に比べて大きな平面々積を有する
放熱板を設け、この放熱板の周囲の一部の領域を除き、
この放熱板の前記半導体ペレットを搭載する表面側が前
記半導体ペレット及び放熱板の周囲を被覆し、かつ放熱
板の前記表面と対向する裏面側が放熱板の周囲を被覆す
る樹脂封止部を設けたことを特徴とする樹脂封止型半導
体装置。 ４、前記放熱板は、その周囲にこの放熱板の表面側、裏
面側の夫々の樹脂封止部を連結する貫通孔を設けたこと
を特徴とする請求項３に記載の樹脂封止型半導体装置。 ５、インナーリードに外部端子が電気的に接続された半
導体ペレットを樹脂封止部で封止する樹脂封止型半導体
装置において、前記半導体ペレットの素子形成面と対向
する裏面に、この裏面に比べて、大きな平面々積を有す
る放熱板を設け、この放熱板の前記半導体ペレットを搭
載した表面側に前記半導体ペレットを被覆し、かつこの
半導体ペレットの素子形成面上の厚さを前記放熱板の厚
さの１．９〜６．０倍で形成した樹脂封止部を設けたこ
とを特徴とする樹脂封止型半導体装置。 ６、前記樹脂封止部はエポキシ系樹脂で形成され、前記
放熱板はＣｕ系材料で形成されることを特徴とする請求
項５に記載の樹脂封止型半導体装置。 ７、前記樹脂封止部の半導体ペレットの素子形成面上の
厚さは放熱板の厚さの３．０〜４．０倍で形成されるこ
とを特徴とする請求項６に記載の樹脂封止型半導体装置
。 ８、インナーリードに外部端子が電気的に接続された半
導体ペレットを樹脂封止部で封止する樹脂封止型半導体
装置において、前記半導体ペレットの表面側及びこの表
面側と対向する裏面側を被覆すると共に、前記表面側に
凸部を有しかつ前記裏面側に前記凸部と嵌合できる形状
で形成された凹部を有する樹脂封止部を設け、この樹脂
封止部の表面側の凸部の周囲に裏面側の凹部の周囲まで
引き回されたアウターリードを設け、このアウターリー
ドの前記表面側又は裏面側の一部分のリード幅を他部分
に比べて太く構成したことを特徴とする樹脂封止型半導
体装置。 ９、前記アウターリードの前記表面側又は裏面側には、
積層される他の樹脂封止型半導体装置のアウターリード
と適度な押圧力で接触できるばね性を設けたことを特徴
とする請求項８に記載の樹脂封止型半導体装置。 １０、前記樹脂封止型半導体装置の半導体ペレットはＤ
ＲＡＭ、ＳＲＡＭ、ＥＰＲＯＭ、ＥＥＰＲＯＭ等の記憶
装置であることを特徴とする請求項１乃至請求項９に記
載の樹脂封止型半導体装置又は電子装置。[Scope of Claims] 1. In a resin-sealed semiconductor device in which a semiconductor pellet in which an external terminal is electrically connected to an inner lead is sealed in a resin sealing portion, a back surface of the semiconductor pellet that faces an element formation surface; A heat sink having a larger planar area than the back surface is provided, and except for a part of the area around this heat sink,
The front side of the heat sink on which the semiconductor pellet is mounted covers the semiconductor pellet and has a convex portion, and the back side of the heat sink opposite to the front side has a concave portion formed in a shape that can fit into the convex portion. A resin-sealed semiconductor device characterized by having a resin-sealed portion. 2. The electronic device according to claim 1, wherein a plurality of the resin-sealed semiconductor devices are stacked in a direction perpendicular to the element formation surface of the semiconductor pellet. 3. In a resin-sealed semiconductor device in which a semiconductor pellet, in which an external terminal is electrically connected to an inner lead, is sealed with a resin sealing part, the back surface of the semiconductor pellet that faces the element formation surface has a surface that is compared to this back surface. A heat sink with a large planar area is provided, except for a part of the area around the heat sink.
A resin sealing portion is provided, the front side of the heat sink on which the semiconductor pellet is mounted covers the semiconductor pellet and the heat sink, and the back side of the heat sink opposite to the front side covers the circumference of the heat sink. A resin-sealed semiconductor device characterized by: 4. The resin-sealed semiconductor according to claim 3, wherein the heat sink is provided with a through hole around the heat sink that connects the resin-sealed parts on the front side and the back side of the heat sink. Device. 5. In a resin-sealed semiconductor device in which a semiconductor pellet, in which an external terminal is electrically connected to an inner lead, is sealed in a resin sealing part, the back surface of the semiconductor pellet facing the element formation surface has a surface that is compared to this back surface. A heat sink having a large planar area is provided, the semiconductor pellet is coated on the surface side of the heat sink on which the semiconductor pellet is mounted, and the thickness of the semiconductor pellet on the element formation surface is set to A resin-sealed semiconductor device characterized by having a resin-sealed portion formed to have a thickness of 1.9 to 6.0 times. 6. The resin-sealed semiconductor device according to claim 5, wherein the resin-sealed portion is made of an epoxy resin, and the heat sink is made of a Cu-based material. 7. The resin sealing according to claim 6, wherein the thickness of the resin sealing portion on the element forming surface of the semiconductor pellet is 3.0 to 4.0 times the thickness of the heat sink. Stop type semiconductor device. 8. In a resin-sealed semiconductor device in which a semiconductor pellet in which an external terminal is electrically connected to an inner lead is sealed with a resin sealing part, the front side of the semiconductor pellet and the back side opposite to this front side are coated. At the same time, a resin sealing part having a convex part on the front side and a recess formed in a shape that can fit with the convex part on the back side is provided, and the convex part on the front side of the resin sealing part is provided. An outer lead is provided around the periphery of the recessed part on the back side, and a part of the outer lead on the front side or the back side is configured to have a lead width wider than other parts. Stop type semiconductor device. 9. On the front side or back side of the outer lead,
9. The resin-sealed semiconductor device according to claim 8, wherein the resin-sealed semiconductor device has a spring property that allows it to come into contact with an outer lead of another resin-sealed semiconductor device stacked thereon with an appropriate pressing force. 10. The semiconductor pellet of the resin-sealed semiconductor device is D
10. The resin-sealed semiconductor device or electronic device according to claim 1, wherein the resin-sealed semiconductor device or electronic device is a storage device such as a RAM, SRAM, EPROM, or EEPROM.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1334137A JP2799408B2 (en) | 1989-12-22 | 1989-12-22 | Semiconductor device and electronic device mounting the same |
| KR1019900003253A KR0145696B1 (en) | 1989-03-13 | 1990-03-12 | Semiconductor device and an electronic device with the semiconductor device mounted thereon |
| US07/915,761 US5266834A (en) | 1989-03-13 | 1992-07-21 | Semiconductor device and an electronic device with the semiconductor devices mounted thereon |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1334137A JP2799408B2 (en) | 1989-12-22 | 1989-12-22 | Semiconductor device and electronic device mounting the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03194954A true JPH03194954A (en) | 1991-08-26 |
| JP2799408B2 JP2799408B2 (en) | 1998-09-17 |
Family
ID=18273943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1334137A Expired - Fee Related JP2799408B2 (en) | 1989-03-13 | 1989-12-22 | Semiconductor device and electronic device mounting the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2799408B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2700416A1 (en) * | 1993-01-08 | 1994-07-13 | Mitsubishi Electric Corp | Semiconductor device having a semiconductor element on a mounting element. |
| EP0642164A3 (en) * | 1993-09-03 | 1995-07-12 | Ibm | Stackable vertical thin package/plastic molded lead-on-chip memory cube. |
| US5592019A (en) * | 1994-04-19 | 1997-01-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and module |
| US5801437A (en) * | 1993-03-29 | 1998-09-01 | Staktek Corporation | Three-dimensional warp-resistant integrated circuit module method and apparatus |
| KR100236016B1 (en) * | 1996-12-16 | 1999-12-15 | 구자홍 | Stacked type semiconductor package and assembly method thereof |
| US6188127B1 (en) | 1995-02-24 | 2001-02-13 | Nec Corporation | Semiconductor packing stack module and method of producing the same |
| US6319753B1 (en) | 1997-05-20 | 2001-11-20 | Nec Corporation | Semiconductor device having lead terminals bent in J-shape |
| JP2014160766A (en) * | 2013-02-20 | 2014-09-04 | Dainippon Printing Co Ltd | Multiple mounted component of lead frame with resin, and multiple mounted component of optical semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS632361A (en) * | 1986-06-23 | 1988-01-07 | Hitachi Ltd | Electronic device |
| JPS63281451A (en) * | 1987-05-13 | 1988-11-17 | Hitachi Ltd | Semiconductor device |
-
1989
- 1989-12-22 JP JP1334137A patent/JP2799408B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS632361A (en) * | 1986-06-23 | 1988-01-07 | Hitachi Ltd | Electronic device |
| JPS63281451A (en) * | 1987-05-13 | 1988-11-17 | Hitachi Ltd | Semiconductor device |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2700416A1 (en) * | 1993-01-08 | 1994-07-13 | Mitsubishi Electric Corp | Semiconductor device having a semiconductor element on a mounting element. |
| US5440169A (en) * | 1993-01-08 | 1995-08-08 | Mitsubishi Denki Kabushiki Kaisha | Resin-packaged semiconductor device with flow prevention dimples |
| US5801437A (en) * | 1993-03-29 | 1998-09-01 | Staktek Corporation | Three-dimensional warp-resistant integrated circuit module method and apparatus |
| US5895232A (en) * | 1993-03-29 | 1999-04-20 | Staktek Corporation | Three-dimensional warp-resistant integrated circuit module method and apparatus |
| EP0642164A3 (en) * | 1993-09-03 | 1995-07-12 | Ibm | Stackable vertical thin package/plastic molded lead-on-chip memory cube. |
| US5592019A (en) * | 1994-04-19 | 1997-01-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and module |
| US6188127B1 (en) | 1995-02-24 | 2001-02-13 | Nec Corporation | Semiconductor packing stack module and method of producing the same |
| KR100236016B1 (en) * | 1996-12-16 | 1999-12-15 | 구자홍 | Stacked type semiconductor package and assembly method thereof |
| US6319753B1 (en) | 1997-05-20 | 2001-11-20 | Nec Corporation | Semiconductor device having lead terminals bent in J-shape |
| KR100287236B1 (en) * | 1997-05-20 | 2001-11-22 | 가네꼬 히사시 | Semiconductor device with lead terminal bent in J-shape |
| JP2014160766A (en) * | 2013-02-20 | 2014-09-04 | Dainippon Printing Co Ltd | Multiple mounted component of lead frame with resin, and multiple mounted component of optical semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2799408B2 (en) | 1998-09-17 |
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