JPH03192690A - El display element - Google Patents

El display element

Info

Publication number
JPH03192690A
JPH03192690A JP1331579A JP33157989A JPH03192690A JP H03192690 A JPH03192690 A JP H03192690A JP 1331579 A JP1331579 A JP 1331579A JP 33157989 A JP33157989 A JP 33157989A JP H03192690 A JPH03192690 A JP H03192690A
Authority
JP
Japan
Prior art keywords
layer
display element
film
transparent
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1331579A
Other languages
Japanese (ja)
Other versions
JPH0760741B2 (en
Inventor
Tadashi Hattori
正 服部
Yoshihiro Hamakawa
圭弘 浜川
Nobue Ito
伊藤 信衛
Tamotsu Hattori
服部 有
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Soken Inc
Original Assignee
Nippon Soken Inc
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Soken Inc, NipponDenso Co Ltd filed Critical Nippon Soken Inc
Priority to JP1331579A priority Critical patent/JPH0760741B2/en
Publication of JPH03192690A publication Critical patent/JPH03192690A/en
Publication of JPH0760741B2 publication Critical patent/JPH0760741B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To improve reliability of an EL display element by forming a transparent In-capturing layer between an electrode composed of an ITO film which is one of a pair of electrodes and an insulating layer film located on the electrode side. CONSTITUTION:A first transparent electrode 1 made of an optically transparent ITO film is formed on a glass substrate 1. An optically transparent first In- capturing layer 21 made of TiSi2, an optically transparent first insulating layer film 31 made of Ta2O5, an electroluminescent layer 41 made of ZnS dopes with Mn, an optically transparent second insulating layer 32 made of Ta2O5, an optically transparent second In-capturing layer 22 made of TiSi2, and a second transparent electrode 12 made of an ITO film are successively stacked and formed is layers on its upper surface. In which exists in the electrodes 11, 12 formed of ITO film is captured in the transparent In-capturing layer 21, 22 during a process where of diffusion toward the insulating films 31, 32 and In is suppressed from diffusion in the insulating films 31, 32. In this way, high reliability is achieved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、例えば計器類のバンクライト用の面光源等に
使用されるBL(エレクトロミネッセンス)ディスプレ
イ素子に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a BL (electroluminescence) display element used, for example, as a surface light source for bank lights of instruments.

〔従来の技術〕[Conventional technology]

ELディスプレイ素子は、硫化亜鉛(ZnS)等の蛍光
体に電界をかけたときに発光する現象を利用したもので
、自発光型の平面ディスプレイを構成するものとして注
目されている。
EL display elements utilize the phenomenon of emitting light when an electric field is applied to a phosphor such as zinc sulfide (ZnS), and are attracting attention as a component of a self-luminous flat display.

このような従来のELディスプレイ素子の一例を第3図
に示す。
An example of such a conventional EL display element is shown in FIG.

図において、ガラス基板1上には、ITO膜よりなる透
明電極11.酸化タンタル(TazOs)等よりなる第
1絶縁層膜211発光層41.第2絶縁層膜22が順次
積層形成してあり、さらにその上にITO膜よりなる透
明電極12が配設しである。
In the figure, a transparent electrode 11 made of an ITO film is placed on a glass substrate 1. A first insulating layer film 211 made of tantalum oxide (TazOs) or the like; a light emitting layer 41; A second insulating layer 22 is sequentially laminated, and a transparent electrode 12 made of an ITO film is further disposed thereon.

I T O(Indium Tin 0xide)膜は
、酸化インジウム(InzOi)にすず(Sn)をドー
プした透明の導電膜で、低抵抗率であることから従来よ
り透明電極用として広く使用されている。
An ITO (Indium Tin Oxide) film is a transparent conductive film made of indium oxide (InzOi) doped with tin (Sn), and has been widely used for transparent electrodes because of its low resistivity.

発光層41としては、例えば、ZnSを母材層とし、発
光中心としてマンガン(Mn)や三フフ化テルビウム(
TbF3)を添加したものが使用される。EL全発光よ
る発光色はZnS中の添加物の種類によって決まり、例
えば発光中心としてMnを添加した場合にはオレンジ色
、TbF:+を添加した場合にはグリーンの発光が得ら
れる。
The light-emitting layer 41 may be made of, for example, ZnS as a base material layer and manganese (Mn) or terbium trifluoride (as a light-emitting center).
TbF3) is used. The color of light emitted by total EL emission is determined by the type of additive in ZnS; for example, when Mn is added as a luminescent center, orange light is obtained, and when TbF:+ is added, green light is obtained.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、上記構造のELディスプレイ素子を製作
し、連続発光試験に供したところ、200時間という比
較的短時間で絶縁破壊が生じ、発光効率ならびに耐久性
能面で大きな問題を有することが判明した。これは駆動
電圧が低い場合Gこしよそれほど重要ではないが、表示
面積の拡大等で駆動電圧を高くする必要が生じた場合に
は大きな問題となる。
However, when an EL display element with the above structure was manufactured and subjected to a continuous light emission test, dielectric breakdown occurred in a relatively short time of 200 hours, and it was found that there were major problems in light emission efficiency and durability. This is not so important when the drive voltage is low, but it becomes a big problem when it becomes necessary to increase the drive voltage to increase the display area or the like.

また、近年、異なる発光色を示す発光層を複数積層して
、ELディスプレイ素子をチューナプルカラー化するこ
とが提案されている(例えば、特開昭60−26409
6号公報、特開昭60−216496号公報等)。
In addition, in recent years, it has been proposed to make EL display elements tunable color by stacking a plurality of light emitting layers that emit light of different colors (for example, Japanese Patent Laid-Open No. 60-26409
6, JP-A-60-216496, etc.).

ところが、上記した絶縁層膜の耐圧低下現象は、このよ
うな積層型のELディスプレイ素子において特に顕著で
あることが判明し、実用化に際し大きな障害となってい
る。
However, it has been found that the above-mentioned phenomenon of reduction in breakdown voltage of the insulating layer film is particularly remarkable in such a laminated type EL display element, and has become a major obstacle to practical application.

本発明者らは、かかる点に鑑みて鋭意、研究したところ
、絶縁層膜の耐圧低下現象につき、次のごときメカニズ
ムを知見した。
In view of the above, the present inventors conducted extensive research and discovered the following mechanism regarding the phenomenon of a decrease in breakdown voltage of an insulating layer film.

即ち、ELディスプレイ素子の製造工程において、透明
電極を構成するITO膜が部分的に還元されてその膜中
に部分的にIn金属が存在し、この導電体であるInが
絶縁層膜中に拡散し、このため絶縁層膜の耐圧低下現象
が生じることを突き止めた。
That is, in the manufacturing process of EL display elements, the ITO film constituting the transparent electrode is partially reduced, and In metal is partially present in the film, and this conductive In is diffused into the insulating layer film. However, it was discovered that this caused a decrease in the withstand voltage of the insulating layer.

本発明は、かような知見に基づいて案出されたものであ
って、絶8i層膜の電気耐圧が高く、高電圧駆動時にお
いても絶縁破壊が生しることがなl、>ため、高信頼性
を有するELディスプレイ素子を稈供することを目的と
するものである。
The present invention was devised based on such knowledge, and the electrical breakdown voltage of the insulated 8i layer film is high, and dielectric breakdown does not occur even when driven at high voltage. The purpose is to provide an EL display element with high reliability.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、かかる目的を達成するため、少なくとも一方
をITO膜で構成した一対の電極の間に、絶縁膜層を介
して発光層を配したELディスプレイ素子において、一
対の電極のうちITO膜で構成された電極と該電極側に
位置する絶縁層膜との間に透明なIn捕捉層を配したと
いう技術的手段を採用したものである。
In order to achieve this object, the present invention provides an EL display element in which a light emitting layer is disposed between a pair of electrodes, at least one of which is made of an ITO film, with an insulating film layer interposed therebetween. A technical measure is adopted in which a transparent In trapping layer is disposed between the constructed electrode and the insulating layer film located on the electrode side.

また、上記透明なIn捕捉層は、Ti、V、Cr。Further, the transparent In trapping layer is made of Ti, V, or Cr.

Hf、Zn、Nb、Mo、Ta、’ W、Ptから選択
された高融点金属のシリサイド、または価電子制御され
た半導体、例えばn型半導体で構成することができる。
It can be composed of a silicide of a high-melting point metal selected from Hf, Zn, Nb, Mo, Ta, 'W, and Pt, or a semiconductor with controlled valence electrons, such as an n-type semiconductor.

〔作用〕[Effect]

本発明によれば、ITO膜で構成された電極中に存在す
るInが絶縁層膜へ向けて拡散する過程で透明なIn捕
捉層に捕捉され、従って絶縁層膜中への拡散が抑制され
ることになる。
According to the present invention, In in the electrode made of an ITO film is captured by the transparent In trapping layer in the process of diffusing toward the insulating layer, and therefore diffusion into the insulating layer is suppressed. It turns out.

〔発明の効果〕〔Effect of the invention〕

本発明においては、ELディスプレイ素子における絶縁
N膜の電気耐圧を向上でき、このため高電圧駆動時にお
いても絶縁破壊を生じることがなく、従って信軌性の高
いELディスプレイ素子を得ることができる。
In the present invention, the electrical withstand voltage of the insulating N film in the EL display element can be improved, so that dielectric breakdown does not occur even when driven at a high voltage, and therefore an EL display element with high reliability can be obtained.

[実施例] 第1図には本発明のE Lディスプレイ素子の一実施例
を示す。図において、ガラス基板1上には光学的に透明
なITO膜よりなる第1透明電極1よりなる光学的に透
明な第1絶縁層膜31.Mnが添加されたZnSよりな
る発光H41,Ta205よりなる光学的に透明な第2
絶縁層膜32.Ti5izよりなる光学的に透明な第2
In捕捉層22、ITO膜よりなる第2透明電極12が
順次積層形成しである。
[Example] FIG. 1 shows an example of the EL display element of the present invention. In the figure, an optically transparent first insulating layer film 31 made of a first transparent electrode 1 made of an optically transparent ITO film is disposed on a glass substrate 1. A light-emitting H41 made of Mn-doped ZnS, an optically transparent second made of Ta205
Insulating layer film 32. an optically transparent second layer made of Ti5iz;
An In trapping layer 22 and a second transparent electrode 12 made of an ITO film are sequentially laminated.

次に、上記構造のELディスプレイ素子の製造方法の一
例を説明する。
Next, an example of a method for manufacturing an EL display element having the above structure will be described.

まず、ガラス基板1上に、第1透明電極11を成膜した
。蒸着材料としては、酸化インジウム(Inz()+)
粉末にすず(Sn)を加えて混合し、ペレット状に成形
したものを用い、成膜装置としては、電子ビーム蒸着装
置を用いた。具体的には、基板1の温度を200°Cに
保持したまま蒸着装置内を5X10−3Paまで排気し
、蒸着レートが1.0〜3.0人/ s e cの範囲
となるようビーム電力を調整した。
First, the first transparent electrode 11 was formed on the glass substrate 1. As a vapor deposition material, indium oxide (Inz()+)
The powder was mixed with tin (Sn) and formed into pellets, and an electron beam evaporation device was used as the film forming device. Specifically, the inside of the evaporation apparatus was evacuated to 5X10-3 Pa while maintaining the temperature of the substrate 1 at 200°C, and the beam power was adjusted so that the evaporation rate was in the range of 1.0 to 3.0 persons/sec. adjusted.

第1透明電極11の上面には、チタンシリサイド(Ti
Si2)よりなる第11n捕捉J!f21をスパッタ装
置により形成した。具体的には、基板1の温度を150
°Cに保持してスパッタ装置内を5X10−’Paまで
排気後、装置内にArガスを導入して、1.4KWの高
周波電力のもと約5分間スパッタし、第1透明電極11
の上面に第11n捕捉層21をなすT i S i z
の膜を堆積した。堆積膜の組成はターゲットのTiとS
iの比を変化する“ことで制御した。このようにして得
られた第11n捕捉1i21の抵抗値はTiSi、膜の
固有抵抗値(10μΩ・CT11)から予想される値と
比較して1桁程度高い値を示すが、後述の熱処理にょっ
て抵抗値は減少する。
The upper surface of the first transparent electrode 11 is made of titanium silicide (Ti).
The 11nth acquisition J! f21 was formed using a sputtering device. Specifically, the temperature of the substrate 1 was set to 150°C.
After maintaining the temperature at °C and evacuating the inside of the sputtering apparatus to 5X10-'Pa, Ar gas was introduced into the apparatus, and sputtering was performed for about 5 minutes under a high frequency power of 1.4KW.
The 11nth trapping layer 21 is formed on the upper surface of T i S i z
film was deposited. The composition of the deposited film is the target Ti and S.
The resistance value of the 11n-th capture 1i21 obtained in this way is one order of magnitude higher than the value expected from the specific resistance value (10 μΩ・CT11) of the TiSi film. Although the resistance value is relatively high, the resistance value decreases by heat treatment, which will be described later.

次に、第11n捕捉層21の上面には、T a 、0゜
よりなる第1絶縁層膜31をスパッタにより形成する。
Next, on the upper surface of the 11n trapping layer 21, a first insulating layer film 31 having a T a of 0° is formed by sputtering.

具体的には基板1の温度を200°Cに保持し、スパッ
タ装置内を1. OP aに維持し、装置内にArとO
Zの混合ガスを導入(2000cc/min )し、I
KWの高周波電力で堆積速度2人/ s e cの条件
で行った。
Specifically, the temperature of the substrate 1 is maintained at 200°C, and the inside of the sputtering apparatus is heated to 1. Maintain at OP a, with Ar and O inside the device.
Introduce the mixed gas of Z (2000cc/min),
The deposition was performed using KW high frequency power at a deposition rate of 2 persons/sec.

この第1絶縁J’W31上には、ZnSを母材層とし、
発光中心としてMnを添加した発光層41をW着により
形成した。具体的には、基板1の温度を120 ’Cニ
保持し、装置内を5X10−’Pa以上に維持し、堆積
速度1.0〜3.0人/ s e cの条件で電子ビー
ム蒸着を行った。
On this first insulation J'W31, ZnS is used as a base material layer,
A light emitting layer 41 doped with Mn as a light emitting center was formed by W deposition. Specifically, the temperature of the substrate 1 was maintained at 120'C, the inside of the apparatus was maintained at 5X10-'Pa or more, and electron beam evaporation was performed at a deposition rate of 1.0 to 3.0 persons/sec. went.

次に、この発光層41の上にT a 20 sよりなる
第2絶縁層膜32.TiSi、よりなる第2In捕捉層
22を、各々第1絶縁層膜31.第11n捕捉層21と
同一の方法で形成する。
Next, on this light emitting layer 41, a second insulating layer film 32 made of T a 20 s is formed. A second In trapping layer 22 made of TiSi and a first insulating layer 31 . It is formed by the same method as the 11n-th trapping layer 21.

以上の各層11,21.31,41,32.22をガラ
ス基板1上に形成後、5X10−’Paの真空中、30
0〜550°Cで熱処理を行った。この熱処理により、
発光層41の結晶性を向上させ、発光輝度が上がる。
After forming each of the above layers 11, 21.31, 41, 32.22 on the glass substrate 1, 30
Heat treatment was performed at 0 to 550°C. With this heat treatment,
The crystallinity of the light-emitting layer 41 is improved, and the luminance of light emission is increased.

この熱処理後に、ITOIIiよりなる第2透明電極1
2を、先の第1透明電極11と同一の方法により、第2
In捕捉JW22の上に形成した。各々の膜厚は、第1
.第2透明電極11.12が3000人、第1.第21
n捕捉層21.22が3゜0人、第1.第2絶縁層膜3
1.32が6000人2発光層41が6000人である
After this heat treatment, the second transparent electrode 1 made of ITOIIi
2 to the second transparent electrode 11 using the same method as the first transparent electrode 11 described above.
It was formed on In-trapping JW22. Each film thickness is the first
.. The second transparent electrode 11.12 is 3000 people, the first transparent electrode 11.12 is 3000 people. 21st
n trapping layer 21.22 is 3°0 people, 1st. Second insulating layer film 3
1.32 is 6000 people and 2 light emitting layer 41 is 6000 people.

このようにして得たELディスプレイ素子を、連続発光
試験に供したところ(交流印加電圧180■)、500
時間経過後も絶縁破壊は認められず、絶縁破壊に対し良
好な性能を有することがわかった。
When the EL display element thus obtained was subjected to a continuous light emission test (AC applied voltage 180μ), 500μ
No dielectric breakdown was observed even after the passage of time, indicating that it had good performance against dielectric breakdown.

第2図は本発明の他の実施例を示す。本実施例で瞳、上
記第1実施例の構造上にさらに第2の発光層を積層した
積層型のELディスプレイ素子としである。
FIG. 2 shows another embodiment of the invention. In this example, the pupil is a layered EL display element in which a second light emitting layer is further laminated on the structure of the first example.

図において、中間電極となる第2透明電極12(ITO
膜)上にはTiSi2よりなる第31n捕捉層23およ
びT a z Osよりなる第3絶縁層膜33が先の実
施例と同一の方法でスバ・ツタにより形成してあり、そ
の上に第2発光層42が先の実施例と同一の方法で形成
しである。第2発光層42は、ZnSを母材層とし、発
光中心としてT b F xを添加したものでグリーン
発光する。
In the figure, a second transparent electrode 12 (ITO
A 31n-th trapping layer 23 made of TiSi2 and a third insulating layer 33 made of T az Os are formed on the same method as in the previous embodiment, and a second The light emitting layer 42 is formed by the same method as in the previous embodiment. The second light emitting layer 42 has ZnS as a base material layer and T b F x is added as a light emitting center, and emits green light.

第2発光層42上には、T a 20 sよりなる第4
絶縁層膜34を介してAN金属よりなる上部電極5が蒸
着により形成しである。第3.第4絶縁層膜33,34
.第2発光層42の膜厚はいずれも6000人であり、
In捕捉層23.24は500人、上部電極5は100
0人である。
On the second light emitting layer 42, there is a fourth layer made of T a 20 s.
An upper electrode 5 made of AN metal is formed by vapor deposition with an insulating layer 34 interposed therebetween. Third. Fourth insulating layer film 33, 34
.. The thickness of the second light emitting layer 42 is 6000 in each case,
500 people for the In trapping layers 23 and 24, 100 people for the upper electrode 5
There are 0 people.

上記構造のELディスプレイ素子において、第1の発光
層41.または第2発光層42に電圧を印加することに
より、それぞれオレンジ、グリーンの発光色が得られ、
さらに第1.第2発光層41.42を同時に発光させる
ことにより、これらの混色であるイエローの発光色が得
られるので、これらを組合わせることによりマルチカラ
ー化力く可能となる。
In the EL display element having the above structure, the first light emitting layer 41. Alternatively, by applying a voltage to the second light emitting layer 42, orange and green light emission colors can be obtained, respectively.
Furthermore, the first. By causing the second light emitting layers 41 and 42 to emit light at the same time, a yellow light emitting color, which is a mixture of these colors, can be obtained, so by combining these colors, it becomes possible to create a multicolor display.

上記の第2図の構造のELディスプレイ素子においても
絶縁破壊に対し良好な性能が得られ、第1実施例と同一
の連続発光試験に供したところ、500時間経過後も絶
縁破壊は認められなかった。
The EL display element with the structure shown in Figure 2 above also exhibited good performance against dielectric breakdown, and when subjected to the same continuous light emission test as in the first example, no dielectric breakdown was observed even after 500 hours had elapsed. Ta.

次に、比較のため、第3図、第4図に示す従来構造のE
Lディスプレイ素子を作製した。なお、図中、第1図、
第2図と同一符号は同一の構成を示す。これらは、それ
ぞれ上記第1実施例(第1図)および第2実施例(第2
図)からIn捕捉層21.22,23.24を省いた構
造となっている点が異なるのみで、他の構造は各実施例
と同一であり、製法も同一である。
Next, for comparison, the E of the conventional structure shown in Figs. 3 and 4 is shown.
An L display element was manufactured. In addition, in the figure, Figure 1,
The same reference numerals as in FIG. 2 indicate the same configurations. These are the above-mentioned first embodiment (Fig. 1) and second embodiment (second embodiment), respectively.
The only difference is that the In trapping layers 21, 22, 23, 24 are omitted from the structure shown in FIG.

これらを第1実施例と同一の連続発光試験に供したとこ
ろ、第3図の構造では200時間で絶縁破壊が生じ、第
4図の構造では40時間で絶縁破壊が生じた。
When these were subjected to the same continuous light emission test as in the first example, dielectric breakdown occurred in the structure shown in FIG. 3 after 200 hours, and dielectric breakdown occurred in the structure shown in FIG. 4 after 40 hours.

このITOによる絶縁破壊を調べるため、第5図のよう
に、ガラス基板1上にITO電極5を設け、その上にT
 a 、05絶縁層膜3をスパッタ法で成膜した試料を
作製してAES分析(オージェ電子分光分析)を行った
。試料は側端面を5°に斜め研磨し、深さ方向の元素の
分布がわかるようにした。結果を第6図に示す。
In order to investigate the dielectric breakdown caused by this ITO, as shown in FIG.
A, AES analysis (Auger electron spectroscopy) was performed on a sample in which the 05 insulating layer film 3 was formed by sputtering. The side end surfaces of the samples were polished at an angle of 5° so that the distribution of elements in the depth direction could be seen. The results are shown in Figure 6.

また、成膜後、350°Cで熱処理したもの、550”
Cで熱処理したものにつき、同様の分析を行ない、結果
をそれぞれ第7図、第8図に示した。
Also, after film formation, heat treated at 350°C, 550"
A similar analysis was carried out on those heat-treated with C, and the results are shown in FIGS. 7 and 8, respectively.

各図に明らかなように、熱処理によりTaとInのオー
バーラツプが大きくなっており、Inが絶8i層3を構
成するT a z Os中に浸入していく様子がよくわ
かる。また、熱処理温度を高くするごとでさらにその傾
向が増加している。
As is clear from each figure, the overlap between Ta and In increases due to the heat treatment, and it can be clearly seen that In penetrates into the T az Os constituting the 8i layer 3. Furthermore, this tendency increases as the heat treatment temperature increases.

Inは導電体であるため、絶縁層膜3中へInが拡散す
ると絶縁層膜の電気耐圧は低くなり、これが原因となっ
て絶縁破壊が生じると考えられる。
Since In is a conductor, when In diffuses into the insulating layer 3, the electric withstand voltage of the insulating layer decreases, and this is considered to be the cause of dielectric breakdown.

このInの絶縁層膜中への拡散は、ITO膜の上層の絶
縁i膜の成膜時に、例えばスバ・ツタのようにプラズマ
を利用する方法を用いるため、Inz03が還元されて
部分的にIn金属となって存在するからで、このIn金
属が熱処理の過程で拡散するためではないかと考えられ
ている。
This diffusion of In into the insulating layer film is caused by the reduction of Inz03 and partial In because a method using plasma is used, for example, as in Suba-Ivy, when forming the insulating i film on the ITO film. It is thought that this is because In metal exists as a metal, and this In metal diffuses during the heat treatment process.

これに対し、第1図の第1実施例のごとく、第1透明電
極11と第1絶8iN膜31との間、および第2透明電
極12と第2絶縁層膜32との間に、各々第1.第21
n捕捉層21.22(厚さ300人、Ti5iz)を形
成した試料を用いてAES分析を行った結果を第9図に
示す。第9図から明らかなように、550°C熱処理後
もInの絶縁層膜中への拡散は見られない。このように
、ITO膜よりなる透明電極−絶縁層膜間にIn捕捉層
を設けることにより、絶縁破壊を防止できる。
On the other hand, as in the first embodiment shown in FIG. 1st. 21st
FIG. 9 shows the results of an AES analysis performed using a sample in which an n-trapping layer 21.22 (thickness: 300 layers, Ti5iz) was formed. As is clear from FIG. 9, no diffusion of In into the insulating layer film was observed even after the heat treatment at 550°C. In this way, by providing the In trapping layer between the transparent electrode made of the ITO film and the insulating layer film, dielectric breakdown can be prevented.

ところで、上記の実施例は透明なIn捕捉層として、高
融点金属のシリサイド即ちTi5izにより構成したが
、微結晶炭化ケイ素等の価電子制御された半導体によっ
てIn捕捉層を構成することができる。炭化ケイ素より
なる薄膜は、例えばシラ゛ン(SiH4)とメタン(C
H,)との混合ガスを高周波放電などにより分解するこ
とで得られるが、混合ガス中にジボラン(B2H1)や
ホスフィン(PH3)を添加すればそれぞれP型。
By the way, in the above embodiment, the transparent In trapping layer is made of high melting point metal silicide, that is, Ti5iz, but the In trapping layer can be made of a semiconductor whose valence electrons are controlled, such as microcrystalline silicon carbide. A thin film made of silicon carbide is made of, for example, silane (SiH4) and methane (C
It can be obtained by decomposing a mixed gas with H, ) by high frequency discharge, etc., but if diborane (B2H1) or phosphine (PH3) is added to the mixed gas, each becomes P type.

n型の半導体膜が得られる。さらに,SixGeiH4
とCH,の混合比によって1.7ev 〜2.7ev程
度まで光学的禁制帯幅を制御することができる。ところ
で、本発明のELディスプレイ素子で用いている透明電
極(ITO)、発光層(ZnS)はn型半導体であるが
、各層の光学的禁制帯幅は異なるため、電荷がトンネリ
ングによって発光層中に導入されるためには大きな電圧
を印加する必要がある。
An n-type semiconductor film is obtained. Furthermore, SixGeiH4
The optical forbidden band width can be controlled to about 1.7ev to 2.7ev by adjusting the mixing ratio of CH and CH. By the way, the transparent electrode (ITO) and the light-emitting layer (ZnS) used in the EL display element of the present invention are n-type semiconductors, but since the optical forbidden band width of each layer is different, charges may be tunneled into the light-emitting layer. In order to be introduced, it is necessary to apply a large voltage.

そこで、前述した方法によって価電子制御した炭化ケイ
素半導体膜をIn捕捉層に用いることで、発光層への電
荷注入効率が大幅に改善される。
Therefore, by using a silicon carbide semiconductor film whose valence electrons are controlled by the method described above as an In trapping layer, the efficiency of charge injection into the light emitting layer is significantly improved.

即ち、光学的禁制帯幅を透明電極(ITO)と発光層(
ZnS)との中間に設定するため、例えば5i)(4と
CH4のガス流量比を1:2とし、2、7 e vとし
た。また、活性化エネルギも同様で、ITOとZnSの
中間に位置するようにSiC成膜時にPH,を5iHa
とCH,の総流量に対して流量比で1%添加した。この
方法により、光学的禁制帯幅2.7ev、活性化エネル
ギ0.4evのn型炭化ケイ素膜を得、緩衝層に応用し
た。その結果、しきい値電圧が約40V低下し8o■と
なり、輝度も2300cd/rrfから2700cd/
rdまで大幅に向上(緑色発光)し、従って電荷の注入
効率が改善されていることがわかる。なお、不純物を添
加しない半導体またはP型半導体は障壁となるので、電
荷の注入効率を改善する効果は期待できない。
In other words, the optical forbidden band width is determined by the distance between the transparent electrode (ITO) and the light emitting layer (
For example, 5i) (the gas flow ratio of 4 and CH4 was set to 1:2, and the activation energy was set to 2,7 e v. When forming the SiC film, the pH was adjusted to 5iHa so that the
and CH, were added at a flow rate ratio of 1% to the total flow rate. By this method, an n-type silicon carbide film with an optical forbidden band width of 2.7 ev and an activation energy of 0.4 ev was obtained and applied to a buffer layer. As a result, the threshold voltage decreased by about 40V to 8o■, and the brightness also increased from 2300cd/rrf to 2700cd/rrf.
It can be seen that the charge injection efficiency is significantly improved to rd (green light emission), and therefore the charge injection efficiency is improved. Note that since a semiconductor to which no impurity is added or a P-type semiconductor acts as a barrier, no effect of improving charge injection efficiency can be expected.

また、第1実施例と同一の連続発光試験を行ったところ
、500時間経過後も絶縁破壊は認められず、先の実施
例のTiS2よりなるIn捕捉層と同様、Inの絶縁層
膜への拡散を防止する効果が認められた。
In addition, when the same continuous light emission test as in the first example was conducted, no dielectric breakdown was observed even after 500 hours had passed, and similar to the In trapping layer made of TiS2 in the previous example, the In insulating layer film was The effect of preventing the spread was recognized.

本発明は上記の実施例に限らず、次のごとく、種々の変
形が可能である。
The present invention is not limited to the above-described embodiments, but can be modified in various ways as described below.

(1) I n捕捉層21,22.23はTi5izの
他に“VS  i2.Ta S  i2.Hf S  
iz、 Z r S  L。
(1) In addition to Ti5iz, the In trapping layers 21, 22, and 23 include “VS i2.Ta Si2.Hf S
iz, Z r S L.

NbS iz、CrS iz、MoS tz、P tS
 izのいわゆる高融点金属のシリサイドにより構成す
ることができる。また、In捕捉層21,22.23は
価電子制御された半導体により構成しているが、その半
導体は5i)(C+−xの他に,SixGei、5i)
(Ge+5ixSn+−xであってもよい。また、価電
子制御された半導体はInの捕捉という観点からすれば
n型の他にP型でもよい。
NbS iz, CrS iz, MoS tz, P tS
It can be composed of silicide of a so-called high melting point metal. In addition, the In trapping layers 21, 22, and 23 are made of a valence-controlled semiconductor, and the semiconductor is 5i) (in addition to C+-x, SixGei, 5i)
(Ge+5ixSn+-x may be used. Also, from the viewpoint of trapping In, the valence electron-controlled semiconductor may be of P type instead of n type.

(2)絶縁層膜31.32,33.34はT a 20
5で構成したが、Af、0.,SixGe i3N、、
PbT i O3て構成してもよい。
(2) Insulating layer films 31, 32, 33, 34 are T a 20
5, but Af, 0. ,SixGe i3N,,
It may also be composed of PbT i O3.

(3)発光層41はZnSにMnを添加したもので構成
したが、ZnSにSm、Tm等の希土類金属イオンを添
加したもので構成してもよい。
(3) Although the light emitting layer 41 is made of ZnS added with Mn, it may be made of ZnS added with rare earth metal ions such as Sm and Tm.

(4)発光層は1層、2層の他に3層以上とすることで
、例えばRGB等の発光層を重ねることでフルカラー化
が可能となる。
(4) By using three or more light-emitting layers in addition to one or two layers, it is possible to achieve full color, for example, by stacking RGB light-emitting layers.

(5)高融点金属のシリサイドにより構成されたIn捕
捉層と、価電子制御された半導体により構成されたIn
捕捉層を重層してもよい。この場合、絶縁層膜側に前者
のIn捕捉層を、透明電極側に後者のIn捕捉層を配す
るとよい。
(5) In trapping layer made of high melting point metal silicide and In made of semiconductor with controlled valence electrons
Acquisition layers may be overlaid. In this case, it is preferable to arrange the former In trapping layer on the insulating layer side and the latter In trapping layer on the transparent electrode side.

(6)価電子制御された半導体により構成されたIn捕
捉層は複層としてもよい。例えば、透明電極側に、光学
的禁制帯幅が大きく活性化エネルギーの小さい層を形成
し、絶縁層膜側に向けて段階的に光学的禁制帯幅を小さ
く活性化エネルギーを大きくした層を順次積層するよう
にしてもよい。この構成により、透明電極と絶縁層膜と
の間の物性値を連続的なものにでき、発光層への電荷の
注入効率が更に改善できる。
(6) The In trapping layer made of a semiconductor whose valence electrons are controlled may be a multilayer. For example, a layer with a large optical band gap and low activation energy is formed on the transparent electrode side, and layers with a small optical band gap and high activation energy are sequentially formed toward the insulating layer side. They may be laminated. With this configuration, the physical property values between the transparent electrode and the insulating layer can be made continuous, and the efficiency of charge injection into the light emitting layer can be further improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1実施例を示すELディスプレイ素
子の全体断面図、第2図は本発明の第2実施例を示すE
Lディスプレイ素子の全体断面図、第3図および第4図
は従来のBLディスプレイ素子の全体断面図、第5図は
従来のELディスプレイ素子におけるInの拡散状態を
調べるための試料の部分断面図、第6〜第8図は従来の
ELディスプレイ素子におけるInの拡散状態を示す図
、第9図は本発明のELディスプレイ素子におけるIn
の拡散状態を示す図である。 1・・・ガラス基板、11.12・・・第1.第2透明
電極、21,22.23・・・第1.第2.第31n捕
捉層、31,32,33.34・・・第1.第2゜第3
.第4絶縁層膜、41.42・・・第1.第2発光層。
FIG. 1 is an overall sectional view of an EL display element showing a first embodiment of the present invention, and FIG. 2 is an E display element showing a second embodiment of the present invention.
3 and 4 are overall sectional views of a conventional BL display element, and FIG. 5 is a partial sectional view of a sample for investigating the diffusion state of In in a conventional EL display element. 6 to 8 are diagrams showing the diffusion state of In in the conventional EL display element, and FIG. 9 is a diagram showing the diffusion state of In in the EL display element of the present invention.
It is a figure showing the diffusion state of. 1... Glass substrate, 11.12... 1st. 2nd transparent electrode, 21, 22, 23... 1st. Second. 31nth trapping layer, 31, 32, 33, 34... 1st. 2nd゜3rd
.. Fourth insulating layer film, 41.42...1st. Second light emitting layer.

Claims (6)

【特許請求の範囲】[Claims] (1)少なくとも一方をITO膜で構成した一対の電極
の間に、絶緑層膜を介して発光層を配したELデイスプ
レイ素子において、 前記一対の電極のうち前記ITO膜で構成された電極と
該電極側に位置する前記絶縁層膜との間に透明なIn捕
捉層を配したことを特徴とするELデイスプレイ素子。
(1) In an EL display element in which a light-emitting layer is arranged between a pair of electrodes, at least one of which is made of an ITO film, with a never-green layer interposed therebetween, the electrode of the pair of electrodes is made of an ITO film, An EL display element characterized in that a transparent In trapping layer is disposed between the insulating layer film located on the electrode side.
(2)前記透明なIn捕捉層は高融点金属のシリサイド
で構成されていることを特徴とする請求項(1)記載の
ELデイスプレイ素子。
(2) The EL display element according to claim 1, wherein the transparent In trapping layer is made of silicide of a high-melting point metal.
(3)前記高融点金属は、Ti,V,Cr,Hf,Zr
,Nb,Mo,Ta,W,Ptから選択されることを特
徴とする請求項(2)記載のELデイスプレイ素子。
(3) The high melting point metal is Ti, V, Cr, Hf, Zr
, Nb, Mo, Ta, W, and Pt.
(4)前記透明なIn捕捉層は、価電子制御された半導
体で構成されていることを特徴とする請求項(1)記載
のELデイスプレイ素子。
(4) The EL display element according to claim (1), wherein the transparent In trapping layer is made of a semiconductor whose valence electrons are controlled.
(5)前記半導体は、Si,Si_xC_t_−_x(
シリコンカーボン),Si_xGe_1_−_x(シリ
コンゲルマニウム),Si_xSn_1_−_x(シリ
コンすず)から選択されることを特徴とする請求項(4
)記載のELデイスプレイ素子。
(5) The semiconductor is Si, Si_xC_t_-_x(
Claim (4) characterized in that the silicone is selected from silicon carbon), Si_xGe_1_-_x (silicon germanium), and Si_xSn_1_-_x (silicon tin).
).The EL display element described in ).
(6)前記価電子制御された半導体はn型半導体である
ことを特徴とする請求項(4)記載のELデイスプレイ
素子。
(6) The EL display element according to claim 4, wherein the valence electron-controlled semiconductor is an n-type semiconductor.
JP1331579A 1989-12-21 1989-12-21 EL display element Expired - Lifetime JPH0760741B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1331579A JPH0760741B2 (en) 1989-12-21 1989-12-21 EL display element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1331579A JPH0760741B2 (en) 1989-12-21 1989-12-21 EL display element

Publications (2)

Publication Number Publication Date
JPH03192690A true JPH03192690A (en) 1991-08-22
JPH0760741B2 JPH0760741B2 (en) 1995-06-28

Family

ID=18245233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1331579A Expired - Lifetime JPH0760741B2 (en) 1989-12-21 1989-12-21 EL display element

Country Status (1)

Country Link
JP (1) JPH0760741B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5726953A (en) * 1995-04-07 1998-03-10 Metro-Mark, Incorporated Electroluminescent lamp with buried indiciae and method for making same
KR100354823B1 (en) * 1999-09-10 2002-10-04 전자부품연구원 Eld using a transparent isolate layer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6389698U (en) * 1986-12-01 1988-06-10

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6389698U (en) * 1986-12-01 1988-06-10

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5726953A (en) * 1995-04-07 1998-03-10 Metro-Mark, Incorporated Electroluminescent lamp with buried indiciae and method for making same
KR100354823B1 (en) * 1999-09-10 2002-10-04 전자부품연구원 Eld using a transparent isolate layer

Also Published As

Publication number Publication date
JPH0760741B2 (en) 1995-06-28

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