JPH0318368B2 - - Google Patents
Info
- Publication number
- JPH0318368B2 JPH0318368B2 JP52120894A JP12089477A JPH0318368B2 JP H0318368 B2 JPH0318368 B2 JP H0318368B2 JP 52120894 A JP52120894 A JP 52120894A JP 12089477 A JP12089477 A JP 12089477A JP H0318368 B2 JPH0318368 B2 JP H0318368B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- level
- signal
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000010354 integration Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03038—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Filters That Use Time-Delay Elements (AREA)
Description
【発明の詳細な説明】
本発明は自動等化器に関し、さらに詳しくはア
ルゴリズムとしてゼロフオーシング法を用いた自
動等化器に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic equalizer, and more particularly to an automatic equalizer using a zero-facing method as an algorithm.
アルゴリズムとしてゼロフオーシング法を用い
た自動等化器の識別器は入力信号の多値数をｍと
すると普通2m−１個の電圧レベル識別する必要
がある。これは信号レベルを識別するためにｍ−
１個を要するとともに波形の振幅が正規の振幅よ
り大か小かを識別するためにｍ個の識別レベルを
要するからであつて、従来のこの種の自動等化器
を第１図Ａに示す。第１図Ａは信号の多値数ｍを
４としタツプ数を前方２、後方２とした場合のゼ
ロフオーシング法を例にとつて示す。第１図Ｂは
入力信号の等化波形のアイパターンを示し、入力
信号は１タイムスロツト遅延素子１ａ，１ｂ，１
ｃ，１ｄに入力されそのおのおのの出力は可変利
得回路２ｂ，２ｃ，２ｄ，２ｅを介して加算器３
に供給される。加算器３の等化波形出力は７個の
電圧識別器４ａ，４ｂ，…，４ｇに入力されそれ
らの出力はアンド回路５ａ，５ｂ，５ｃオア回路
６を介して誤差極性信号になるとともに識別器４
ｄの出力は信号極性となり、これらの信号は１ビ
ツトシフトレジスタ７ａ，７ｂ，７ｃ，７ｄを介
して排他的論理和回路８ａ，８ｂ，８ｃ，８ｄ，
８ｅおよび積分回路９ａ，９ｂ，９ｃ，９ｄ，９
ｅを介して可変利得回路を制御する。 An automatic equalizer discriminator using the zero-facing method as an algorithm normally needs to discriminate 2m-1 voltage levels, where m is the number of multi-values of an input signal. This is used to identify the signal level.
A conventional automatic equalizer of this type is shown in FIG. 1A. . FIG. 1A shows an example of a zero-following method in which the multilevel number m of the signal is 4 and the number of taps is 2 in the front and 2 in the rear. FIG. 1B shows the eye pattern of the equalized waveform of the input signal.
c, 1d, and their respective outputs are sent to adder 3 via variable gain circuits 2b, 2c, 2d, 2e.
is supplied to The equalized waveform output of the adder 3 is input to seven voltage discriminators 4a, 4b, . 4
The output of d becomes the signal polarity, and these signals are sent to exclusive OR circuits 8a, 8b, 8c, 8d, via 1-bit shift registers 7a, 7b, 7c, 7d.
8e and integral circuits 9a, 9b, 9c, 9d, 9
Control the variable gain circuit via e.
識別器として並列型以外のＡ−Ｄ変換器を用い
る場合には信号レベルの識別用にもともとlog2m
ビツト必要であるがさらに１ビツト加えれば2m
−１個の電圧レベルの識別が行える。しかし信号
速度が数十Msymbol／ｓ以上になると動作速度
の点で各レベルに対応して電圧識別器を設ける並
列器Ａ−Ｄ変換器を用いなければならない。並列
型Ａ−Ｄ変換器を用いる場合には信号レベルの識
別用にもともとｍ−１個の電圧識別器が必要であ
るが自動等化を行なうとさらにｍ個の電圧識別器
が必要となり規模が大きくなる。 When using a non-parallel type A-D converter as a discriminator, the log 2 m
It requires 1 bit, but if you add 1 more bit, it will be 2m
- One voltage level can be identified. However, when the signal speed exceeds several tens of Msymbol/s, it is necessary to use a parallel A-D converter which is provided with a voltage discriminator corresponding to each level in terms of operating speed. When using a parallel A-D converter, m-1 voltage discriminators are originally required for signal level discrimination, but when automatic equalization is performed, an additional m voltage discriminators are required, increasing the scale. growing.
本発明の目的は並列型Ａ−Ｄ変換器を構成する
電圧識別器の数を少なくした自動等化器を提供す
ることにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic equalizer that reduces the number of voltage discriminators that constitute a parallel A-D converter.
本発明によればｍ値（４値）の入力信号を１タ
イムスロツト分遅延させる複数の遅延素子１ａ，
１ｂ，１ｃ，１ｄと、少なくとも前記遅延素子の
出力段に接続した可変利得回路２ｂ，２ｃ，２
ｄ，２ｅと、前記可変利得回路の出力を加算する
加算回路３と、前記加算回路の出力の信号極性を
示す信号を出力する第１の電圧識別器と、正規の
レベルからの誤差を出力する第２の電圧識別器
と、前記第１および第２の電圧識別器の出力の排
他的論理和を出力する排他的論理和回路８ａ，８
ｂ，８ｃ，８ｄ，８ｅと前記排他的論理和回路の
出力を積分して前記可変利得回路の利得を制御す
る積分回路９ａ，９ｂ，９ｃ，９ｄ，９ｅを備え
る自動等化器において、前記第１の電圧識別器
は、前記ｍ値の信号レベルの中央値（レベル２）
に対して前記加算器の出力レベルの信号極性を判
別する１つの電圧識別器１１ｃ或いは１５ｃから
なり、前記第２の電圧識別器は、前記ｍ値の信号
のうち１つの信号値レベル４或いはレベル５に対
する前記加算器の出力レベルの誤差極性を出力す
る１つの電圧識別器１１ａ或いは１５ａからな
り、さらに、前記加算器の出力レベルが誤差極性
を検出するために設定した１つの信号レベル領域
（レベル４領域或いはレベル５領域）に存在する
ことを示す有効信号を出力する第３の電圧識別器
１１ｂ或いは１５ｂを前記第１および前記第２の
電圧識別器と並列に設けるとともに、前記第３の
電圧識別器或いは前記第３の電圧識別器と前記第
２の電圧識別器の論理積により有効信号が出力さ
れている時のみ、前記可変利得回路の利得を制御
する積分回路に前記排他的論理和回路出力を入力
するゲート回路１３ａ，１３ｂ，１３ｃ，１３
ｄ，１３ｅを有することを特徴とする自動等化器
が提案される。 According to the present invention, a plurality of delay elements 1a that delay an m-value (four-value) input signal by one time slot,
1b, 1c, 1d, and variable gain circuits 2b, 2c, 2 connected at least to the output stage of the delay element.
d, 2e, an adder circuit 3 that adds the outputs of the variable gain circuit, a first voltage discriminator that outputs a signal indicating the signal polarity of the output of the adder circuit, and an error from the normal level. A second voltage discriminator and exclusive OR circuits 8a and 8 that output an exclusive OR of the outputs of the first and second voltage discriminators.
b, 8c, 8d, 8e and integrating circuits 9a, 9b, 9c, 9d, 9e that control the gain of the variable gain circuit by integrating the output of the exclusive OR circuit. The voltage discriminator 1 detects the median signal level (level 2) of the m values.
The second voltage discriminator includes one voltage discriminator 11c or 15c that discriminates the signal polarity of the output level of the adder, and the second voltage discriminator discriminates the signal value level 4 or level of one of the m-value signals. The output level of the adder includes one voltage discriminator 11a or 15a that outputs the error polarity of the output level of the adder with respect to the output level of the adder. A third voltage discriminator 11b or 15b is provided in parallel with the first and second voltage discriminators, and outputs a valid signal indicating that the third voltage The exclusive OR circuit is added to the integrating circuit that controls the gain of the variable gain circuit only when a valid signal is output by the logical product of the discriminator or the third voltage discriminator and the second voltage discriminator. Gate circuits 13a, 13b, 13c, 13 that input the output
An automatic equalizer is proposed, characterized in that it has d, 13e.
以下本発明にかゝる自動等化器の実施例につい
て図面により詳細に説明する。 Embodiments of the automatic equalizer according to the present invention will be described in detail below with reference to the drawings.
第２図Ａは本発明にかゝる自動等化器の第１の
実施例を示し第２図Ｂは入力信号の等化波形のア
イパターンを示す。第２図Ａにおいて第１図Ａと
同記号はそれと同等の部品を示すものとする。 FIG. 2A shows a first embodiment of an automatic equalizer according to the present invention, and FIG. 2B shows an eye pattern of an equalized waveform of an input signal. In FIG. 2A, the same symbols as in FIG. 1A indicate equivalent parts.
第２図ＡおよびＢについて本発明にかゝる自動
等化器を説明する。ゼロフオーシング法のタツプ
係数Cjの変更方法は次式のごとくである。 The automatic equalizer according to the present invention will be described with reference to FIGS. 2A and 2B. The method for changing the tap coefficient Cj in the zero-facing method is as shown in the following equation.
Cj(v+1)＝Cj(v)−△sgna^o-j・sgne^o
上式においてsgn ｘはｘの極性を表わしｘが
正のとき＋１でありｘが負のとき−１である。ま
た上式において
Cj：ｖ回変更後のタツプｊの係数
a^n−ｊ：出力推定値
e^n：出力振幅誤差推定値
△：１回の変更でのタツプ係数修正量
こゝで第３図ａはsgna^o-jを示し、電圧識別器
１１ｃの出力である。第３図ｂの波形は等化波形
の振幅が第２図Ｂの斜線の部分にある場合には
sgne^nを表わし、それ以外のときは正しい情報と
しては使えない。これは電圧識別器１１ａの出力
でありこの波形ｂが正しい情報であるかどうかは
第３図の波形ｃ、すなわち電圧識別器１１ｂの波
形によつてわかる。したがつて波形ａとｂとの排
他的論理和出力ｄが正しいときには波形ｃをクロ
ツクで打抜いた波形ｆでＤ−フクツプフロツプ１
３ａ〜１３ｅによつて読取り正しくないときには
排他的論理和出力は読みとらないで前の情報をそ
のまま用いる。即ち、本発明は、一部のレベル領
域部分のみを用いて、誤差信号を抽出し、その領
域にある時に係数の制御を行うようにしたので従
来の回路構成に比較し、電圧識別器を大幅に削減
できる。 Cj (v+1) = Cj (v) −Δsgna^ oj ·sgne^ oIn the above equation, sgn x represents the polarity of x, and is +1 when x is positive and -1 when x is negative. In addition, in the above equation, Cj: coefficient of tap j after v changes a^n−j: estimated output value e^n: estimated output amplitude error value △: amount of tap coefficient correction in one change Here, the third Figure a shows sgna^ oj , which is the output of the voltage discriminator 11c. If the amplitude of the equalized waveform is in the shaded area of Figure 2B, the waveform in Figure 3b is
It represents sgne^n and cannot be used as correct information in any other case. This is the output of the voltage discriminator 11a, and whether or not this waveform b is correct information can be determined from the waveform c in FIG. 3, that is, the waveform of the voltage discriminator 11b. Therefore, when the exclusive OR output d of waveforms a and b is correct, the waveform f obtained by punching out the waveform c with a clock is used as the D-flip flop 1.
If the reading by 3a to 13e is incorrect, the exclusive OR output is not read and the previous information is used as is. That is, in the present invention, the error signal is extracted using only a part of the level region, and the coefficients are controlled when it is in that region, so the voltage discriminator can be significantly simplified compared to the conventional circuit configuration. can be reduced to
例えば４値の信号を扱う場合に、その中の１つ
の値のみに着目することで、回路的には電圧識別
器を３個にできる。 For example, when dealing with a four-value signal, by focusing on only one of the values, the number of voltage discriminators can be reduced to three in terms of the circuit.
尚、処理的には平均４回に１度の係数調整を図
ることになり、従来の各受信信号毎に処理を行う
ものと異なるが、可変利得回路の係数の調整は最
終的には収束するものであり逐次調整するか４回
に１度調整するかは問題とならない。 In addition, in terms of processing, the coefficients are adjusted once every four times on average, which is different from the conventional process in which processing is performed for each received signal, but the adjustment of the coefficients of the variable gain circuit will eventually converge. It does not matter whether it is adjusted sequentially or once every four times.
第４図Ａは本発明にかゝる自動等化器の第２の
実施例であつて誤差極性を使う領域が第２図Ａの
場合と異なる例であり第４図Ｂは識別レベルを示
す。第４図Ａにおける実施例においては識別レベ
ル“２”による信号極性と識別レベル“４”によ
る誤差極性を用い、誤差極性は常に「＋」極性で
あるから、中央タツプCoの制御は図示のように
通常のAGC制御回路１５などを用いる。 FIG. 4A shows a second embodiment of the automatic equalizer according to the present invention, in which the area in which error polarity is used is different from that in FIG. 2A, and FIG. 4B shows the discrimination level. . In the embodiment shown in FIG. 4A, the signal polarity according to the discrimination level "2" and the error polarity according to the discrimination level "4" are used, and since the error polarity is always the "+" polarity, the central tap Co is controlled as shown in the figure. A normal AGC control circuit 15 or the like is used for this purpose.
第４図Ａは本発明にかゝる自動等化器の第２の
実施例であり、第４図Ｂはその識別レベルを示
す。第２の実施例においては識別レベル１および
２ならびに誤差極性用レベル５を用いた場合を示
すものであつて、回路の動作は第２図Ａの場合と
同様であつて、排他的論理和回路の出力が正しい
ときにのみＤ−フリツプフロツプで情報を読みと
り正しくないときは前の情報をそのまま用いてい
る。 FIG. 4A shows a second embodiment of the automatic equalizer according to the present invention, and FIG. 4B shows its discrimination level. The second embodiment shows a case where discrimination levels 1 and 2 and error polarity level 5 are used, and the operation of the circuit is the same as in the case of FIG. 2A. The D-flip-flop reads the information only when the output is correct, and when it is incorrect, the previous information is used as is.
以上の説明に用いた図においては信号の多値数
ｍを４とし、トランスバーサルフイルタのタツプ
数を５とした場合について説明したがそれ以外の
ときもこの方法を適用することができることは勿
論である。また以上の説明においてはゼロフオー
シング法の場合について説明したが、ゼロフオー
シング法以外の制御アルゴリズムを用いるときで
もこの方法を適用でき、さらに排他的論理和回路
の出力が正しくないときに前の情報を積分器入力
として用いず積分器の出力を保持することにより
同様の効果がもたらされることは勿論である。 In the diagrams used in the above explanation, the case where the multilevel number m of the signal is 4 and the number of taps of the transversal filter is 5 has been explained, but it goes without saying that this method can be applied to other cases as well. be. Although the above explanation deals with the case of the zero-focusing method, this method can also be applied when using control algorithms other than the zero-focusing method, and furthermore, when the output of the exclusive OR circuit is incorrect, the previous Of course, a similar effect can be achieved by holding the output of the integrator without using the information as the integrator input.
第１図Ａ，Ｂは従来の自動等化器の１例、第２
図Ａ，Ｂは本発明にかゝる自動等化器の第１の実
施例第３図は第２図Ａの回路の動作を説明するた
めの各部波形図、第４図Ａ，Ｂは本発明にかゝる
第２の実施例である。
図において、１１ａ，１１ｂ，１１ｃ，１１
ｄ，１４ａ，１４ｂ，１４ｃ，１４ｄおよび１５
ａ，１５ｂ，１５ｃ，１５ｄがそれぞれ電圧識別
器である。
Figures 1A and 1B are examples of conventional automatic equalizers;
Figures A and B show the first embodiment of the automatic equalizer according to the present invention. Figure 3 is a waveform diagram of each part for explaining the operation of the circuit in Figure 2A, and Figures 4A and B are the main parts. This is a second embodiment of the invention. In the figure, 11a, 11b, 11c, 11
d, 14a, 14b, 14c, 14d and 15
a, 15b, 15c, and 15d are voltage discriminators, respectively.
Claims (1)
分遅延させる複数の遅延素子１ａ，１ｂ，１ｃ，
１ｄと、少なくとも前記遅延素子の出力段に接続
した可変利得回路２ｂ，２ｃ，２ｄ，２ｅと、前
記可変利得回路の出力を加算する加算回路３と、
前記加算回路の出力の信号極性を示す信号を出力
する第１の電圧識別器と、正規のレベルからの誤
差を出力する第２の電圧識別器と、前記第１およ
び第２の電圧識別器の出力の排他的論理和を出力
する排他的論理和回路８ａ，８ｂ，８ｃ，８ｄ，
８ｅと前記排他的論理和回路の出力を積分して前
記可変利得回路の利得を制御する積分回路９ａ，
９ｂ，９ｃ，９ｄ，９ｅを備える自動等化器にお
いて、 前記第１の電圧識別器は、前記ｍ値の信号レベ
ルの中央値（レベル２）に対して前記加算器の出
力レベルの信号極性を判別する１つの電圧識別器
１１ｃ或いは１５ｃからなり、 前記第２の電圧識別器は、前記ｍ値の信号のう
ち１つの信号値レベル４或いはレベル５に対する
前記加算器の出力レベルの誤差極性を出力する１
つの電圧識別器１１ａ或いは１５ａからなり、 さらに、前記加算器の出力レベルが誤差極性を
検出するために設定した１つの信号レベル領域レ
ベル４領域或いはレベル５領域に存在することを
示す有効信号を出力する第３の電圧識別器１１ｂ
或いは１５ｂを前記第１および前記第２の電圧識
別器と並列に設けるとともに、 前記第３の電圧識別器或いは前記第３の電圧識
別器と前記第２の電圧識別器の論理積により有効
信号が出力されている時のみ、前記可変利得回路
の利得を制御する積分回路に前記排他的論理和回
路出力を入力するゲート回路１３ａ，１３ｂ，１
３ｃ，１３ｄ，１３ｅを有することを特徴とする
自動等化器。 ２ 前記ゲート回路として、フリツプフロツプ回
路を用い、該有効信号が入力した時のみ、該排他
的論理和回路出力をセツトする様にしたことを特
徴とする特許請求の範囲第１項記載の自動等化
器。[Claims] A plurality of delay elements 1a, 1b, 1c, which delay an input signal of 1 m value (4 values) by 1 time slot.
1d, variable gain circuits 2b, 2c, 2d, and 2e connected to at least the output stage of the delay element, and an adder circuit 3 that adds the outputs of the variable gain circuits;
a first voltage discriminator that outputs a signal indicating the signal polarity of the output of the adding circuit; a second voltage discriminator that outputs an error from a normal level; and the first and second voltage discriminators. exclusive OR circuits 8a, 8b, 8c, 8d, which output exclusive OR of outputs;
8e and an integration circuit 9a that integrates the output of the exclusive OR circuit to control the gain of the variable gain circuit;
In the automatic equalizer including 9b, 9c, 9d, and 9e, the first voltage discriminator determines the signal polarity of the output level of the adder with respect to the median value (level 2) of the signal levels of the m values. The second voltage discriminator outputs the error polarity of the output level of the adder with respect to one signal value level 4 or level 5 among the m-value signals. Do 1
It further outputs a valid signal indicating that the output level of the adder exists in one signal level region level 4 region or level 5 region set for detecting error polarity. The third voltage discriminator 11b
Alternatively, 15b is provided in parallel with the first and second voltage discriminators, and the valid signal is determined by the AND of the third voltage discriminator or the third voltage discriminator and the second voltage discriminator. gate circuits 13a, 13b, 1 that input the output of the exclusive OR circuit to an integrating circuit that controls the gain of the variable gain circuit only when the output is being output;
3c, 13d, and 13e. 2. The automatic equalization according to claim 1, wherein a flip-flop circuit is used as the gate circuit, and the output of the exclusive OR circuit is set only when the valid signal is input. vessel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12089477A JPS5454559A (en) | 1977-10-11 | 1977-10-11 | Automatic equalizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12089477A JPS5454559A (en) | 1977-10-11 | 1977-10-11 | Automatic equalizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5454559A JPS5454559A (en) | 1979-04-28 |
| JPH0318368B2 true JPH0318368B2 (en) | 1991-03-12 |
Family
ID=14797613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12089477A Granted JPS5454559A (en) | 1977-10-11 | 1977-10-11 | Automatic equalizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5454559A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1212993B (en) * | 1983-08-11 | 1989-12-07 | Sip | ADAPTIVE EQUALIZER FOR NUMERICAL SIGNALS SUBJECT TO VARIABLE DISTORTIONS OVER TIME |
| AR241298A1 (en) * | 1985-10-03 | 1992-04-30 | Siemens Ag | Adaptive transversal equalizer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4924338A (en) * | 1972-06-27 | 1974-03-04 |
-
1977
- 1977-10-11 JP JP12089477A patent/JPS5454559A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4924338A (en) * | 1972-06-27 | 1974-03-04 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5454559A (en) | 1979-04-28 |
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