JPH03181280A - Digital picture memory device - Google Patents
Digital picture memory deviceInfo
- Publication number
- JPH03181280A JPH03181280A JP1319920A JP31992089A JPH03181280A JP H03181280 A JPH03181280 A JP H03181280A JP 1319920 A JP1319920 A JP 1319920A JP 31992089 A JP31992089 A JP 31992089A JP H03181280 A JPH03181280 A JP H03181280A
- Authority
- JP
- Japan
- Prior art keywords
- parallel
- serial
- points
- converter
- pixel data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 6
- 230000004044 response Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Image Input (AREA)
- Studio Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はディジタル画像メモリ装置に関し、特にテレビ
ジョンの特殊効実用のディジタル画像メモリ装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital image memory device, and more particularly to a digital image memory device for practical use in special effects for television.
かかるディジタル画像メモリ装置は、画素の座標点の間
を補間して新しく画素データをつくるために、任意の座
標(X、Y)ならびにその近傍の座標(X+1.Y)、
(X、Y+1)、(X+1 。Such a digital image memory device uses arbitrary coordinates (X, Y) and neighboring coordinates (X+1.Y), in order to create new pixel data by interpolating between pixel coordinate points.
(X, Y+1), (X+1.
Y+1〉の4点の座標の画素データを同時に読出す必要
がある。It is necessary to read out the pixel data at the coordinates of four points Y+1> at the same time.
そのため、従来は、メモリ部を4個のメモリチップで構
成し、これらメモリチップに同じディジタル画像の画素
データを並列に書込み、それぞれのメモリチップから各
1座標点、計4座標点の画素データを同時に読出すよう
に構成されていた。Therefore, in the past, the memory section was configured with four memory chips, pixel data of the same digital image was written in parallel to these memory chips, and pixel data of one coordinate point each, for a total of four coordinate points, was written from each memory chip. They were configured to be read out simultaneously.
上述した従来のディジタル画像メモリ装置は、NTSC
信号の動作速度には対応できるが、メモリチップの応答
速度の制約から、高品位テレビジョン信号のように速い
動作速度には対応できない欠点がある。The conventional digital image memory device mentioned above is NTSC
Although it can handle signal operating speeds, it has the disadvantage that it cannot support high-speed operating speeds such as high-definition television signals due to constraints on the response speed of memory chips.
本発明の目的は、メモリチップの応答速度を上げること
なく高速で動作できるディジタル画像メモリ装置を提供
することにある。An object of the present invention is to provide a digital image memory device that can operate at high speed without increasing the response speed of the memory chip.
本発明のディジタル画像メモリ装置は、ディジタル画像
の順次入力する画素データをN組(Nは2以上の整数)
に直列並列変換する直列−並列変換器と、この直列−並
列変換器が出力した前記N組の前記画素データをそれぞ
れ書込み前記ディジタル画像の横軸及び縦軸をX及びY
として任意の座標(X、Y)ならびにこの座標(X、Y
)の近傍の座標(X+1.Y)、(X、Y+1)及び(
X+1.Y+1)の4点の前記画素データをそれぞれ読
出し可能なN個の記憶手段と、これら記憶手段が出力し
た4N点の前記画素データからなるパラレルデータを前
記4点の前記画素データからなるパラレルデータに並列
直列変換する並列−直列変換器とを備えている。The digital image memory device of the present invention stores N sets of sequentially input pixel data of a digital image (N is an integer of 2 or more).
A serial-to-parallel converter that performs serial-to-parallel conversion, and writes the N sets of pixel data output from the serial-to-parallel converter, respectively, and converts the horizontal and vertical axes of the digital image into X and Y.
as arbitrary coordinates (X, Y) and this coordinate (X, Y
) neighborhood coordinates (X+1.Y), (X, Y+1) and (
X+1. N storage means each capable of reading out the pixel data of the four points (Y+1), and parallel data consisting of the pixel data of the 4N points outputted by these storage means into parallel data consisting of the pixel data of the four points. and a parallel-to-serial converter that performs parallel-to-serial conversion.
本発明のディジタル画像メモリ装置が備える前記記憶手
段のそれぞれに4N個のメモリチップを含んでいてもよ
い。Each of the storage means included in the digital image memory device of the present invention may include 4N memory chips.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
第1図において、20は直列−並列変換器であり、入力
端子10から1座標点ずつ順次入力したディジタル画像
の画素データをN組(Nは2以上の整数)に直列並列変
換する。直列−並列変換器20はシフトレジスタによっ
て構成できる。In FIG. 1, reference numeral 20 denotes a serial-parallel converter, which converts pixel data of a digital image sequentially input one coordinate point at a time from the input terminal 10 into N sets (N is an integer of 2 or more) into serial-parallel converters. The serial-parallel converter 20 can be configured by a shift register.
31〜3Nはメモリ部であり、それぞれ4N個のメモリ
チップを含んでいる。直列−並列変換器20からメモリ
部31〜3NのそれぞれにN座標点の画素データが同時
に入力する。これらN座標点の画素データはメモリ部3
1〜3Nのそれぞれのメモリチップに書込まれる。この
とき、1つの画素データを4つのメモリチップに並列に
書込む。31 to 3N are memory sections, each of which includes 4N memory chips. Pixel data of N coordinate points are simultaneously input from the serial-parallel converter 20 to each of the memory units 31 to 3N. The pixel data of these N coordinate points are stored in the memory section 3.
1 to 3N are written to each memory chip. At this time, one pixel data is written in parallel to four memory chips.
50はこの書込みの番地を発生する書込番地発生器であ
る。50 is a write address generator that generates this write address.
60は読出番地発生器である。ディジタル画像の横軸を
X、縦軸をYとすると、読出番地発生器60は任意の座
標(X、Y)とその近傍の座標(X+1.Y)、(X、
Y+1)、(X+1.Y+1〉との4座標点の画素デー
タの読出番地を同時にN組発生する。これらN組の読出
番地はメモリ部31〜3Nに1対1で送られ、メモリ部
31〜3Nはそれぞれ4個の画素データを同時に読出す
。60 is a read address generator. If the horizontal axis of the digital image is X and the vertical axis is Y, the read address generator 60 generates arbitrary coordinates (X, Y) and its neighboring coordinates (X+1.Y), (X,
N sets of read addresses for pixel data of four coordinate points (Y+1), (X+1. 3N read out four pixel data simultaneously.
40は並列−直列変換器であり、メモリ部31〜3Nが
読出した4N個の画素データを4個の画素データからな
るパラレルデータに並列直列変換し、出力端子70へ出
力する。Reference numeral 40 denotes a parallel-to-serial converter, which converts the 4N pixel data read by the memory units 31 to 3N into parallel data consisting of four pixel data, and outputs the parallel data to the output terminal 70.
入力端子10から入力する画素データのクロ・ンクと出
力端子70から出力する画素データのクロックとは同じ
であり、メモリ部31〜3Nの書込み及び読出しの動作
クロックのN倍になっている。The clock of pixel data inputted from the input terminal 10 and the clock of pixel data outputted from the output terminal 70 are the same, and are N times the operating clock for writing and reading of the memory sections 31 to 3N.
以上説明したように本発明は、同時に4点の画素データ
を読出しできる記憶手段を複数設け、これら記憶手段に
画素データを書込み4個の画素データを同時に読出す動
作を記憶手段の数だけ並列に行って記憶手段を構成する
メモリ部・ンプのこれら書込み読出し動作の処理速度を
ディジタル画像信号の速度より記憶手段の数だけ遅くす
ることにより、メモリチップの応答速度を上げることな
く高速で動作することができる効果がある。As explained above, the present invention provides a plurality of storage means capable of reading out pixel data of four points at the same time, writes pixel data to these storage means, and simultaneously reads out four pieces of pixel data in parallel as many times as there are storage means. By making the processing speed of these write/read operations of the memory unit/amplifier constituting the storage means slower than the speed of the digital image signal by the number of storage means, the memory chip can operate at high speed without increasing its response speed. There is an effect that can be done.
【図面の簡単な説明】
第1図は本発明の一実施例を示すブロック図である。
20・・・直列−並列変換器、31〜3N・・・メモリ
部、40・・・並列−直列変換器、50・・・書込番地
発土器、
6
O・・・読出番地発生器。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. 20...Serial-parallel converter, 31-3N...Memory section, 40...Parallel-serial converter, 50...Write address generator, 6O...Read address generator.
Claims (1)
Nは2以上の整数)に直列並列変換する直列−並列変換
器と、この直列−並列変換器が出力した前記N組の前記
画素データをそれぞれ書込み前記ディジタル画像の横軸
及び縦軸をX及びYとして任意の座標(X、Y)ならび
にこの座標(X、Y)の近傍の座標(X+1、Y)、(
X、Y+1)及び(X+1、Y+1)の4点の前記画素
データをそれぞれ読出し可能なN個の記憶手段と、これ
ら記憶手段が出力した4N点の前記画素データからなる
パラレルデータを前記4点の前記画素データからなるパ
ラレルデータに並列直列変換する並列−直列変換器とを
備えたことを特徴とするディジタル画像メモリ装置。 2、前記記憶手段のそれぞれに4N個のメモリチップを
含むことを特徴とする請求項1記載のディジタル画像メ
モリ装置。[Claims] 1. N sets (
N is an integer of 2 or more), and a serial-to-parallel converter that performs serial-to-parallel conversion, and writes the N sets of pixel data output from this serial-to-parallel converter, respectively, and converts the horizontal and vertical axes of the digital image into As Y, arbitrary coordinates (X, Y) and coordinates (X+1, Y) in the vicinity of this coordinate (X, Y), (
N storage means each capable of reading out the pixel data at the four points ( A digital image memory device comprising: a parallel-to-serial converter that converts the pixel data into parallel data into parallel data. 2. The digital image memory device according to claim 1, wherein each of said storage means includes 4N memory chips.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1319920A JPH03181280A (en) | 1989-12-08 | 1989-12-08 | Digital picture memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1319920A JPH03181280A (en) | 1989-12-08 | 1989-12-08 | Digital picture memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03181280A true JPH03181280A (en) | 1991-08-07 |
Family
ID=18115707
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1319920A Pending JPH03181280A (en) | 1989-12-08 | 1989-12-08 | Digital picture memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03181280A (en) |
-
1989
- 1989-12-08 JP JP1319920A patent/JPH03181280A/en active Pending
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