JPH03171741A - Manufacture of gaas fet - Google Patents
Manufacture of gaas fetInfo
- Publication number
- JPH03171741A JPH03171741A JP1309179A JP30917989A JPH03171741A JP H03171741 A JPH03171741 A JP H03171741A JP 1309179 A JP1309179 A JP 1309179A JP 30917989 A JP30917989 A JP 30917989A JP H03171741 A JPH03171741 A JP H03171741A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- photoresist layer
- gate
- recess
- gate metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000002184 metal Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 21
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 7
- 238000007740 vapor deposition Methods 0.000 claims description 4
- 230000003321 amplification Effects 0.000 abstract description 4
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 5
- 230000008021 deposition Effects 0.000 abstract 3
- 238000010894 electron beam technology Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004347 surface barrier Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、マイクロ波帯の高い周波数帯域でも低雑音特
性を発揮するためにゲート長を短くした高周波、低雑音
増幅用のＧａＡｓＦＥＴの製造方法に関する．
〔従来の技術〕
ＧａＡｓの表面には、シリコンの表面のように、酸素中
で加熱処理し、丈夫な酸化物を形成することができない
ため、ＭＯＳ形ゲートを形成することができなく、Ｇａ
ＡｓＦＥＴは表面障壁型（ショットキー形障壁）ゲート
構造を採る．
第２図は従来のゲート長が０．２５μ階のＧａＡｓＦＥ
Ｔの製造方法の一例を示す。[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a method for manufacturing a GaAsFET for high-frequency, low-noise amplification in which the gate length is shortened in order to exhibit low-noise characteristics even in the high frequency band of the microwave band. Regarding. [Prior Art] Unlike the surface of silicon, GaAs cannot be heat-treated in oxygen to form a durable oxide, so it is impossible to form a MOS gate.
AsFET uses a surface barrier type (Schottky type barrier) gate structure. Figure 2 shows a conventional GaAsFE with a gate length of 0.25 μm.
An example of a method for manufacturing T is shown below.
まず、ＧａＡｓ動作層にバンチスルー防止用の層形成の
ためのイオン注入を行ない、ＧａＡｓ動作層１にソース
電極２・ドレイン電極３形成〔図（ａ）〕後、電子線露
光技術を用い、２段階露光により、開口部において下の
部分が０．２５μ階幅で上の部分が幅のより広い２段階
構造のレジスト層１４を形成し（図（ｂ））、このレジ
スト層ｌ４をマスクにリセスエッチングを行ない〔図（
Ｃ）） （リセス横造を採らないものもある）、次に
、真上から第１層のゲートメタル７を蒸着し、第１層の
ゲートメタル７の上に第２層のゲートメタル８を蒸着す
る〔図（ｄ））．レジスト層ｌ４の表面に蒸着されたゲ
ートメタル７と該ゲートメタル７上に蒸着されたゲート
メタル８は、リセス開口底６表面に蒸着されたゲートメ
タル７と該ゲートメタル７上に蒸着されたゲートメタル
８からリフトオフされ、レジスト層ｌ４を除去すると、
ゲート部分以外の蒸着メタルが除去され、ゲートが形成
される。First, ions are implanted into the GaAs active layer to form a layer for preventing bunch-through, and after forming the source electrode 2 and drain electrode 3 on the GaAs active layer 1 [Figure (a)], electron beam exposure technology is used to By stepwise exposure, a resist layer 14 with a two-step structure in which the lower part is 0.25μ step wide and the upper part is wider is formed at the opening (Figure (b)), and this resist layer 14 is used as a mask to form a resist layer 14. Perform etching [Figure (
C)) (Some products do not have a horizontal recessed structure.) Next, the first layer of gate metal 7 is deposited from directly above, and the second layer of gate metal 8 is deposited on top of the first layer of gate metal 7. Vapor deposition (Figure (d)). The gate metal 7 deposited on the surface of the resist layer l4 and the gate metal 8 deposited on the gate metal 7 are the same as the gate metal 7 deposited on the surface of the recess opening bottom 6 and the gate metal 7 deposited on the gate metal 7. When lifted off from metal 8 and removing resist layer l4,
The deposited metal other than the gate portion is removed to form a gate.
従来の上記の製造方法では、０．２５μ−幅の開口部を
持つレジスト層パターンを形戒するため非常に高価な電
子線露光装置が必要であり、電子線露光装置を用いるた
め、バッチ処理ができない。The conventional manufacturing method described above requires a very expensive electron beam exposure system to form a resist layer pattern with a 0.25μ-wide opening, and since the electron beam exposure system is used, batch processing is not required. Can not.
そのうえ、リセスエッチングでできるレジスト層１４の
庇とリセス開口底６との間の空間のために、ゲートメタ
ル蒸着時に廻り込みが生じ、実際のゲート長がレジスト
層パターン幅より拡がる。Furthermore, due to the space between the eaves of the resist layer 14 created by recess etching and the bottom of the recess opening 6, wraparound occurs during gate metal deposition, and the actual gate length becomes wider than the resist layer pattern width.
また、多層ゲートメタルの場合、上記メタルの廻り込み
の影響で、２層目、３層目のメタルが、ゲート脇でＧａ
Ａｓ層と接触するという問題があった。In addition, in the case of a multilayer gate metal, due to the effect of the above-mentioned metal wrapping around, the second and third layer metals are exposed to Ga on the side of the gate.
There was a problem of contact with the As layer.
本発明は、上記のような問題に鑑みてなされたもので、
電子線露光装置を使用することなく、信頼性の高い高周
波、低雑音増幅用のＧａＡｓ Ｆ Ｅ Ｔを製造ずる製
造方法を提供することを目的とする。The present invention was made in view of the above problems, and
It is an object of the present invention to provide a manufacturing method for manufacturing a highly reliable GaAs FET for high frequency, low noise amplification without using an electron beam exposure device.
本発明の製造方法は、ＧａＡｓ動作層にソース・ドレイ
ン電極形戒後、ゲート領域に通常の遠紫外線露光法によ
り所定の幅の開ロパターンを有するフォトレジスト層を
形成し、このフォトレジスト層をマスクにリセスエソチ
ングを行ない、上記フォトレジスト層の庇を利用し、絶
縁膜の斜め蒸着によりリセス開口底に上記フォトレジス
ト層の開口パターン幅より狭い開口パターンを有する絶
縁膜を形成し、真上からのゲートメタルの蒸着により、
上記絶縁膜の間ロバターン内でＧａＡｓ動作層に接合す
るオーバレイ構造のゲートを形成するものである。In the manufacturing method of the present invention, after forming source and drain electrodes on the GaAs active layer, a photoresist layer having an open pattern of a predetermined width is formed in the gate region by a normal deep ultraviolet exposure method. Recess etching is performed on the mask, and an insulating film having an opening pattern narrower than the opening pattern width of the photoresist layer is formed at the bottom of the recess opening by diagonal vapor deposition of an insulating film using the eaves of the photoresist layer. By vapor deposition of gate metal,
A gate with an overlay structure is formed within the lobe pattern between the insulating films and connected to the GaAs active layer.
第１図は本発明の一実施例を示す。 FIG. 1 shows an embodiment of the invention.
ＧａＡｓ動作ｌ！１にソース電極２、ドレイン電極３を
形成ｃ図（ａ）〕後、通常の遠紫外線露光法により、ゲ
ート領域に所定の幅の開口パターンを有するフォトレジ
スト層４を形成し〔図（ｂ））、フォトレジスト層４を
マスクにゲート領域のＧａＡｓ動作層ｌをリセスエソチ
ングし〔図（Ｃｌ）、次にフォトレジスト層４の庇を利
用し、絶縁膜の斜め蒸着によりリセス開口底６に０．２
５μ幅幅の開ロパターンを有する絶縁膜５を形成する〔
図（ｄ》〕。GaAs operation! After forming a source electrode 2 and a drain electrode 3 on the gate region 1 (Fig. (a)), a photoresist layer 4 having an opening pattern of a predetermined width is formed in the gate region by a conventional deep ultraviolet exposure method (Fig. (b)). ), using the photoresist layer 4 as a mask, the GaAs active layer 1 in the gate region is recessed and etched (Fig. (Cl)). Next, using the eaves of the photoresist layer 4, an insulating film is diagonally deposited to form a 0.00000000000000000000000 in the bottom of the recess opening 6. 2
An insulating film 5 having an open pattern with a width of 5μ is formed [
Figure (d)].
次に、真上から第１層目のゲートメタル７を蒸着し、続
いて、第２層目のゲートメタル８を蒸着する〔図（ｅ）
〕。Next, a first layer of gate metal 7 is deposited from directly above, and then a second layer of gate metal 8 is deposited [Figure (e)
].
フォトレジスｌ−Ｊｉｄ上に蒸着された絶縁膜５とこの
絶縁膜５上に蒸着された第１層目のゲートメタル７とこ
のゲートメタル７上に蒸着された第２層目のゲートメタ
ル８は、リセス開口底６上の蒸着部分からリフトオフさ
れ、フォトレジスト層４を除去すると、リセス開口底６
上のオーバーレイ構造のゲート部分のみが残る〔図（ｒ
））−上記の方法によると、フォトレジスト層４の開口
部パターンを微細にする必要がなく、遠紫外線露光法で
容易に形成できる幅であっても、絶縁膜５の開口部幅を
０．２５μ一にすることができ、ゲート長０．２５μ−
のオーバーレイ構造のゲートが得られる。The insulating film 5 deposited on the photoresist l-Jid, the first layer gate metal 7 deposited on this insulating film 5, and the second layer gate metal 8 deposited on this gate metal 7 are as follows. , is lifted off from the deposited portion on the recess opening bottom 6, and when the photoresist layer 4 is removed, the recess opening bottom 6
Only the gate part of the overlay structure above remains [Figure (r
)) - According to the above method, there is no need to make the opening pattern of the photoresist layer 4 finer, and even if the width can be easily formed by deep ultraviolet exposure, the opening width of the insulating film 5 can be reduced to 0. 25μ can be set to one, gate length 0.25μ-
A gate with an overlay structure is obtained.
そして、開口幅０．２５μ−パターンの絶縁膜５とリセ
ス開口底６との間には空間がないので、実際のゲート長
は０．２５μ鰯内におさまる。Since there is no space between the insulating film 5 of the opening width 0.25μ pattern and the recess opening bottom 6, the actual gate length falls within 0.25μ.
以上説明したように、本発明によれば、電子線露光装置
を用いることなく高周波、低雑音増幅用のＧａＡｓＦＥ
Ｔを製造することができ、かつ、第２層目、第３層目な
どのゲートメタルがＧａＡｓ層と接触することがなくな
るなどの利点がある．As explained above, according to the present invention, GaAsFE for high frequency, low noise amplification can be used without using an electron beam exposure device.
This method has the advantage that it is possible to manufacture T, and gate metals such as the second and third layers do not come into contact with the GaAs layer.
第１図は本発明の一実施例を示す説明図、第２図は従来
のゲート長が０．２５μ一のＧａＡｓＦＥＴの製造方法
の一例を示す説明図である．
ｌ・・・ＧａＡｓ動作層、２・・・ソース電極、３・・
・ドレイン電極、４・・・フォトレジスト層、５・・・
絶縁膜、６・・・リセス開口底、
７，
８・・・ゲートメタル。
なお図中同一符号は同一または担当する部分を示す。FIG. 1 is an explanatory diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing an example of a conventional method for manufacturing a GaAsFET with a gate length of 0.25 μm. l...GaAs operating layer, 2...source electrode, 3...
- Drain electrode, 4... Photoresist layer, 5...
Insulating film, 6... Recess opening bottom, 7, 8... Gate metal. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
ゲート領域に所定の幅の開口パターンを有するフォトレ
ジスト層を形成し、該フォトレジスト層をマスクにゲー
ト領域のＧａＡｓ動作層のリセスエッチングを行ない、
リセスエッチング後、上記フォトレジスト層の庇を利用
し、絶縁膜の斜め蒸着によりリセス開口底に上記フォト
レジスト層の開口パターン幅より狭い開口パターンを有
する絶縁膜を形成し、真上からゲートメタルを蒸着し、
上記フォトレジスト層でリフトオフさせ、リセス開口底
に上記絶縁膜の開口パターンでＧａＡｓ動作層に接合す
るオーバレイ構造のゲートを形成することを特徴とする
ＧａＡｓＦＥＴの製造方法。After forming source and drain electrodes on the GaAs active layer,
forming a photoresist layer having an opening pattern of a predetermined width in the gate region, and performing recess etching of the GaAs active layer in the gate region using the photoresist layer as a mask;
After recess etching, an insulating film having an opening pattern narrower than the opening pattern width of the photoresist layer is formed at the bottom of the recess opening by diagonal vapor deposition of an insulating film using the eaves of the photoresist layer, and the gate metal is applied from directly above. vapor deposited,
A method for manufacturing a GaAs FET, characterized in that lift-off is performed using the photoresist layer, and a gate having an overlay structure is formed at the bottom of the recess opening to be bonded to the GaAs active layer using the opening pattern of the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1309179A JPH03171741A (en) | 1989-11-30 | 1989-11-30 | Manufacture of gaas fet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1309179A JPH03171741A (en) | 1989-11-30 | 1989-11-30 | Manufacture of gaas fet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03171741A true JPH03171741A (en) | 1991-07-25 |
Family
ID=17989883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1309179A Pending JPH03171741A (en) | 1989-11-30 | 1989-11-30 | Manufacture of gaas fet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03171741A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9263292B2 (en) | 2004-07-12 | 2016-02-16 | Globalfoundries Inc. | Processing for overcoming extreme topography |
-
1989
- 1989-11-30 JP JP1309179A patent/JPH03171741A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9263292B2 (en) | 2004-07-12 | 2016-02-16 | Globalfoundries Inc. | Processing for overcoming extreme topography |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0883809A (en) | Manufacture of semiconductor device | |
| US4525448A (en) | Method of fabricating sub-half-micron-size gates on semiconductor substrates | |
| JPH03171741A (en) | Manufacture of gaas fet | |
| JP3612533B2 (en) | Manufacturing method of semiconductor device | |
| JPS61240684A (en) | Schottky-type field effect transistor and manufacture thereof | |
| JP3165712B2 (en) | Method for manufacturing semiconductor device | |
| JPS63273363A (en) | Manufacture of semiconductor device | |
| JPH0329328A (en) | Semiconductor device and its manufacture | |
| US6300190B1 (en) | Method for fabricating semiconductor integrated circuit device | |
| JPS6143484A (en) | Formation of electrode in semiconductor device | |
| JP2868771B2 (en) | Method of forming alignment mark for electron beam exposure | |
| JPH07107906B2 (en) | Method for manufacturing semiconductor device | |
| JPS62274715A (en) | Manufacture of semiconductor device | |
| JPS59114826A (en) | Manufacture of semiconductor device | |
| JPS63204742A (en) | Manufacture of semiconductor device | |
| JP3153560B2 (en) | Method for manufacturing semiconductor device | |
| JPH02165639A (en) | Manufacture of semiconductor element | |
| JP2002009275A (en) | Field effect compound semiconductor device | |
| JPS616870A (en) | Manufacture of field-effect transistor | |
| JPH02180032A (en) | Manufacture of gaas mesfet | |
| JPH0574817A (en) | Manufacture of semiconductor device | |
| JPS58197883A (en) | Manufacture of semiconductor device | |
| JPH03289142A (en) | Manufacture of compound semiconductor device | |
| JP2000031166A (en) | Fabrication of semiconductor device | |
| JP2002043317A (en) | Method for manufacturing semiconductor device |