JP2868771B2 - Method of forming alignment mark for electron beam exposure - Google Patents
Method of forming alignment mark for electron beam exposureInfo
- Publication number
- JP2868771B2 JP2868771B2 JP22126088A JP22126088A JP2868771B2 JP 2868771 B2 JP2868771 B2 JP 2868771B2 JP 22126088 A JP22126088 A JP 22126088A JP 22126088 A JP22126088 A JP 22126088A JP 2868771 B2 JP2868771 B2 JP 2868771B2
- Authority
- JP
- Japan
- Prior art keywords
- electron beam
- alignment mark
- beam exposure
- forming
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Electron Beam Exposure (AREA)
Description
【発明の詳細な説明】 〔発明の効果〕 （産業上の利用分野） 本発明は半導体装置の製造における電子ビーム露光用
位置合せマークの形成方法に関する。The present invention relates to a method for forming an alignment mark for electron beam exposure in the manufacture of a semiconductor device.
（従来の技術） 半導体装置の製造工程で要求される最小加工寸法は著
しく微細化されており、特に砒化ガリウム（GaAs）等の
化合物半導体を用いたマイクロ波半導体装置の最小ゲー
ト電極寸法はすでに0.25μｍに達している。このような
微細パターンの加工方法としては、電子ビームを用いた
電子ビーム露光技術が広く採用されている。(Prior Art) The minimum processing size required in the manufacturing process of a semiconductor device is remarkably miniaturized. In particular, the minimum gate electrode size of a microwave semiconductor device using a compound semiconductor such as gallium arsenide (GaAs) is already 0.25. μm. As a method for processing such a fine pattern, an electron beam exposure technique using an electron beam is widely adopted.
電子ビーム露光で半導体基板上の所望の位置にパター
ンを形成するために必要な位置合せマークは、半導体基
板上に平面形状が十字形またはＬ字形のパターン、ある
いは半導体基板のエツチングパターンを使用することが
多い。この位置合せマークの形成条件によつて検出位置
精度及び検出信号のS/N比が大幅に左右される。電子ビ
ーム露光用位置合せマークに対して要求される条件はマ
ークのエツジ部がシヤープに切り立つていることやマー
クの表面が平坦であることが最も重要である。The alignment mark required to form a pattern at a desired position on the semiconductor substrate by electron beam exposure should use a cross-shaped or L-shaped pattern on the semiconductor substrate or an etching pattern on the semiconductor substrate. There are many. The detection position accuracy and the S / N ratio of the detection signal are greatly affected by the conditions for forming the alignment marks. The most important condition required for the alignment mark for electron beam exposure is that the edge of the mark is sharply cut and the surface of the mark is flat.
しかし電子ビーム露光は、露光に長時間要するため通
常の光露光に比べてスループツトが無く半導体装置を製
造するに際し、最も加工精度が要求される工程にのみ使
用されることが多い。例えばGaAsFETを用いたシヨツト
キ障壁型電界効果トランジスタ（以下MESFETと称す）で
は、ゲート電極のパターン形成を行うことが一般的であ
る。However, since electron beam exposure requires a long time for exposure, it is often used only in a process that requires the highest processing accuracy when manufacturing a semiconductor device without throughput compared to ordinary light exposure. For example, in a Schottky barrier field effect transistor (hereinafter referred to as MESFET) using GaAsFET, it is common to form a gate electrode pattern.
MESFETの特性はゲート電極の寸法とオーミツク電極で
あるソース電極及びドレイン電極との距離によつて大き
な影響を受ける。したがつて、MESFETのゲート電極はオ
ーミツク電極に対して精度よく位置合せを行なわなけれ
ばならない。このためMESFETに用いられる電子ビーム露
光用位置合せマークはオーミツク電極の形成と同時に形
成されるのが望ましい。The characteristics of the MESFET are greatly affected by the dimensions of the gate electrode and the distance between the source electrode and the drain electrode, which are the ohmic electrodes. Therefore, the gate electrode of the MESFET must be accurately aligned with the ohmic electrode. For this reason, it is desirable that the alignment mark for electron beam exposure used in the MESFET be formed simultaneously with the formation of the ohmic electrode.
しかしながら、MESFETのオーミツク電極は一般にNiと
AuGeからなる合金が用いられ半導体基板とのオーミツク
接触を得るために450℃以上の高温で合金化処理が行な
われる。このため電子ビーム露光用位置合せマークをNi
とAuGeにより形成した場合には、半導体基板を構成して
いるGaAsとオーミツク電極を形成するAu,Ge,Niとの相互
の拡散により位置合せマークのエツジ部の劣化及び表面
の平坦性を著しく損ねてしまう。However, the ohmic electrode of MESFET is generally Ni
An alloy made of AuGe is used, and an alloying process is performed at a high temperature of 450 ° C. or more in order to obtain ohmic contact with the semiconductor substrate. Therefore, the alignment mark for electron beam exposure is
And AuGe, the GaAs forming the semiconductor substrate and the Au, Ge, Ni forming the ohmic electrode are mutually diffused. Would.
したがつて、オーミツク電極と同時に電子ビーム露光
用位置合せマークを形成しても電気ビーム照射によつて
得られる位置検出精度や検出信号のS/N比は要求される
値に対して不十分である。Therefore, even if the alignment mark for electron beam exposure is formed simultaneously with the ohmic electrode, the position detection accuracy and the S / N ratio of the detection signal obtained by electric beam irradiation are insufficient for the required values. is there.
加えて合金化後の位置合せマークの表面状態はNiとAu
Geのわずかな組成の違い及び合金化の際の温度、時間等
の条件が多少変化するだけでまつたく変わつた状態とな
り、ひどい場合には検出信号の雑音成分が多すぎてマー
ク検出不能となる場合もある。In addition, the surface condition of the alignment mark after alloying is Ni and Au.
A slight difference in the composition of Ge and a slight change in the conditions such as temperature and time during alloying result in a state of sudden change.In severe cases, the mark signal cannot be detected due to too much noise component of the detection signal. In some cases.
またオーミツク電極と電子ビーム用位置合せマークと
を別々にパターニングし、電子ビーム用位置合せマーク
がオーミツク電極形成時の熱処理の影響を受けない構造
とした場合、これら２つのパターン間における相対的な
位置ずれが発生しゲート電極の位置が設計値からずれて
しまいMESFETの特性変動を引き起こしてしまう。When the ohmic electrode and the electron beam alignment mark are separately patterned to have a structure in which the electron beam alignment mark is not affected by the heat treatment at the time of forming the ohmic electrode, the relative position between these two patterns is determined. A shift occurs, and the position of the gate electrode shifts from a design value, causing a change in the characteristics of the MESFET.
（発明が解決しようとする課題） 以上述べたように従来の電子ビーム露光用位置合せマ
ークの形成方法では、オーミツク電極形成の際の熱処理
工程により位置合せマークが変形してゲート電極の位置
合せを正確にすることができなかつた。そこで本発明で
はこのような欠点を排除し、ゲート電極の正確な位置合
せを行なうことができる位置合せマークを形成すること
を目的とする。(Problems to be Solved by the Invention) As described above, in the conventional method for forming an alignment mark for electron beam exposure, the alignment mark is deformed by a heat treatment step at the time of forming the ohmic electrode, and the alignment of the gate electrode is performed. Can not be exactly. In view of the foregoing, an object of the present invention is to eliminate such a drawback and form an alignment mark capable of performing accurate alignment of a gate electrode.
（課題を解決するための手段） 上記目的を達成するために本発明の電子ビーム露光用
位置合せマークの形成方法では、一方の面に活性層が形
成された半導体基板の電子ビーム走査領域に薄膜のみを
形成する工程と、前記半導体基板の活性層が形成された
領域にオーミツク電極用金属膜及び前記薄膜上に電子ビ
ーム露光用位置合せマークをそれぞれ同時にかつ同一金
属で形成する工程とを含むものである。(Means for Solving the Problems) In order to achieve the above object, in the method for forming an alignment mark for electron beam exposure according to the present invention, a thin film is formed on an electron beam scanning region of a semiconductor substrate having an active layer formed on one surface. Forming only an ohmic electrode metal film in the region of the semiconductor substrate where the active layer is formed and simultaneously forming an electron beam exposure alignment mark on the thin film with the same metal. .
（作 用） 本発明の電子ビーム露光用位置合せマークの形成方法
では、位置合せマークを半導体基板上に形成した薄膜上
に形成し、またオーミツク電極用金属膜と同時にかつ同
一金属を用いて形成することにより、オーミツク電極用
金属膜の合金化処理に伴う熱処理に対して位置合せマー
クと半導体基板との相互拡散が抑制できるとともに、オ
ーミツク電極とゲート電極の正確な位置合せを行なうこ
とができる。(Operation) In the method for forming an alignment mark for electron beam exposure according to the present invention, the alignment mark is formed on a thin film formed on a semiconductor substrate and is formed simultaneously with the same metal as the ohmic electrode metal film. By doing so, the interdiffusion between the alignment mark and the semiconductor substrate can be suppressed with respect to the heat treatment accompanying the alloying treatment of the ohmic electrode metal film, and the accurate alignment between the ohmic electrode and the gate electrode can be performed.
（実施例） 以下本発明の一つの実施例について図面を参照して説
明する。第１図（ａ）〜第１図（ｄ）は本発明の電子ビ
ーム露光用位置合せマークの形成方法の一実施例につい
てMESFETの製造方法を例に示した図である。(Embodiment) One embodiment of the present invention will be described below with reference to the drawings. FIGS. 1 (a) to 1 (d) are views showing an example of a method of forming an alignment mark for electron beam exposure according to the present invention using a method of manufacturing a MESFET.
第１図（ａ）に示すように半導体基板1,例えば半絶縁
性GaAs基板上に活性層２を形成した後、この半導体基板
１上に第１のレジスト膜３を積層し、活性層２が形成さ
れない部分のマーク検出のための電子ビーム走査領域に
開口を設け、全面にタングステンを用いた薄膜４を1000
Å蒸着する。As shown in FIG. 1A, after an active layer 2 is formed on a semiconductor substrate 1, for example, a semi-insulating GaAs substrate, a first resist film 3 is laminated on the semiconductor substrate 1, and the active layer 2 is formed. An opening is provided in the electron beam scanning area for mark detection in a portion where no mark is formed, and a thin film 4 using tungsten is
ÅEvaporate.
次に第１図（ｂ）に示すように、第１のレジスト膜３
及び第１のレジスト膜上の薄膜４をリフトオフ法により
除去した後に、半導体基板１にSiO2膜５、第２のレジス
ト膜６を順次積層する。さらに、SiO2膜５をエツチング
除去するために第２のレジスト膜６に第１の開口７及び
第２の開口８を形成する。ここで第１の開口７はオーミ
ツク電極であるソース電極及びドレイン電極を形成する
ために第２のレジスト膜６の活性層２が形成された部分
に対応する位置に２ケ所形成する。また、第２の開口８
は位置合せマークを形成するために第２のレジスト膜６
の薄膜が形成された部分に対応する位置に１ケ所形成す
る。その後、第２のレジスト膜６をマスクにして露出し
たSiO2膜５を同時にエツチング除去する。Next, as shown in FIG. 1B, the first resist film 3
After removing the thin film 4 on the first resist film by a lift-off method, an SiO 2 film 5 and a second resist film 6 are sequentially laminated on the semiconductor substrate 1. Further, a first opening 7 and a second opening 8 are formed in the second resist film 6 in order to remove the SiO 2 film 5 by etching. Here, two first openings 7 are formed at positions corresponding to the portions of the second resist film 6 where the active layers 2 are formed in order to form source and drain electrodes as ohmic electrodes. Also, the second opening 8
Is a second resist film 6 for forming an alignment mark.
Is formed at a position corresponding to the portion where the thin film is formed. Thereafter, the exposed SiO 2 film 5 is simultaneously removed by etching using the second resist film 6 as a mask.
次に第１図（ｃ）に示すように、Ni−AuGeで構成され
た金属膜を第１の開口７及び第２開口８を通して活性層
２及び薄膜４上にそれぞれ300Å、2000Å被着する。こ
こで第１の開口７を通して被着された金属膜はオーミツ
ク電極用金属膜９−１となり第２の開口８を通して被着
された金属膜は位置合せマーク用金属膜９−２となる。
さらにリフトオフ法を用いて不要部分の金属膜を第２の
レジスト膜６とともに除去する。Next, as shown in FIG. 1 (c), a metal film made of Ni—AuGe is deposited on the active layer 2 and the thin film 4 through the first opening 7 and the second opening 8, respectively, by 300 ° and 2000 °. Here, the metal film deposited through the first opening 7 becomes the ohmic electrode metal film 9-1 and the metal film deposited through the second opening 8 becomes the alignment mark metal film 9-2.
Further, an unnecessary portion of the metal film is removed together with the second resist film 6 by using a lift-off method.
次に第１図（ｄ）に示すようにSiO2膜５を剥離し450
℃以上の高温で合金化処理を行なつてオーミツク電極10
を形成し、最後に電子ビーム露光によつて位置合せマー
ク９−２をターゲツトにゲート電極の位置合せを行なつ
てゲート電極11を形成することによりMESFETが完成す
る。Then peeling the SiO 2 film 5 as shown in FIG. 1 (d) 450
Alloying is performed at a high temperature of at least
Finally, the MESFET is completed by aligning the gate electrode with the alignment mark 9-2 as a target by electron beam exposure to form the gate electrode 11.
このようにして得られた電子ビーイ露光用位置合せマ
ークはタングステンの薄膜で半導体基板と分離されてい
るので、オーミツク接触を得るための熱処理ではNi−Au
GeとGaAsの相互拡散がほとんど生じないため電子ビーム
露光用位置合せマークの変形はなく位置合せを行なう場
合良好な位置検出信号が得られる。Since the alignment mark for electron beam exposure obtained in this manner is separated from the semiconductor substrate by a thin film of tungsten, Ni-Au is not heat-treated to obtain ohmic contact.
Since almost no mutual diffusion of Ge and GaAs occurs, there is no deformation of the alignment mark for electron beam exposure, and a good position detection signal can be obtained when performing alignment.
また、薄膜を形成する場合、第１のレジストパターン
を開口した後、この開口を通して半導体基板を適当な深
さにエツチングすればより容易にリフトオフすることが
できる。In the case of forming a thin film, the lift-off can be more easily performed by opening the first resist pattern and then etching the semiconductor substrate to an appropriate depth through the opening.
上記実施例では薄膜としてタングステンを用いたがオ
ーミツク電極用金属と半導体基板との相互拡散を抑制す
る他の物質、例えばタンタル、プラチナ、モリブデンな
どの金属薄膜あるいはSiO2など絶縁物薄膜やであつても
よい。また、オーミツク電極用金属はNi−AuGeに限定さ
れるものではなくAu−AuGe、AuGeでもよい。In the above embodiment, tungsten was used as the thin film. However, other materials that suppress interdiffusion between the metal for the ohmic electrode and the semiconductor substrate, such as a metal thin film such as tantalum, platinum, and molybdenum, or an insulating thin film such as SiO 2, were used. Is also good. The metal for the ohmic electrode is not limited to Ni-AuGe, but may be Au-AuGe or AuGe.
さらに、電子ビーム露光に限定されず、他の荷電ビー
ム露光、例えばイオンビームにおいても適用できること
は無論である。更に薄膜の形成方法はリフトオフ法のみ
ならずエツチング法を用いてもよいことは無論である。Further, it is needless to say that the present invention is not limited to the electron beam exposure, but can be applied to other charged beam exposures, for example, an ion beam. Further, it goes without saying that the etching method as well as the lift-off method may be used for forming the thin film.
以上述べたように本発明によれば、位置合せマークを
半導体基板に形成した薄膜上に設けるので、オーミツク
電極形成時の合金化処理に伴なう熱処理工程による位置
合せマークの変形が行ならない。As described above, according to the present invention, since the alignment mark is provided on the thin film formed on the semiconductor substrate, the alignment mark is not deformed by the heat treatment process accompanying the alloying process when forming the ohmic electrode.
したがつて、位置検出精度が高く、雑音成分が少ない
検出信号が得られ良好な電子ビーム露光用位置合せマー
クを形成することができる。Accordingly, it is possible to obtain a detection signal with high position detection accuracy and a small noise component, and to form a good alignment mark for electron beam exposure.
第１図（ａ）乃至第１図（ｄ）は本発明の一実施例を示
す工程断面図である。 １……半導体基板、２……活性層、４……薄膜、 ９−１……オーミツク電極用金属膜 ９−２……位置合せマーク1 (a) to 1 (d) are process sectional views showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Active layer, 4 ... Thin film, 9-1 ... Metal film for ohmic electrodes 9-2 ... Alignment mark
フロントページの続き (56)参考文献 特開 平１−117029（ＪＰ，Ａ) 特開 平１−117030（ＪＰ，Ａ) 特開 平１−117027（ＪＰ，Ａ) 特開 昭63−187628（ＪＰ，Ａ) 特開 昭63−148629（ＪＰ，Ａ) 特開 昭64−81317（ＪＰ，Ａ) 特開 昭63−94625（ＪＰ，Ａ) 特開 昭63−187629（ＪＰ，Ａ) 特開 昭62−171120（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/27 Continuation of the front page (56) References JP-A 1-117029 (JP, A) JP-A 1-111730 (JP, A) JP-A 1-117027 (JP, A) JP-A 63-187628 (JP JP-A-63-148629 (JP, A) JP-A-64-81317 (JP, A) JP-A-63-94625 (JP, A) JP-A-63-187629 (JP, A) 62-171120 (JP, A) (58) Field surveyed (Int. Cl. 6 , DB name) H01L 21/27
Claims (1)
電子ビーム露光法における前記マークを形成する電子ビ
ーム露光用位置合せマークの形成方法において、一方の
面に活性層が形成された半導体基板の電子ビーム走査領
域に薄膜のみ形成する工程と、前記半導体基板の活性層
が形成された領域にオーミック電極用金属膜及び前記薄
膜上に電子ビーム露光用位置合せマークをそれぞれ同時
にかつ同一金属で形成する工程とを含むことを特徴とす
る電子ビーム露光用位置合せマークの形成方法。1. An electron beam exposure method according to claim 1, wherein said mark is formed by electron beam scanning. In the method of forming an alignment mark for electron beam exposure, said electron beam is formed on a semiconductor substrate having an active layer formed on one surface. A step of forming only a thin film in the scanning region, and a step of forming an ohmic electrode metal film in the region where the active layer of the semiconductor substrate is formed and an electron beam exposure alignment mark on the thin film simultaneously and with the same metal. A method for forming an alignment mark for electron beam exposure, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22126088A JP2868771B2 (en) | 1988-09-06 | 1988-09-06 | Method of forming alignment mark for electron beam exposure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22126088A JP2868771B2 (en) | 1988-09-06 | 1988-09-06 | Method of forming alignment mark for electron beam exposure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0269928A JPH0269928A (en) | 1990-03-08 |
| JP2868771B2 true JP2868771B2 (en) | 1999-03-10 |
Family
ID=16763983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22126088A Expired - Fee Related JP2868771B2 (en) | 1988-09-06 | 1988-09-06 | Method of forming alignment mark for electron beam exposure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2868771B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311144A (en) * | 2012-03-16 | 2013-09-18 | 中国科学院微电子研究所 | Method for manufacturing electron beam alignment mark based on tungsten metal |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01117027A (en) * | 1987-10-30 | 1989-05-09 | Nec Corp | Position detection reference mark for electron beam |
-
1988
- 1988-09-06 JP JP22126088A patent/JP2868771B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0269928A (en) | 1990-03-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |