JPH03165147A - 4-phase demodulation circuit - Google Patents
4-phase demodulation circuitInfo
- Publication number
- JPH03165147A JPH03165147A JP30509689A JP30509689A JPH03165147A JP H03165147 A JPH03165147 A JP H03165147A JP 30509689 A JP30509689 A JP 30509689A JP 30509689 A JP30509689 A JP 30509689A JP H03165147 A JPH03165147 A JP H03165147A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- circuit
- vco
- output
- qpsk
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012935 Averaging Methods 0.000 claims abstract description 8
- 230000010354 integration Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000005236 sound signal Effects 0.000 description 5
- 238000005070 sampling Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000008929 regeneration Effects 0.000 description 2
- 238000011069 regeneration method Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
本発明は、衛星放送受信機において、音声信号を復調す
るための4位相復調回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a four-phase demodulation circuit for demodulating audio signals in a satellite broadcasting receiver.
「従来の技術」
一般に、衛星放送受信機は第4図に示すように、放送衛
星(1)からの電波をパラボラアンテナ(2)で受信し
、BSコンバータ(3)でIGHz帯の中間周波数帯に
変換し、BSチューナ(4)に送られる。"Prior Art" Generally, as shown in Figure 4, a satellite broadcasting receiver receives radio waves from a broadcasting satellite (1) with a parabolic antenna (2), and converts them into intermediate frequency bands in the IGHz band with a BS converter (3). and sent to the BS tuner (4).
このBSチューナ(4)では選局回路(5)により希望
するチャンネルを選択し、FM復調回路(6)でFM復
調をした後、映像−音声分離回路(7)で映像信号と音
声信号に分離する。このうち、映像信号はデエンファシ
ス回路(8)、エネルギー拡散信号除去回路(9)によ
ってもとの映像信号を再生し、テレビ受像n(10)の
映像入力端子(11)に加える。In this BS tuner (4), the desired channel is selected by the channel selection circuit (5), FM demodulated by the FM demodulation circuit (6), and then separated into a video signal and an audio signal by the video-audio separation circuit (7). do. Of these, the original video signal is reproduced by a de-emphasis circuit (8) and an energy diffusion signal removal circuit (9), and is applied to the video input terminal (11) of the television receiver n (10).
他方、音声信号は4位相復調(以下QPSKという)回
路(12)、 PCMfjf調回路(13)によって復
調し、デエンファシス回路(14)によってもとの音声
信号に再生する。そして前記テレビ受像機(lO)の音
声入力端子(15)に加える。このようにして衛星放送
の受信を可能とする。On the other hand, the audio signal is demodulated by a four-phase demodulation (hereinafter referred to as QPSK) circuit (12) and a PCMfjf modulation circuit (13), and then reproduced into the original audio signal by a de-emphasis circuit (14). Then, it is applied to the audio input terminal (15) of the television receiver (10). In this way, satellite broadcasting can be received.
以上のような衛星放送受信機において、QPSK@路(
12)は第3図のように構成され、音声信号の復調をア
ナログ処理していた。この従来のQPSK回路(12)
において、QPSK信号は乗算器(17)(18)、L
P F (19) (20)を通り、2値化器(21
)(22)と位相差検出器(23)に送られる。位相差
検出器(23)ではQPSKも1号の発生側の搬送波の
位相と、搬送波再生回路としてのV CO(24)から
発生する再生搬送波の位相差を比較し、その差が0とな
るようにループフィルタ(35)を介してVCO(24
)に制御信号を加える。このV CO(24)からの発
振信号は、一方の乗算器(エフ)に−90°移相器(2
5)を介して送られ、また他方の乗算器(]8)にその
まま送られて入力したQPSK信号と乗算される。そし
て位相差が次第にOになって、復調信号として2値化器
(21) (22)から出力する。なお、(26)はピ
ットクロック再生回路である。In the above satellite broadcasting receiver, QPSK@route (
12) was constructed as shown in FIG. 3, and demodulated the audio signal using analog processing. This conventional QPSK circuit (12)
, the QPSK signal is passed through multipliers (17) (18), L
Pass through P F (19) (20) and binarizer (21
) (22) and a phase difference detector (23). In the phase difference detector (23), QPSK also compares the phase of the carrier wave on the generation side of No. 1 and the phase difference of the recovered carrier wave generated from the VCO (24) as a carrier wave recovery circuit, and makes sure that the difference becomes 0. to the VCO (24) via the loop filter (35).
). The oscillation signal from this V CO (24) is sent to one multiplier (F) through a -90° phase shifter (24).
5), and is sent directly to the other multiplier (]8) where it is multiplied by the input QPSK signal. Then, the phase difference gradually becomes O, and the signal is output as a demodulated signal from the binarizers (21) and (22). Note that (26) is a pit clock regeneration circuit.
しかるに、従来のQPSK回路(12)はすべてアナロ
グ信号で処理していたので、回路パラメータにばらつき
があること、動作がやや不安定であること、V CO(
24)からの出力は正弦波であるため一90°移相器(
25)での移相量に誤差が生じることなどの問題があっ
た。However, since the conventional QPSK circuit (12) processes all analog signals, there are variations in circuit parameters, somewhat unstable operation, and V CO (
Since the output from 24) is a sine wave, a 90° phase shifter (
25), there were problems such as an error occurring in the amount of phase shift.
そこで、本出願人は第2図に示すように、QPSKの復
調をディジタルで行うことによって従来の問題点を解決
するような回路を提案した。Therefore, the present applicant proposed a circuit that solves the conventional problems by performing QPSK demodulation digitally, as shown in FIG.
第3図の回路と異なる点は、QPSK入方端子方端子)
とディジタル形乗算器(27) (2g)の間に、A/
D変換器(31)を挿入し、また、乗算器(27) (
28)とL P F (29) (30)はそれぞれデ
ィジタル形を用い。The difference from the circuit in Figure 3 is the QPSK input terminal)
and digital multiplier (27) (2g), A/
A D converter (31) is inserted, and a multiplier (27) (
28) and L P F (29) and (30) respectively use digital forms.
さらに1位相差検出器(23)とV CO(24)の間
にD/A変換器(32)を介在したことである。Furthermore, a D/A converter (32) is interposed between the one phase difference detector (23) and the VCO (24).
このようなディジタル処理を行う構成とすることによっ
て、問題点を解決している。The problem is solved by using a configuration that performs such digital processing.
しかし、それでも若干の問題がある。QPSK回路では
、入力したQPSK信号の搬送波と同期した搬送波を再
生する必要があるが、QPSK信号の搬送波検出はその
信号の変調の影響を受けることである。すなわち、QP
SK信号はデータ伝送のため変調されているので、第5
図に示すような特性となっている。今、VCO(24)
の再生搬送波とQPSK入力信号の搬送波とに位相差が
あり。However, there are still some problems. In the QPSK circuit, it is necessary to reproduce a carrier wave that is synchronized with the carrier wave of the input QPSK signal, but carrier wave detection of the QPSK signal is affected by the modulation of the signal. That is, QP
Since the SK signal is modulated for data transmission, the fifth
The characteristics are as shown in the figure. Now VCO (24)
There is a phase difference between the reproduced carrier wave and the carrier wave of the QPSK input signal.
それが第5図のA点にあるとする。QPSK信号はデー
タ伝送のため、(−単位で位相が変化する。Assume that it is at point A in Figure 5. The phase of the QPSK signal changes in (-) units for data transmission.
そのため、A点に止っていることもあればA点からB点
に位相が移動することもある。A点に止っているときは
位相差検出器(23)は一定の位相差に対応する電圧を
出力する。ところが、A点からB点に移動するときは、
時間が0ということはないため、A点からB点へある速
度で変化し、その途中の位相差の電圧を発生する0位相
差検出器(23)の後段には通常、ループフィルタ(3
5)があり、高周波成分は除去され、直流成分のみが取
り出される。このA点に止っているときの位相差検出器
(23)の直流成分と、変化したときの直流分には一般
に差異がある。このため位相差検出器の出力を用いてQ
PSK信号の搬送波とvCoの再生搬送波との位相同期
をとるとき、不必要な振動がおきることがある。Therefore, the phase may remain at point A, or may move from point A to point B. When stopped at point A, the phase difference detector (23) outputs a voltage corresponding to a constant phase difference. However, when moving from point A to point B,
Since time is never 0, a loop filter (3
5), high frequency components are removed and only DC components are extracted. There is generally a difference between the DC component of the phase difference detector (23) when it remains at point A and the DC component when it changes. Therefore, using the output of the phase difference detector, Q
When achieving phase synchronization between the carrier wave of the PSK signal and the regenerated carrier wave of vCo, unnecessary vibrations may occur.
本発明はQPSK入力端子の搬送波とvcoからの再生
搬送波との位相同期をとる場合に、不必要な振動がおき
ないような回路を得ることである。The object of the present invention is to provide a circuit that does not cause unnecessary vibration when phase synchronizing the carrier wave of the QPSK input terminal and the reproduced carrier wave from the VCO.
「課題を解決するための手段」
本発明はQPSK入力端子に入力したQPSK信号を2
つに分岐し、それぞれ乗算器、LPF、2値化器を介し
て復調出力端子へ送るとともに。"Means for Solving the Problem" The present invention provides two
The signal is branched into two, and sent to the demodulation output terminal via a multiplier, an LPF, and a binarizer, respectively.
前記2つのLPFの出力を位相検出器を介してVCoへ
送り、このVCOの信号を前記一方の乗算器には移相器
を介して、また、他方の乗算器にはそのまま送ることに
より入力した搬送波と再生搬送波の位相差がOとなるよ
うに制御するようにしたものにおいて、前記位相検出器
とvcoとの間に位相差検出器の出力を所定時間にわた
って平均化するための平均化回路を介在してなるもので
ある。The outputs of the two LPFs were sent to the VCo via a phase detector, and the VCO signal was input to one of the multipliers via a phase shifter and to the other multiplier as it was. The phase difference between the carrier wave and the reproduced carrier wave is controlled to be O, and an averaging circuit is provided between the phase detector and the VCO to average the output of the phase difference detector over a predetermined period of time. It is something that occurs through intervention.
「作用」
QPSK入力端子に入力したQPSKは乗算器とLPF
を通過し、2値化器と位相差検出器に送られる6位相差
検出器ではQPSK信号の発生側の搬送波の位相と、V
COより発生する再生搬送波の位相差とを比較しその差
がOとなるように制御信号をVCOに加えるが位相差検
出器の出力は−・定時間分のデータを平均化しているの
で、位相の移動があっても平均化されて大差がなくなる
。"Operation" The QPSK input to the QPSK input terminal is connected to the multiplier and LPF.
The 6-phase difference detector passes through the QPSK signal and sends it to the binarizer and the phase difference detector.
A control signal is applied to the VCO so that the phase difference of the reproduced carrier wave generated by the CO is compared and the difference becomes O, but the output of the phase difference detector is - Since the data for a certain period of time is averaged, the phase Even if there is a movement, it will be averaged out and there will be no big difference.
VCOからの出力は一90°移相器を介し、また直接乗
算器へ加えられて位相差が0となるように処理される。The output from the VCO is processed through a 190° phase shifter and directly to a multiplier so that the phase difference is zero.
「実施例」 以下、本発明の一実施例を図面に基き″説明する。"Example" Hereinafter, one embodiment of the present invention will be described based on the drawings.
第1図において、第2図と異なるところは、位相差検出
器(23)の一定時間分の出力を平均化する平均化回路
(36)を介在したことである。この平均化回路(36
)は、位相差検出器(23)の出力を★倍する★倍回路
(37)と、一定時間(T)を8回サンプリングして積
算するための加算回路(38a)とラッチ回路(38b
)からなる積算回路(38)と、この積算回路(38)
のN回分の積算出力を次段へ送るために、N回のサンプ
リング毎に1回だけ閉じるスイッチ回路(39)と、積
算出力を次段へ送った後積算回路(38)をN回のサン
プリング毎に1回クリアするためのクリア回路(40)
とからなる。The difference between FIG. 1 and FIG. 2 is that an averaging circuit (36) is provided to average the output of the phase difference detector (23) over a certain period of time. This averaging circuit (36
) consists of a ★ multiplier circuit (37) that multiplies the output of the phase difference detector (23), an adder circuit (38a) for sampling and integrating a certain period of time (T) 8 times, and a latch circuit (38b).
) and this integrating circuit (38).
In order to send the integration output N times to the next stage, a switch circuit (39) is closed only once every N samplings, and after sending the integration output to the next stage, the integration circuit (38) is closed for N samplings. Clear circuit (40) for clearing once every time
It consists of
以上のような構成において、QPSK入力端子(16)
に入力したQPSK信号をA/D変換器(31)でディ
ジタル量に変換し、その信号はディジタル乗算器(27
) (28)とディジタルL P F (29) (3
0)を通過し、2値化器(21) (22)と位相差検
出器(23)に送られる0位相差検出器(23)ではQ
PSK信号の発生側の搬送波の位相と、V CO(24
)より発生する再生搬送波の位相差とを比較する。この
位相差検出器(23)の出力は、★倍回路(37)で前
借され、積算回路(38)で一定時間(T)の間に8回
サンプリングし積算される。N回積算されると、スイッ
チ回路(39)が閉じて平均値がループフィルタ(35
)へ送られる。送られると、積算回路(38)はクリア
回路(40)でクリアされて再び新たに積算を開始する
。In the above configuration, the QPSK input terminal (16)
The A/D converter (31) converts the input QPSK signal into a digital quantity, and the signal is sent to the digital multiplier (27).
) (28) and digital L P F (29) (3
0) and is sent to the binarizers (21) (22) and the phase difference detector (23).
The phase of the carrier wave on the generation side of the PSK signal and V CO (24
) is compared with the phase difference of the reproduced carrier wave generated by the carrier wave. The output of this phase difference detector (23) is pre-borrowed by a *multiplying circuit (37), and is sampled and integrated eight times during a fixed time (T) by an integrating circuit (38). When the integration is completed N times, the switch circuit (39) closes and the average value is passed through the loop filter (35).
). When sent, the integration circuit (38) is cleared by the clear circuit (40) and starts new integration again.
ループフィルタ(35)の出力はD/A変換器(32)
でアナログに変換してV CO(24)に加える。VC
O(24)からは矩形波が出力するが、これは実質的な
ディジタル信号であり、これが−90”移相器(25)
を介して一方のディジタル乗算器(27)へ送られると
ともに、直接他方のディジタル乗算器(28)へ送られ
る。このディジタル乗算器(27) (28)のデータ
が再びディジタルL P F (29) (30)を介
して位相検出器(23)で比較され、D/A変換された
制御信号をV CO(24)に加える。この動作を位相
差がOになるまで繰返えして2値化器(21)(22)
で2値化して復調出力として出力端子(33)(34)
からテレビ受信機(10)へ送られる。The output of the loop filter (35) is the D/A converter (32)
Convert it to analog and add it to V CO (24). VC
A square wave is output from O (24), which is essentially a digital signal, and this is the -90" phase shifter (25).
is sent to one digital multiplier (27) and directly to the other digital multiplier (28). The data from the digital multipliers (27) (28) is again compared by the phase detector (23) via the digital LPF (29) (30), and the D/A converted control signal is sent to the VCO (24). ). This operation is repeated until the phase difference becomes O, and the binarizer (21) (22)
to output terminals (33) (34) as demodulated output.
from there to the television receiver (10).
前記実施例では、V CO(24)をアナログ形とした
ため位相検出器(23)の出力をD/A変換[1(32
)でアナログに変換したが、V CO(24)をディジ
タル形とした場合には、D/A変換器(32)を省略す
ることができる。In the above embodiment, since the V CO (24) is of analog type, the output of the phase detector (23) is subjected to D/A conversion [1 (32).
), but if the VCO (24) is of digital type, the D/A converter (32) can be omitted.
前記実施例では、QPSK回路(12)がディジタル処
理の回路構成としたため、特に安定な動作となる。しか
し、第3図に示すアナログ処理のQPSK回路(12)
において平均化回路(36)を付加することもできる。In the embodiment described above, since the QPSK circuit (12) has a digital processing circuit configuration, the operation is particularly stable. However, the analog processing QPSK circuit (12) shown in Figure 3
An averaging circuit (36) can also be added.
「発明の効果」
本発明は上述のように構成したので、入力したQPSK
信号の搬送波とQPSK回路の再生搬送波の位相同期を
とるとき、不必要な振動がおきることがない。"Effects of the Invention" Since the present invention is configured as described above, the input QPSK
Unnecessary vibrations do not occur when the signal carrier wave and the reproduced carrier wave of the QPSK circuit are phase synchronized.
第1図は本発明による4位相復調回路の一実施例を示す
ブロック図、第2図はディジタル処理の4位相復調回路
のブロック図、第3図は従来のアナログ処理の回路のブ
ロック図、第4図は一般的な衛星放送受信機のブロック
図、第5図は位相差検出器の出力波形図である。
(1)・・・放送衛星、(2)・・・パラボラアンテナ
、(3)・・・BSコンバータ、(4)・・・BSチュ
ーナ、(5)・・・選周回路、(6)・・・FM復調回
路、(7)・・・映像−音声分離回路、(8)・・・デ
エンファシス回路、(9)・・・エネルギー拡散信号除
去回路、(10)・・・テレビ受像機、(11)・・・
映像入力端子、(12)・・・4位相復調回路、 (1
3)・・・、(14)・・・デエンファシス回路、(1
5)・・・音声入力端子(15)、(16)・・・、(
17) (1g)・・・乗算器、 (19)(20)・
・・LPF、(21)(22)・・・2値化器、(23
)・・・位相差検出器、(24)−V CO、(25)
−−−−90”移相器、(26)・ピットクロック再
生回路、(27) (28)・・・乗算器、(29)
(30)・・・LPF、(31)・・・A/D変換器、
(32)・・・D/A変換器、(33) (34)・・
・出力端子、 (35)・・・ループフィルタ、(36
)・・・平均化回路、(37)・・・★倍回路。
(38)・・・積算回路、(38a)・・・加算回路、
(38b)・・・ラッチ回路、(39)・・・スイッチ
回路、(40)・・・クリア回路。FIG. 1 is a block diagram showing an embodiment of a four-phase demodulation circuit according to the present invention, FIG. 2 is a block diagram of a four-phase demodulation circuit for digital processing, and FIG. 3 is a block diagram of a conventional analog processing circuit. FIG. 4 is a block diagram of a general satellite broadcasting receiver, and FIG. 5 is an output waveform diagram of a phase difference detector. (1)... Broadcasting satellite, (2)... Parabolic antenna, (3)... BS converter, (4)... BS tuner, (5)... Frequency selection circuit, (6)... ... FM demodulation circuit, (7) ... video-audio separation circuit, (8) ... de-emphasis circuit, (9) ... energy diffusion signal removal circuit, (10) ... television receiver, (11)...
Video input terminal, (12)...4-phase demodulation circuit, (1
3)..., (14)... de-emphasis circuit, (1
5)...Audio input terminals (15), (16)..., (
17) (1g)...multiplier, (19)(20)
...LPF, (21) (22) ... Binarizer, (23
)...Phase difference detector, (24)-V CO, (25)
-----90" phase shifter, (26)・Pit clock regeneration circuit, (27) (28)... Multiplier, (29)
(30)...LPF, (31)...A/D converter,
(32)...D/A converter, (33) (34)...
・Output terminal, (35)...Loop filter, (36
)...Averaging circuit, (37)...★Doubling circuit. (38)... Integration circuit, (38a)... Addition circuit,
(38b)...Latch circuit, (39)...Switch circuit, (40)...Clear circuit.
Claims (3)
に分岐し、それぞれ乗算器、LPF、2値化器を介して
復調出力端子へ送るとともに、前記2つのLPFの出力
を位相検出器を介してVCOへ送り、このVCOの信号
を前記一方の乗算器には移相器を介して、また、他方の
乗算器にはそのまま送ることにより入力した搬送波と再
生搬送波の位相差が0となるように制御するようにした
ものにおいて、前記位相検出器とVCOとの間に位相差
検出器の出力を所定時間にわたって平均化するための平
均化回路を介在してなることを特徴とする4位相復調回
路。(1) The QPSK signal input to the input terminal of the QPS is branched into two and sent to the demodulation output terminal via a multiplier, an LPF, and a binarizer, respectively, and the outputs of the two LPFs are sent to a phase detector. By sending this VCO signal to one of the multipliers via a phase shifter and sending it as is to the other multiplier, the phase difference between the input carrier wave and the reproduced carrier wave becomes 0. In the four-phase system, an averaging circuit is interposed between the phase detector and the VCO to average the output of the phase difference detector over a predetermined period of time. Demodulation circuit.
を介在し、前記乗算器およびLPFはディジタル形を用
い、前記位相検出器とVCOとの間にD/A変換器を介
在してなる請求項(1)記載の4位相復調回路。(2) An A/D converter is interposed between the input terminal and the multiplier in the QPS, the multiplier and LPF are of digital type, and the D/A converter is interposed between the phase detector and the VCO. 4. The four-phase demodulation circuit according to claim 1, wherein the four-phase demodulation circuit is formed by interposing the four-phase demodulation circuit.
を介在し、前記乗算器、LPFおよびVCOはディジタ
ル形を用いてなる請求項(1)記載の4位相復調回路。(3) The four-phase demodulation circuit according to claim 1, wherein an A/D converter is interposed between the input terminal of the QPS and the multiplier, and the multiplier, LPF, and VCO are of a digital type.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30509689A JP2932289B2 (en) | 1989-11-24 | 1989-11-24 | 4 phase demodulation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30509689A JP2932289B2 (en) | 1989-11-24 | 1989-11-24 | 4 phase demodulation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03165147A true JPH03165147A (en) | 1991-07-17 |
JP2932289B2 JP2932289B2 (en) | 1999-08-09 |
Family
ID=17941056
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30509689A Expired - Lifetime JP2932289B2 (en) | 1989-11-24 | 1989-11-24 | 4 phase demodulation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2932289B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001077871A (en) * | 1999-08-02 | 2001-03-23 | Mitsubishi Electric Inf Technol Center America Inc | Phase locked loop circuit for demodulator |
-
1989
- 1989-11-24 JP JP30509689A patent/JP2932289B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001077871A (en) * | 1999-08-02 | 2001-03-23 | Mitsubishi Electric Inf Technol Center America Inc | Phase locked loop circuit for demodulator |
Also Published As
Publication number | Publication date |
---|---|
JP2932289B2 (en) | 1999-08-09 |
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