JPH03165149A - 4-phase demodulation circuit - Google Patents
4-phase demodulation circuitInfo
- Publication number
- JPH03165149A JPH03165149A JP30509889A JP30509889A JPH03165149A JP H03165149 A JPH03165149 A JP H03165149A JP 30509889 A JP30509889 A JP 30509889A JP 30509889 A JP30509889 A JP 30509889A JP H03165149 A JPH03165149 A JP H03165149A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- vco
- signal
- digital
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010363 phase shift Effects 0.000 abstract description 5
- 238000006243 chemical reaction Methods 0.000 abstract 1
- 230000005236 sound signal Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000008929 regeneration Effects 0.000 description 3
- 238000011069 regeneration method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
本発明は、衛星放送受信機において、音声信号を復調す
るための4位相復調回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a four-phase demodulation circuit for demodulating audio signals in a satellite broadcasting receiver.
「従来の技術」 一般に、衛星放送受信機は第3図に示すように。"Conventional technology" Generally, a satellite broadcast receiver is as shown in Figure 3.
放送衛星(1)からの電波はパラボラアンテナ(2)で
受信し、BSコンバータ(3)でIGfh帯の中間周波
数帯に変換し、BSチューナ(4)に送られる。Radio waves from a broadcasting satellite (1) are received by a parabolic antenna (2), converted to an intermediate frequency band of the IGfh band by a BS converter (3), and sent to a BS tuner (4).
このBSチューナ(4)では選局回路(5)により希望
するチャンネルを選択し、FM復調回路(6)でFM復
調をした後、映像−音声分離回路(7)で映像信号と音
声信号に分離する。このうち、映像信号はデエンファシ
ス回路(8)、エネルギー拡散信号除去回路(9)によ
ってもとの映像信号を再生し、テレビ受像機(10)の
映像入力端子(11)に加える。In this BS tuner (4), the desired channel is selected by the channel selection circuit (5), FM demodulated by the FM demodulation circuit (6), and then separated into a video signal and an audio signal by the video-audio separation circuit (7). do. Of these, the original video signal is reproduced by a de-emphasis circuit (8) and an energy diffusion signal removal circuit (9), and is applied to a video input terminal (11) of a television receiver (10).
他方、音声信号は4位相後!I!l(以下QPSKとい
う)回路(12)、PCM復調回路(13)によって復
調し、デエンファシス回路(14)によってもとの音声
信号に再生する。そして前記テレビ受像機(10)の音
声入力端子(15)に加える。このようにして衛星放送
の受信を可能とする。On the other hand, the audio signal is 4 phases later! I! (hereinafter referred to as QPSK) circuit (12) and a PCM demodulation circuit (13), and a de-emphasis circuit (14) reproduces the original audio signal. Then, it is applied to the audio input terminal (15) of the television receiver (10). In this way, satellite broadcasting can be received.
以上のような衛星放送受信機において、QPSK回路(
12)は第2図のように構成され、音声信号の復調をア
ナログ処理していた。この従来のQPSK回路(12)
において、QPSK信号は乗算器(17) (18)、
L P F (19) (20)を通り、2値化器(2
1)(22)と位相差検出器(23)に送られる。位相
差検出器(23)ではQPSK信号の発生側の搬送波の
位相と、V CO(24)から発生する再生搬送波の位
相差を比較し、その差がOとなるようにV CO(24
)に制御信号を加える。このV CO(24)からの発
振信号は。In the satellite broadcasting receiver as described above, the QPSK circuit (
12) was constructed as shown in FIG. 2, and demodulated the audio signal using analog processing. This conventional QPSK circuit (12)
, the QPSK signal is passed through the multipliers (17) (18),
L P F (19) (20)
1) (22) and a phase difference detector (23). The phase difference detector (23) compares the phase of the carrier wave on the generation side of the QPSK signal and the phase difference of the reproduced carrier wave generated from the V CO (24), and adjusts the phase of the carrier wave on the V CO (24) so that the difference becomes O.
). The oscillation signal from this VCO (24) is.
一方の乗算器(17)に−90’移相器(25)を介し
て送られ。また他方の乗算器(18)にそのまま送られ
て入力したQPSK信号と乗算される。そして位相差が
次第にOになって、復調信号として2値化器(21)
(22)から出力する。なお、(26)はピットクロッ
ク再生回路である。It is sent to one multiplier (17) via a -90' phase shifter (25). It is also sent as is to the other multiplier (18) and multiplied by the input QPSK signal. Then, the phase difference gradually becomes O, and the demodulated signal is sent to the binarizer (21).
Output from (22). Note that (26) is a pit clock regeneration circuit.
「発明が解決しようとする課題」
しかるに、従来のQPSK回路(12)はすべてアナロ
グ信号で処理していたので、回路パラメータにばらつき
があること、動作がやや不安定であること、V CO(
24)からの出力は正弦波であるため一90°移相器(
25)での移相量に誤差が生じることなどの問題があっ
た。``Problem to be solved by the invention'' However, since the conventional QPSK circuit (12) processes all analog signals, there are variations in circuit parameters, somewhat unstable operation, and V CO (
Since the output from 24) is a sine wave, a 90° phase shifter (
25), there were problems such as an error occurring in the amount of phase shift.
本発明はQPSKの復調をディジタルで行うことによっ
て従来の問題点を解決するような回路を得ることを目的
とする。An object of the present invention is to obtain a circuit that solves the conventional problems by performing QPSK demodulation digitally.
「課題を解決するための手段」
本発明はQPSK入力端子に入力したQPSK信号を2
つに分岐し、それぞれ乗算器、LPF、2値化器を介し
て復調8力端子へ送るとともに、前記2つのLPFの出
力を位相検出器を介してVCOへ送り、このVCOの信
号を前記一方の乗算器には移相器を介して、また、他方
の乗算器にはそのまま送ることにより入力した搬送波と
再生搬送波の位相差がOとなるように制御するようにし
たものにおいて、前記QPSK入力端子と乗算器との間
にA/D変換器を介在し、前記乗算器およびLPFはデ
ィジタル形を用い、前記位相検出器とVCOとの間にD
/A変換器を介在してなるものである。"Means for Solving the Problem" The present invention provides two
The outputs of the two LPFs are sent to the VCO via a phase detector, and the signal of this VCO is sent to one of the two terminals via a multiplier, an LPF, and a binarizer. The QPSK input is controlled so that the phase difference between the input carrier wave and the reproduced carrier wave becomes O by sending it to one multiplier through a phase shifter and sending it as it is to the other multiplier. An A/D converter is interposed between the terminal and the multiplier, the multiplier and the LPF are of digital type, and a D converter is interposed between the phase detector and the VCO.
/A converter is interposed.
「作用」
QPSK入力端子に入力したQPSK信号をA/D変換
器でディジタル量に変換し、その信号はディジタル乗算
器とディジタルLPFを通過し。"Operation" The QPSK signal input to the QPSK input terminal is converted into a digital quantity by an A/D converter, and the signal passes through a digital multiplier and a digital LPF.
2値化器と位相差検出器に送られる。位相差検出器では
QPSK信号の発生側の搬送波の位相と、VCOより発
生する再生搬送波の位相差とを比較しその差がOとなる
ようにD/A変換した信号をvcoに加える。すなわち
、VCOはディジタル動作が困難であるため、アナログ
信号に変換して加える。VCOからは矩形波が出力する
が、これは実質的なディジタル信号であり、これが−9
0″の移相器を介し、また直接乗算器へ加えられてディ
ジタル処理される。The signal is sent to a binarizer and a phase difference detector. The phase difference detector compares the phase of the carrier wave on the generation side of the QPSK signal with the phase difference of the reproduced carrier wave generated by the VCO, and adds a D/A converted signal to the VCO so that the difference becomes O. That is, since it is difficult for a VCO to operate digitally, it is converted into an analog signal and added. A square wave is output from the VCO, but this is essentially a digital signal, which is -9
It is digitally processed via a 0'' phase shifter and directly to a multiplier.
「実施例」 以下、本発明の一実施例を第1図に基き説明する。"Example" An embodiment of the present invention will be described below with reference to FIG.
第2図の従来回路と異なる点は、QPSK入力端子(1
6)とディジタル形乗算器(27) (2g)の間に、
A/D変換器(31)を挿入し、また1乗算器(27)
(28)とL P F (29) (30)はそれぞ
れディジタル形を用い、さらに、位相差検出器(23)
とV CO(24)の間にD/A変換器(32)を介在
したことである。The difference from the conventional circuit shown in Figure 2 is that the QPSK input terminal (1
6) and the digital multiplier (27) (2g),
Insert A/D converter (31) and also 1 multiplier (27)
(28) and L P F (29) (30) each use a digital type, and furthermore, a phase difference detector (23) is used.
A D/A converter (32) is interposed between the VCO (24) and the VCO (24).
以上のような構成において、QPSK入力端子(16)
に入力したQPSK信号をA/D変換器(31)でディ
ジタル量に変換し、その信号はディジタル乗算器(27
) (28)とディジタルL P F (29) (3
0)を通過し、2値化器(21H22)と位相差検出器
(23)に送られる1位相差検出器(23)ではQPS
K信号の発生側の搬送波の位相と、VCO(24)より
発生する再生搬送波の位相差とを比較しその差がOとな
るようにD/A変換器(32)でアナログに変換した信
号をV CO(24)に加える。すなわち、VCO(2
4)はディジタル動作が困難であるため、アナログ信号
に変換して加える。V CO(24)からは矩形波が出
力するが、これは実質的なディジタル信号であり、これ
が−90°移相器(25)を介して一方のディジタル乗
算器(27)へ送られるとともに、直接他方のディジタ
ル乗算IG>(28)へ送られる。このディジタル乗算
器(27028)のデータが再びディジタルLP F
(29) (30)を介して位相検出器(23)で比較
され、D/A変換された制御信号をV CO(24)に
加える。In the above configuration, the QPSK input terminal (16)
The A/D converter (31) converts the input QPSK signal into a digital quantity, and the signal is sent to the digital multiplier (27).
) (28) and digital L P F (29) (3
0) and is sent to the binarizer (21H22) and the phase difference detector (23).
The phase of the carrier wave on the generation side of the K signal is compared with the phase difference of the reproduced carrier wave generated from the VCO (24), and the signal is converted into an analog signal by the D/A converter (32) so that the difference becomes O. Add to VCO (24). That is, VCO(2
4) is difficult to perform digitally, so it is converted into an analog signal and added. A rectangular wave is output from the V CO (24), which is essentially a digital signal, and is sent to one digital multiplier (27) via a -90° phase shifter (25). Directly to the other digital multiplier IG>(28). The data of this digital multiplier (27028) is again converted into digital LP F
(29) The phase detector (23) compares the control signal via (30) and applies the D/A converted control signal to the VCO (24).
この動作を位相差が0になるまで繰返えして2値化器(
21) (22)で2値化して復調出力として出力端子
(33) (34)からテレビ受信機(10)へ送られ
る。This operation is repeated until the phase difference becomes 0, and the binarizer (
21) It is binarized in (22) and sent as a demodulated output from the output terminals (33) and (34) to the television receiver (10).
前記実施例では、VCO(24)をアナログ形としたた
め位相検出器(23)の出力をD/A変換器(32)で
アナログに変換したが、V CO(24)をディジタル
形とした場合には、D/A変換器(32)を省略するこ
とができる。In the above embodiment, the VCO (24) is of analog type, so the output of the phase detector (23) is converted to analog by the D/A converter (32). However, when the VCO (24) is of digital type, In this case, the D/A converter (32) can be omitted.
「発明の効果」
本発明は上述のように構成したので以下のような効果を
有する。"Effects of the Invention" Since the present invention is configured as described above, it has the following effects.
(1)回路パラメータがディジタルであるためばらつき
がない。(1) Since the circuit parameters are digital, there are no variations.
(2)動作が安定する。(2) Operation becomes stable.
(3)搬送波再生のVCOの基本周波数を搬送波の4倍
にすることにより、−90°の移相器はディジタル的に
移相量を発生でき、この移相量の誤差がなくなる。(3) By making the fundamental frequency of the VCO for carrier wave regeneration four times that of the carrier wave, the -90° phase shifter can digitally generate a phase shift amount, eliminating errors in this phase shift amount.
第1図は本発明による4位相復調回路の一実施例を示す
ブロック図、第2図は従来の回路のブロック図、第3図
は一般的な衛星放送受信機のブロック図である。
(1)・・・放送衛星、(2)・・・パラボラアンテナ
、(3)・・・BSコンバータ、(4)・・・BSチュ
ーナ、(5)・・・選局回路、(6)・・・FM復調回
路、(7)・・・映像−音声分離回路、(8)・・・デ
エンファシス回路、(9)・・・エネルギー拡散信号除
去回路、(10)・・・テレビ受像機、(11)・・・
映像入力端子、(12)・・・4位相復調回路、(13
)・・、(14)・・・デエンファシス回路+ (tS
)・・・音声入力端子、(16)・・・QPSK入力端
子、 (17)(18)・・・乗算器、(19)(20
)・・・L P F 、 (21)(22)・・・2値
化器、(23)−・・位相差検出器、(24) ・V
C01(25) ・−・−90゜移相器、(26)・・
・ビットクロック再生回路、(27) (28)・・・
乗算器、(29) (30)・・・LPF、(31)・
・・A/D変換器、(32)・・・D/A変換器。FIG. 1 is a block diagram showing an embodiment of a four-phase demodulation circuit according to the present invention, FIG. 2 is a block diagram of a conventional circuit, and FIG. 3 is a block diagram of a general satellite broadcasting receiver. (1)... Broadcasting satellite, (2)... Parabolic antenna, (3)... BS converter, (4)... BS tuner, (5)... Tuning circuit, (6)... ... FM demodulation circuit, (7) ... video-audio separation circuit, (8) ... de-emphasis circuit, (9) ... energy diffusion signal removal circuit, (10) ... television receiver, (11)...
Video input terminal, (12)... 4-phase demodulation circuit, (13
)..., (14)... De-emphasis circuit + (tS
)... Audio input terminal, (16)... QPSK input terminal, (17) (18)... Multiplier, (19) (20
)...L P F , (21) (22)... Binarizer, (23) -... Phase difference detector, (24) ・V
C01(25) ・-・-90° phase shifter, (26)・・
・Bit clock regeneration circuit, (27) (28)...
Multiplier, (29) (30)...LPF, (31)
...A/D converter, (32)...D/A converter.
Claims (2)
に分岐し、それぞれ乗算器、LPF、2値化器を介して
復調出力端子へ送るとともに、前記2つのLPFの出力
を位相検出器を介してVCOへ送り、このVCOの信号
を前記一方の乗算器には移相器を介して、また、他方の
乗算器にはそのまま送ることにより入力した搬送波と再
生搬送波の位相差が0となるように制御するようにした
ものにおいて、前記QPSK入力端子と乗算器との間に
A/D変換器を介在し、前記乗算器およびLPFはディ
ジタル形を用い、前記位相検出器とVCOとの間にD/
A変換器を介在してなることを特徴とする4位相復調回
路。(1) The QPSK signal input to the input terminal of the QPS is branched into two and sent to the demodulation output terminal via a multiplier, an LPF, and a binarizer, respectively, and the outputs of the two LPFs are sent to a phase detector. By sending this VCO signal to one of the multipliers via a phase shifter and sending it as is to the other multiplier, the phase difference between the input carrier wave and the reproduced carrier wave becomes 0. In the control device, an A/D converter is interposed between the QPSK input terminal and the multiplier, the multiplier and the LPF are of digital type, and the control is performed between the phase detector and the VCO. niD/
A four-phase demodulation circuit characterized by interposing an A converter.
に分岐し、それぞれ乗算器、LPF、2値化器を介して
復調出力端子へ送るとともに、前記2つのLPFの出力
を位相検出器を介してVCOへ送り、このVCOの信号
を前記一方の乗算器には移相器を介して、また、他方の
乗算器にはそのまま送ることにより入力した搬送波と再
生搬送波の位相差が0となるように制御するようにした
ものにおいて、前記QPSK入力端子と乗算器との間に
A/D変換器を介在し、前記乗算器、LPFおよびVC
Oはディジタル形を用いてなることを特徴とする4位相
復調回路。(2) The QPSK signal input to the input terminal of the QPS is branched into two and sent to the demodulation output terminal via a multiplier, an LPF, and a binarizer, respectively, and the outputs of the two LPFs are sent to a phase detector. By sending this VCO signal to one of the multipliers via a phase shifter and sending it as is to the other multiplier, the phase difference between the input carrier wave and the reproduced carrier wave becomes 0. In the control device, an A/D converter is interposed between the QPSK input terminal and the multiplier, and the multiplier, the LPF and the VC
A four-phase demodulation circuit characterized in that O is a digital type.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1305098A JP2932290B2 (en) | 1989-11-24 | 1989-11-24 | 4 phase demodulation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1305098A JP2932290B2 (en) | 1989-11-24 | 1989-11-24 | 4 phase demodulation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03165149A true JPH03165149A (en) | 1991-07-17 |
JP2932290B2 JP2932290B2 (en) | 1999-08-09 |
Family
ID=17941080
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1305098A Expired - Lifetime JP2932290B2 (en) | 1989-11-24 | 1989-11-24 | 4 phase demodulation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2932290B2 (en) |
-
1989
- 1989-11-24 JP JP1305098A patent/JP2932290B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2932290B2 (en) | 1999-08-09 |
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