JPH0316118A - Formation of polycrystalline silicon film - Google Patents
Formation of polycrystalline silicon filmInfo
- Publication number
- JPH0316118A JPH0316118A JP6510290A JP6510290A JPH0316118A JP H0316118 A JPH0316118 A JP H0316118A JP 6510290 A JP6510290 A JP 6510290A JP 6510290 A JP6510290 A JP 6510290A JP H0316118 A JPH0316118 A JP H0316118A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline
- amorphous
- ion implantation
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 82
- 230000015572 biosynthetic process Effects 0.000 title 1
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 37
- 239000013078 crystal Substances 0.000 claims abstract description 23
- 238000005468 ion implantation Methods 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 17
- 239000007790 solid phase Substances 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 3
- 239000012071 phase Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 239000007787 solid Substances 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 description 13
- 239000007789 gas Substances 0.000 description 9
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- 229910000077 silane Inorganic materials 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000005465 channeling Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要］
多結晶Ｓｉ膜の堆積方法に関し、
平坦な表面と高い配同性を有する多結晶Ｓｉ膜を形戒す
ることを目的とし、
絶縁膜上に多結晶Ｓｉ膜を堆積する工程と、ついでこの
上に非晶質Ｓｉ膜を堆積する工程と、ついで熱処理を行
うことにより該非晶質Ｓｉ膜を固相戒長させるように構
戒するか、あるいは、絶縁膜上に多結晶Ｓｉ膜を堆積す
る工程と、ついで該多結晶Ｓｉ膜に対してイオン注入角
度を一定としかつイオン注入深さを該多結晶Ｓｉ膜の膜
厚と同一かあるいはより深くしたイオン注入を行うこと
により、該多結晶Ｓｉ膜を構戒する結晶粒のうち該イオ
ン注入角度の方向に面方位を有する結晶粒以外の結晶粒
を非晶質化する工程と、ついでこの上に非晶’７９ Ｓ
ｉ膜を堆積する工程と、ついで熱処理を行うことによ
り該非晶質ｓｉ膜を固相成長させるように構或するか、
あるいは、上記多結晶Ｓｉ膜の膜厚を４０〜１５０ｎｍ
の範囲とするように構或する。[Detailed Description of the Invention] [Summary] Regarding the method of depositing a polycrystalline Si film, the purpose of this method is to deposit a polycrystalline Si film on an insulating film, with the aim of forming a polycrystalline Si film having a flat surface and high conformity. A step of depositing an amorphous Si film on the insulating film, a step of depositing an amorphous Si film on the insulating film, and a heat treatment to make the amorphous Si film into a solid phase, or a step of depositing a polycrystalline Si film on the polycrystalline Si film, and then ion implantation into the polycrystalline Si film at a constant ion implantation angle and with an ion implantation depth equal to or deeper than the film thickness of the polycrystalline Si film. By performing this step, a step of amorphizing the crystal grains other than the crystal grains having a plane orientation in the direction of the ion implantation angle among the crystal grains forming the polycrystalline Si film, and then amorphous ' 79 S
The amorphous Si film is grown in a solid phase by depositing the i film and then performing heat treatment;
Alternatively, the thickness of the polycrystalline Si film is 40 to 150 nm.
It is designed to be within the range of .
本発明は、多結晶Ｓｉ膜の堆積方法に関する。 The present invention relates to a method of depositing a polycrystalline Si film.
多結晶Ｓｉ膜は、トランジスタのゲート電極や配線材料
、不純物の拡散源として用いられる他、これを酸化して
ＤＲＡＭのキャパシタ構戒材料としても用いられ、ＩＣ
の製造には不可欠の材料である。そのためＩＣの微細化
、特性の高度化に伴って表面の平坦性および特性の均一
性について、より一層の向上が望まれている。Polycrystalline Si films are used as transistor gate electrodes, wiring materials, and impurity diffusion sources, and are also used as DRAM capacitor structural materials by oxidizing them.
It is an essential material for the production of. Therefore, with the miniaturization of ICs and the advancement of their characteristics, further improvements in surface flatness and uniformity of characteristics are desired.
通常のＩＣ製造工程において多結晶Ｓｉ膜の形成は、常
圧ＣＶＤ法あるいは減圧ＣＶＤ法によって行われる。即
ち、常圧あるいは減圧（０．１〜Ｉ Ｔｏｒｒ）下にお
いて６００〜８００ ’Ｃの温度範囲でシランガス（Ｓ
ｉ｝Ｉ４）を熱分解させるものであり、様々な大きさ及
び面方位を有する結晶粒から戊っている。In a normal IC manufacturing process, a polycrystalline Si film is formed by normal pressure CVD or low pressure CVD. That is, silane gas (S
i}I4) is thermally decomposed and is formed from crystal grains having various sizes and plane orientations.
〔発明が解決しようとする課題］
ところが通常、多結晶Ｓｉ膜の表面には凹凸が生じてお
り、ＩＣ製造工程におけるパターニング精度を劣化させ
る原因となっている。また、多結晶Ｓｉの酸化膜は単結
晶Ｓｉの酸化膜に比べて一般にリーク電流が大きくかつ
絶縁耐圧が低いことが知られているが、これは、多結晶
Ｓｉ膜とその酸化膜の界面が多結晶Ｓｉ膜表面の凹凸形
状を反映して平坦でないこと、及び多結晶Ｓｉ膜を構或
する個々の結晶粒の面方位に依存してその酸化速度が異
なるため酸化膜厚が不均一となることに起因して、該酸
化膜中で局所的に電界集中が生じるためと考えられてい
る。[Problems to be Solved by the Invention] However, the surface of a polycrystalline Si film usually has irregularities, which causes deterioration of patterning accuracy in the IC manufacturing process. Furthermore, it is known that polycrystalline Si oxide films generally have larger leakage current and lower dielectric strength voltage than single-crystalline Si oxide films, but this is because the interface between the polycrystalline Si film and its oxide film is The oxide film thickness is uneven because it is not flat due to the uneven shape of the polycrystalline Si film surface, and the oxidation rate differs depending on the plane orientation of the individual crystal grains that make up the polycrystalline Si film. This is thought to be due to local electric field concentration occurring in the oxide film.
そこで本発明は、平坦な表面と高い配同性を有する多結
晶Ｓｉ膜を形戒することを目的とする。Therefore, an object of the present invention is to form a polycrystalline Si film having a flat surface and high conformality.
［課題を解決するための手段］
上記課題の解決は、絶縁膜上に多結晶Ｓｉ膜を堆積する
工程と、ついでこの上に非晶質Ｓｉ膜を堆積する工程ど
、ついで熱処理を行うことにより該非晶質Ｓｉ膜を固相
成長させることを特徴とする多結晶Ｓｉ膜の形成方法、
あるいは、絶縁膜上に多結晶Ｓｉ膜を堆積する工程と、
ついで該多結晶Ｓｉ膜に対してイオン注入角度を一定と
しかつイオン注入深さを該多結晶Ｓｉ膜の膜厚と同一か
あるいはより深くしたイオン注入を行うことにより、該
多結晶Ｓｉ膜を構戒する結晶粒のうち該イオン注入角度
の方向に面方位を有する結晶粒以外の結晶粒を非晶質化
する工程と、ついでこの上に非晶質Ｓｉ膜を堆積する工
程と、ついで熱処理を行うことにより該非晶質Ｓｉ膜を
固相戒長させることを特徴とする多結晶Ｓｉ膜の形成方
法、あるいは、上記多結晶Ｓｉ膜の膜厚が４０〜１５０
ｎｍの範囲であることを特徴とする上記多結晶Ｓｉ膜
の形成方法によって達或される。[Means for Solving the Problems] The above problems can be solved by performing heat treatment on the steps of depositing a polycrystalline Si film on the insulating film, and then depositing an amorphous Si film thereon. A method for forming a polycrystalline Si film, which comprises growing the amorphous Si film in a solid phase;
Alternatively, a step of depositing a polycrystalline Si film on the insulating film;
Next, the polycrystalline Si film is structured by performing ion implantation into the polycrystalline Si film at a constant ion implantation angle and with an ion implantation depth equal to or deeper than the film thickness of the polycrystalline Si film. A process of amorphizing crystal grains other than crystal grains having a plane orientation in the direction of the ion implantation angle among the crystal grains to be treated, a process of depositing an amorphous Si film thereon, and a heat treatment. A method for forming a polycrystalline Si film, characterized in that the amorphous Si film is made to have a solid phase by
This can be achieved by the method for forming a polycrystalline Si film characterized in that the film is in the nanometer range.
［作 用］
第１図（ａ）、（ｂ）を参照して本発明の原理を説明す
る。同図（ａ）に示したように基板１上の酸化ｆｆ！Ｊ
２に堆積された多結晶Ｓｉ膜３は様々な粒径及び面方位
を有する結晶粒により構成されているためその表面には
凹凸が生じている。そして、この上に非晶質Ｓｉ膜４を
堆積する際、非晶質Ｓｉ膜は等方的に付着するためその
表面の凹凸差は緩和されることが知られている（たとえ
ば特開昭６３−２３６３０９号公報）。これを熱処理す
ると、同図（ｂ）に示すように多結晶Ｓｉ膜３を構或す
る結晶粒が核となって非晶質Ｓｉ膜が固相戒長し、この
固相戒長面が図中６、７に示すように変化する。ところ
が固相成長では溶融によるＳｉ原子の移動がないため、
固相成長後も表面形状自体は変化しない。従って、凹凸
差の緩和された平坦な表面形状を保持した状態で非晶質
Ｓｉ膜が多結晶Ｓｉ膜５となる。[Operation] The principle of the present invention will be explained with reference to FIGS. 1(a) and (b). As shown in FIG. 1(a), oxidation ff! on the substrate 1 is shown. J
Since the polycrystalline Si film 3 deposited on the substrate 2 is composed of crystal grains having various grain sizes and plane orientations, its surface has irregularities. It is known that when an amorphous Si film 4 is deposited on this, the difference in surface unevenness is alleviated because the amorphous Si film is isotropically deposited (for example, in Japanese Patent Laid-Open No. 63 -236309). When this is heat-treated, the crystal grains constituting the polycrystalline Si film 3 serve as nuclei and the amorphous Si film becomes solid-phase elongated, as shown in FIG. It changes as shown in 6 and 7. However, in solid phase growth, there is no movement of Si atoms due to melting, so
The surface shape itself does not change even after solid phase growth. Therefore, the amorphous Si film becomes the polycrystalline Si film 5 while maintaining a flat surface shape with reduced unevenness.
また、よく知られているように、結晶粒を構戊する原子
のうち、ある一定の面方位を構或する原子は、その一定
の面方位に対応した方向、いわゆるチャネリングアング
ルから入射した粒子に対する散乱確率が非常に小さくな
る。従って、上記一定の面方位を構或する原子以外の原
子を入射粒子によって散乱させその配置を変えると、上
記一定の面方位を有する結晶粒のみが残り他の面方位を
有する結晶粒は破壊されてしまう。In addition, as is well known, among the atoms constituting a crystal grain, atoms with a certain plane orientation will react to particles incident from a direction corresponding to the certain plane orientation, the so-called channeling angle. The probability of scattering becomes very small. Therefore, if atoms other than those with the above-mentioned fixed plane orientation are scattered by incident particles and their arrangement changed, only the crystal grains with the above-mentioned fixed plane orientation will remain, and the crystal grains with other plane orientations will be destroyed. I end up.
そこで多結晶Ｓｉ膜３に対し、イオン注入角度を一定に
保ち、かつイオン注入深さをこの多結晶Ｓｉ膜３の膜厚
と同一かあるいはより深くしたイオン注入を行うことに
より、上記イオン注入角度をチャネリングアングルとす
る一定の面方位以外の面方位を有する結晶粒を全て非晶
質化することができる。そこでこの上に非晶質Ｓｉ４を
堆積してその表面の凹凸を緩和した後に熱処理を行って
固相成長させると、上記一定の面方位を持つ結晶粒のみ
が成長ずることとなる。従って、平坦な表面を有すると
ともに配同性の高い多結晶Ｓｉ膜５を得ることができる
。Therefore, by performing ion implantation into the polycrystalline Si film 3 while keeping the ion implantation angle constant and making the ion implantation depth the same as or deeper than the film thickness of the polycrystalline Si film 3, it is possible to It is possible to amorphize all crystal grains having a plane orientation other than a certain plane orientation with a channeling angle of . Therefore, if amorphous Si4 is deposited on top of this to soften its surface irregularities and then subjected to heat treatment to cause solid phase growth, only crystal grains having the above-described fixed plane orientation will grow. Therefore, it is possible to obtain a polycrystalline Si film 5 having a flat surface and a high degree of orientation.
先に述べたように、多結晶Ｓｉ膜３上に非晶質Ｓｉ膜４
を堆積することによってこの多結晶Ｓｉ膜３の表面の凹
凸差は緩和される。しかしながら、非晶質Ｓｉ膜４が薄
い場合には、当然のことながらその凹凸差の緩和の程度
は小さい。従って素子製作上、非晶質Ｓｉ膜４の堆積膜
厚が制限される場合には、非晶質Ｓｉ膜４を堆積する前
の多結晶Ｓｉ膜３の表面の凹凸差自体をある限度以下に
抑えておくことが必要となる。As mentioned earlier, the amorphous Si film 4 is formed on the polycrystalline Si film 3.
By depositing the polycrystalline Si film 3, the unevenness on the surface of the polycrystalline Si film 3 is alleviated. However, when the amorphous Si film 4 is thin, the degree of relaxation of the unevenness difference is naturally small. Therefore, when the thickness of the deposited amorphous Si film 4 is limited due to device fabrication, the unevenness of the surface of the polycrystalline Si film 3 before depositing the amorphous Si film 4 must be kept below a certain limit. It is necessary to keep it in check.
第２図は、減圧ＣＶＤ法により堆積した多結晶Ｓｉ膜の
膜厚とその表面の凹凸差との関係を示す実験データであ
る。常圧ＣＶＤ法を用いた場合にもほぼ同様な結果が得
られる。同図に見られるように、凹凸差は多結晶Ｓｉ膜
の膜厚とともに減少する。FIG. 2 shows experimental data showing the relationship between the thickness of a polycrystalline Si film deposited by low pressure CVD and the difference in surface roughness. Almost similar results can be obtained when atmospheric pressure CVD is used. As seen in the figure, the difference in unevenness decreases with the thickness of the polycrystalline Si film.
多結晶Ｓｉ膜の膜厚がおよそ５０ｎｍ以下となったとき
に凹凸差が逆に増大するのは、結晶粒が鳥状に戒長ずる
ためと考えられる。The reason why the unevenness difference increases when the thickness of the polycrystalline Si film becomes approximately 50 nm or less is considered to be because the crystal grains lengthen in a bird-like manner.
一方、本発明者は、表面の凹凸差が１５ｎｍより小さい
多結晶Ｓｉ膜の上に非晶質Ｓｉ膜を堆積しこれを熱処理
して多結晶Ｓｉ膜化した場合、この多結晶Ｓｉ膜の酸化
膜は非晶質Ｓｉ膜の膜厚にかかわらず絶縁耐圧が高くか
つリーク電流の小さなものとなることを実験的に確かめ
た。第２図から明らかなように、凹凸差が１５ｎａ＋以
下となるような多結晶Ｓｉ膜の膜厚範囲は４０〜１５０
ｎｍである。即ち、上記範囲の膜厚を有する多結晶Ｓｉ
膜に対しては、この上に堆積された非晶質Ｓｉ膜の膜厚
が薄い場合にも、酸化に対して良好な特性を示す多結晶
Ｓｉ膜を得ることができる。On the other hand, the present inventor has discovered that when an amorphous Si film is deposited on a polycrystalline Si film with a surface unevenness difference of less than 15 nm and is heat-treated to form a polycrystalline Si film, the polycrystalline Si film is oxidized. It has been experimentally confirmed that the film has high dielectric strength and low leakage current regardless of the thickness of the amorphous Si film. As is clear from Figure 2, the thickness range of the polycrystalline Si film for which the unevenness difference is 15 na+ or less is 40 to 150 nm.
It is nm. That is, polycrystalline Si having a film thickness within the above range
As for the film, even if the thickness of the amorphous Si film deposited thereon is small, a polycrystalline Si film exhibiting good oxidation resistance can be obtained.
本発明の第１の実施例について第３図（ａ）〜（Ｃ）を
参照して説明する。同図（ａ）に示すようにＳｉｉ板ｌ
上に酸化膜２を形威した後、この上に減圧ＣＶＤ法によ
り成長ガスをシランガス（ＳｉＨ４）とし威長温度を６
２５゜Ｃとして１５０ ｎｓ＋の膜厚の多結晶Ｓｉ膜３
を形成する。次いで同図（ハ）に示すように減圧ＣＶＤ
法により非晶質Ｓｉ膜４を１５０ ｎｍ形成する。成長
ガスをシランガス（ＳｉＨ．）、戒長温度を５５０″Ｃ
とした。A first embodiment of the present invention will be described with reference to FIGS. 3(a) to 3(C). As shown in figure (a), Sii plate l
After forming an oxide film 2 on top, a low-pressure CVD method is used to grow the oxide film 2 using silane gas (SiH4) as the growth gas and the growth temperature is 6.
Polycrystalline Si film 3 with a film thickness of 150 ns+ at 25°C
form. Next, as shown in the same figure (c), low pressure CVD
An amorphous Si film 4 with a thickness of 150 nm is formed by the method. The growth gas was silane gas (SiH.), and the temperature was 550″C.
And so.
次いで同図（Ｃ）に示すように窒素ガス雰囲気中で９０
０゜Ｃ、１時間の熱処理により固相戒長を行わせること
により（１１０）配向し凹凸の小さな清らかな表面を有
する多結晶Ｓｉ膜５が得られた。Then, as shown in the same figure (C), the
A polycrystalline Si film 5 having a (110) orientation and a clean surface with small irregularities was obtained by heat treatment at 0° C. for 1 hour to induce solid phase modification.
次に本発明の第２の実施例について第４図（ａ）〜（Ｃ
）を参照して説明する。同図（ａ）に示すようにＳｉ基
板１１上に酸化膜１２を形威した後、この上に減圧ＣＶ
Ｄ法により威長ガスをシランガス（ＳｉＨｍ）とし成長
温度を７００゜Ｃとして１５０ ｎｍの膜厚の多結晶Ｓ
ｉ膜１３を威長させる。戒長温度を７００’Ｃとした場
合、多結晶Ｓｉ膜１３は（１００）面と（１１０）面を
有する結晶粒を比較的多く含むようになる。次いで、該
多結晶Ｓｉ膜ｌ３に対して注入角度４５゜でＳｉイ矛ン
を打ち込む。このときの加速電圧を４０ｋｅＶとし、ド
ーズ量を１×・１０”ｃｍ−”とした。上記注入角度４
５゜は＜１１０＞方位に対するチャネリングアングルと
なっている。従って上記イオン注入により、＜１１０＞
以外の面方位を有する結晶粒は非晶質化される。Next, regarding the second embodiment of the present invention, FIGS. 4(a) to (C)
). As shown in the figure (a), after forming an oxide film 12 on a Si substrate 11, a low-pressure CV
Polycrystalline S with a film thickness of 150 nm was grown using the D method using silane gas (SiHm) as the SiH gas and growing at a growth temperature of 700°C.
Make the i-film 13 more imposing. When the temperature is set to 700'C, the polycrystalline Si film 13 contains relatively many crystal grains having (100) and (110) planes. Next, a Si implant is implanted into the polycrystalline Si film 13 at an implantation angle of 45°. The accelerating voltage at this time was 40 keV, and the dose was 1×·10"cm.sup.-". Above injection angle 4
5° is the channeling angle with respect to the <110> direction. Therefore, by the above ion implantation, <110>
Crystal grains having other plane orientations are amorphized.
次いで同図（ｂ）に示すように減圧ＣＶＤ法により非晶
質Ｓｉ膜ｌ４を形成する。戒長ガスをシランガス、成長
温度を５５０゜Ｃとした。次いで同図（Ｃ）に示すよう
に窒素ガス雰囲気中で９００゜ｃ，１時間の熱処理によ
り固相成長を行わせた結果、強＜ ＜１１０＞配向し表
面の滑らかな多結晶Ｓｉ膜１５が得られた。Next, as shown in FIG. 2(b), an amorphous Si film 14 is formed by low pressure CVD. The Kaicho gas was silane gas, and the growth temperature was 550°C. Next, as shown in the same figure (C), solid phase growth was performed by heat treatment at 900°C for 1 hour in a nitrogen gas atmosphere, resulting in a polycrystalline Si film 15 with a strong <<110> orientation and a smooth surface. Obtained.
上記第２の実施例において、酸化膜１２上に多結晶Ｓｉ
膜ｌ３を成長させ、続いて非晶１ｉ Ｓ ｉ膜１４を形
威した後に該非晶質Ｓｉ膜１４を通して下地の多結晶Ｓ
ｉ膜１３にイオン注入を行っても同様な結果が得られる
。また、イオン注入に用いる原子として上記Ｓｉ原子以
外にリン、ボロン、砒素等の■族あるいはＶ族元素を用
いることもできる。この場合には、該イオン注入によっ
て多結晶Ｓｉ膜の配同性を高くすることができるととも
に、その比抵抗を下げ導電型を任意に設定することがで
きる。In the second embodiment, polycrystalline Si is formed on the oxide film 12.
After growing the film 13 and subsequently forming the amorphous 1i Si film 14, the underlying polycrystalline S is grown through the amorphous Si film 14.
Similar results can be obtained by implanting ions into the i-film 13. Further, as atoms used for ion implantation, in addition to the above-mentioned Si atoms, group II or group V elements such as phosphorus, boron, arsenic, etc. can also be used. In this case, by the ion implantation, it is possible to increase the distribution property of the polycrystalline Si film, and at the same time, it is possible to lower the specific resistance and set the conductivity type arbitrarily.
次に、本発明の第３の実施例について第５図を参照して
説明する。同図は本発明に係る方法を用いて製作したキ
ャパシタを有するメモリセルの断面図を示したものであ
り、２ｌはＳｉ基板、２２はフィールド酸化膜、２３は
多結晶Ｓｉ層からなるワード線、２４はＣＶＯ酸化膜か
らなる絶縁膜、２５は拡散層、２６は多結晶Ｓｉ膜から
なる下部電極、２７は多結晶Ｓｉ酸化膜からなるキャパ
シタ絶縁膜、２日は多結晶Ｓｉ膜からなる上部電極、２
９はＣＶＤ酸化膜からなる眉間絶縁膜、３０は多結晶Ｓ
ｉ膜からなるビット線電極、３ｌはＡｔ膜からなるビッ
ト線である。Next, a third embodiment of the present invention will be described with reference to FIG. The figure shows a cross-sectional view of a memory cell having a capacitor manufactured using the method according to the present invention, in which 2l is a Si substrate, 22 is a field oxide film, 23 is a word line made of a polycrystalline Si layer, 24 is an insulating film made of a CVO oxide film, 25 is a diffusion layer, 26 is a lower electrode made of a polycrystalline Si film, 27 is a capacitor insulating film made of a polycrystalline Si oxide film, and 2nd is an upper electrode made of a polycrystalline Si film. ,2
9 is a glabellar insulating film made of a CVD oxide film, and 30 is a polycrystalline S.
The bit line electrode 3l is made of an I film, and the bit line 3l is made of an At film.
同図において、キャパシタは下部電極２６、キャパシタ
絶縁膜２７、上部電極２８から戒っており、キャパシタ
絶縁膜２７に対しては、蓄積容量を確保するためにその
膜厚を１０ｎｍとしかつ５ ＭＶ／Ｃｍ以上の耐圧とす
ることが要求される。このような要求を満たすため、キ
ャパシタは以下のようにして形成する。In the figure, the capacitor is composed of a lower electrode 26, a capacitor insulating film 27, and an upper electrode 28. The capacitor insulating film 27 has a film thickness of 10 nm to ensure storage capacity and a 5 MV/ It is required to have a breakdown voltage of Cm or more. In order to meet such requirements, a capacitor is formed as follows.
まず、第１の実施例で述べた方法と同様の方法を用いる
ことにより、下部電極となる膜厚１２０ｎｍの多結晶Ｓ
ｉ膜、続いてキャパシタ絶縁膜となる膜厚１０ｎｓの非
晶質Ｓｉ膜を全面に堆積し、この上にレジストパターン
を形成し、これをマスクにして３亥多結晶Ｓｉ膜および
該非晶質Ｓｉ膜を選択的にエッチング・除去する。つい
で窒素ガス雰囲気中で、９００℃、１０分間の熱処理を
行って該非晶質Ｓｉ膜を固相戒長させる．ついで、これ
らの非晶質Ｓｉ膜および側面の多結晶Ｓｉ膜を熱酸化し
てキャパシタ絶縁膜２７とする。その後、通常の工程に
従ってこの上に多結晶Ｓｉ膜を堆積し、上記キャパシタ
絶縁膜２７を覆うようにパターニングして上部電極２８
とする。First, by using a method similar to that described in the first example, a polycrystalline S film with a thickness of 120 nm, which will become the lower electrode, is prepared.
A 10 ns thick amorphous Si film, which will become a capacitor insulating film, is deposited on the entire surface of the i film, and a resist pattern is formed on this, and using this as a mask, the polycrystalline Si film and the amorphous Si film are Selectively etch and remove the film. Next, heat treatment is performed at 900° C. for 10 minutes in a nitrogen gas atmosphere to transform the amorphous Si film into a solid state. Then, these amorphous Si films and the polycrystalline Si films on the side surfaces are thermally oxidized to form a capacitor insulating film 27. Thereafter, a polycrystalline Si film is deposited thereon according to a normal process, and is patterned to cover the capacitor insulating film 27 to form an upper electrode 28.
shall be.
なお、下部電極２６となる多結晶ｓｉを堆積した後、非
晶質Ｓｉ膜を堆積する前にイオン注入を行うこともでき
る。Note that ion implantation can also be performed after depositing the polycrystalline Si that will become the lower electrode 26 but before depositing the amorphous Si film.
次に、以上のようにして製作したキャパシタが要求性能
を満たしているか否かについて述べる．第６図は、下部
電極２６となる多結晶Ｓｉ膜の表面の凹凸差によってキ
ャパシタ絶縁膜２７の耐圧がどのように変化するかを非
晶質Ｓｉ膜厚が１０ｎｍの場合について示した実験デー
タである。同図に見られるように、多結晶Ｓｉ膜の表面
の凹凸差が１５ ｎｍ以下であれば絶縁耐圧は５ ＭＶ
／ｃｍ以上となって要求性能を満たすことになる。この
条件を満たすために必要な多結晶Ｓｉ膜の膜厚は第２図
から明らかなように４０〜１５０ ｎｍであり、上記第
３の実施例で用いた多結晶Ｓｉ膜の膜厚は１２０ｎｍで
あるので、この条件を満たしており、良好な耐圧が得ら
れることがわかる。Next, we will discuss whether the capacitor manufactured as described above satisfies the required performance. FIG. 6 shows experimental data showing how the withstand voltage of the capacitor insulating film 27 changes depending on the unevenness of the surface of the polycrystalline Si film that becomes the lower electrode 26 when the amorphous Si film thickness is 10 nm. be. As seen in the figure, if the difference in surface roughness of the polycrystalline Si film is 15 nm or less, the dielectric breakdown voltage is 5 MV.
/cm or more, which satisfies the required performance. The thickness of the polycrystalline Si film required to satisfy this condition is 40 to 150 nm, as is clear from Fig. 2, and the thickness of the polycrystalline Si film used in the third example above is 120 nm. Therefore, it can be seen that this condition is satisfied and a good withstand voltage can be obtained.
以上述べたように本発明によれば、凹凸差の小さな表面
と高い配向性を有する多結晶Ｓｉ膜を形成することが可
能となり、ＩＣ製造におけるバターニング精度の向上あ
るいは該多結晶Ｓｉ膜を酸化した膜の絶縁耐圧向上、リ
ーク電流低減を図ることができ、ＩＣの特性向上に有益
である。As described above, according to the present invention, it is possible to form a polycrystalline Si film having a surface with a small unevenness difference and a high degree of orientation. It is possible to improve the dielectric strength of the film and reduce leakage current, which is beneficial for improving the characteristics of the IC.
第１図（ａ）、い）は本発明の原理説明図、第２図は多
結晶Ｓｉ膜表面の凹凸差の膜厚依存性を示す実験データ
、
第３図（ａ）〜（Ｃ）は第１の実施例を示す断面図、第
４図（ａ）〜（Ｃ）は第２の実施例を示す断面図、第５
図は第３の実施例を示す断面図、
第６図は絶縁耐圧の多結晶Ｓｉ膜表面凹凸差依存性を示
す実験データ、
である。
図において、
１ふｌ１、２１はＳｉ基板、
２、１２は酸化膜、
３、１３は多結晶Ｓｉ膜、
４、１４は非晶質Ｓｉ膜、
５、１５は固相成長した多結晶Ｓｉ膜、６、７は固相成
長面、
２２はフィールド酸化膜、
２３はワード線、
２４は絶縁膜、
２５は拡散層、
２６は下部電極、
２７はキャパシタ絶縁膜、
２８は上部電極、
２９は眉間絶縁膜、
３０はビット線電極、
３１はビット線、
である。
｛シ圭吉品ＳＣ月更Ａ享
（ｎｍ）
卆邦晶Ｓｉ腋表面の凹凸差の躾厚
ｎ辷存・ト生左ブ丁；３ｔ実ｊ〜哄；゛ラ゛ニータ第
Ｚ
図
オく矛５５日の原王里段巴口月 ｉ
＃＝１
２デ）１σｒフさ■二春ｈ≦ｉイタ゛Ｊ乞示ずレり′「
亡買コＥ≧コ↓
↓
↓
↓
秦Ｚの定泡伊長末▼祈面図
秦
４
回
２＋
第３の突絶例とホ寸訪勿記
第５
起Figures 1 (a) and (i) are diagrams explaining the principle of the present invention, Figure 2 is experimental data showing the film thickness dependence of the unevenness difference on the surface of a polycrystalline Si film, and Figures 3 (a) to (C) are 4(a) to (C) are sectional views showing the second embodiment.
The figure is a cross-sectional view showing the third embodiment, and FIG. 6 is experimental data showing the dependence of dielectric strength on the unevenness difference on the surface of a polycrystalline Si film. In the figure, 1fl1 and 21 are Si substrates, 2 and 12 are oxide films, 3 and 13 are polycrystalline Si films, 4 and 14 are amorphous Si films, and 5 and 15 are solid phase grown polycrystalline Si films. , 6 and 7 are solid phase growth surfaces, 22 is a field oxide film, 23 is a word line, 24 is an insulating film, 25 is a diffusion layer, 26 is a lower electrode, 27 is a capacitor insulating film, 28 is an upper electrode, 29 is between the eyebrows 30 is a bit line electrode; 31 is a bit line; {Shi Keikichi product SC Tsukisara A (nm) 卆 卆 煭子 Si armpit surface unevenness difference thickness n 辷 Existence / To raw left button; 3t actual j ~ song; 55th Hara no Ridan Tomoe Kuchi month i # = 1 2 de) 1σr Fusa■ Niharu h≦i Ita゛J without any indication'
Bad purchase Ko E ≧ Ko↓ ↓ ↓ ↓ Hata Z's Teiwa Inagasue▼Prayer mask Hata 4th episode 2+ 3rd sudden example and Hosunbo Muki 5th occurrence
Claims (3)
工程と、ついでこの上に非晶質Ｓｉ膜（４）を堆積する
工程と、ついで熱処理を行うことにより該非晶質Ｓｉ膜
（４）を面相成長させることを特徴とする多結晶Ｓｉ膜
の形成方法。(1) A step of depositing a polycrystalline Si film (3) on an insulating film (2), a step of depositing an amorphous Si film (4) on this, and then a heat treatment to make the amorphous A method for forming a polycrystalline Si film, which comprises growing the Si film (4) by plane phase growth.
工程と、ついで該多結晶Ｓｉ膜（３）に対して、イオン
注入角度を一定としかつイオン注入深さを該多結晶Ｓｉ
膜（３）の膜厚と同一かあるいはより深くしたイオン注
入を行うことにより、該多結晶Ｓｉ膜（３）を構成する
結晶粒のうち該イオン注入角度の方向に面方位を有する
結晶粒以外の結晶粒を非晶質化する工程と、ついでこの
上に非晶質Ｓｉ膜（４）を堆積する工程と、ついで熱処
理を行うことにより該非晶質Ｓｉ膜（４）を固相成長さ
せることを特徴とする多結晶Ｓｉ膜の形成方法。(2) A step of depositing a polycrystalline Si film (3) on the insulating film (2), and then implanting the ions into the polycrystalline Si film (3) at a constant angle and implanting the ion depth at a constant angle. Crystal Si
By performing ion implantation to a thickness equal to or deeper than that of the film (3), the crystal grains constituting the polycrystalline Si film (3) other than the crystal grains having a plane orientation in the direction of the ion implantation angle are removed. a step of amorphizing the crystal grains, a step of depositing an amorphous Si film (4) thereon, and then a heat treatment to grow the amorphous Si film (4) in a solid phase. A method for forming a polycrystalline Si film, characterized by:
範囲であることを特徴とする請求項（１）又は請求項（
２）記載の多結晶Ｓｉ膜の形成方法。(3) Claim (1) or claim (3) characterized in that the film thickness of the polycrystalline Si film (3) is in the range of 40 to 150 nm.
2) Method of forming a polycrystalline Si film as described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6510290A JPH0316118A (en) | 1989-03-15 | 1990-03-15 | Formation of polycrystalline silicon film |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1-62803 | 1989-03-15 | ||
| JP6280389 | 1989-03-15 | ||
| JP6510290A JPH0316118A (en) | 1989-03-15 | 1990-03-15 | Formation of polycrystalline silicon film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0316118A true JPH0316118A (en) | 1991-01-24 |
Family
ID=26403862
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6510290A Pending JPH0316118A (en) | 1989-03-15 | 1990-03-15 | Formation of polycrystalline silicon film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0316118A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6586706B2 (en) | 2001-08-18 | 2003-07-01 | Trumpf Werkzeugmaschinen Gmbh + Co. Kg | Laser machine tool with beam guide |
-
1990
- 1990-03-15 JP JP6510290A patent/JPH0316118A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6586706B2 (en) | 2001-08-18 | 2003-07-01 | Trumpf Werkzeugmaschinen Gmbh + Co. Kg | Laser machine tool with beam guide |
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