JPH03132078A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH03132078A JPH03132078A JP1268926A JP26892689A JPH03132078A JP H03132078 A JPH03132078 A JP H03132078A JP 1268926 A JP1268926 A JP 1268926A JP 26892689 A JP26892689 A JP 26892689A JP H03132078 A JPH03132078 A JP H03132078A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- silicon film
- silicon
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 24
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 14
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 14
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 7
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 5
- 239000013078 crystal Substances 0.000 claims abstract description 4
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims abstract description 3
- 239000011574 phosphorus Substances 0.000 claims description 19
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 239000007789 gas Substances 0.000 claims description 14
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 10
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 9
- 229910052786 argon Inorganic materials 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 5
- 239000012298 atmosphere Substances 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 239000002994 raw material Substances 0.000 claims description 3
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 229910052754 neon Inorganic materials 0.000 claims description 2
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 15
- 229910052710 silicon Inorganic materials 0.000 claims 15
- 239000010703 silicon Substances 0.000 claims 15
- 239000002245 particle Substances 0.000 claims 1
- VEDJZFSRVVQBIL-UHFFFAOYSA-N trisilane Chemical compound [SiH3][SiH2][SiH3] VEDJZFSRVVQBIL-UHFFFAOYSA-N 0.000 claims 1
- 229910052681 coesite Inorganic materials 0.000 abstract description 9
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 9
- 229910052682 stishovite Inorganic materials 0.000 abstract description 9
- 229910052905 tridymite Inorganic materials 0.000 abstract description 9
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000004913 activation Effects 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 229910007264 Si2H6 Inorganic materials 0.000 abstract 1
- 238000002425 crystallisation Methods 0.000 abstract 1
- 230000008025 crystallization Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 8
- 239000003085 diluting agent Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 239000012300 argon atmosphere Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
本発明は半導体装置及びその製造方法に係り。
特に高耐圧、高信頼性を有するＭＯＳ型半導体装置およ
びその製造方法に関する。
［従来の技術］
今日のＬＳＩの発展をささえてきた技術の一つに、多結
晶シリコン（Ｓｉ）電極・配線形成技術がある。多結晶
Ｓｉ膜は、膜堆積直後の状態では、極めて抵抗が高いた
め、その後の工程で、イオン打込み法や熱拡散法により
不純物をドーピングし、導電性を得ている−０
ＭＯ５型不揮発性メモリ等では、上記方法により形成し
た第１の多結晶Ｓｉ膜の表面を熱酸化して二酸化シリコ
ン（Ｓｉｎ、）から成るｋｎ膜を形成し、更にこの絶縁
膜上に、第２の多結晶Ｓｉ膜を第１の多結晶Ｓｉ膜と同
様の方法で形成して、トランジスタやキャパシタを構成
している。この種の半導体装置の製造方法に関連するも
のとじては、電子情報通信学会技術研究報告第１８４巻
、１９８５年、第４３頁から４８頁が挙げられる。
［発明が解決しようとする課題］
しかし、上記従来技術により形成した多結晶Ｓｉの熱酸
化膜の絶縁耐圧は、基板単結晶Ｓｉの熱酸化膜のそれに
比べて著しく劣るという問題があった。これは、以下の
２つの理由によると考えられている。
（Ｄ多結晶Ｓｉ／５ｉｎ２界面に存在する凹凸での電界
集中。
膜堆積後の多結晶Ｓｉの表面には、多数の凹凸が存在す
る。この凹凸に局所的に電界が集中する結果、Ｓ ｉ
Ｏ，膜の絶縁破壊が起こる。更に、この凹凸に起因して
、多結晶Ｓｉが酸化されずにＳｉＯ２膜中に取り残され
ることもあり、電流漏洩の原因となる。
この問題を解決するために、例えば、Ｓｉ膜の堆積を５
５×１０２０Ｃから５７５℃の範囲という従来より低温
で行ない、膜堆積時のＳｉ膜の状態を非晶質とすること
により、Ｓｉ膜表面の凹凸を低減する方法も提案されて
いる。しかし、多結晶Ｓ１膜の表面を平滑にしただけで
は、高い絶縁耐圧は得られなかった。
■不純物の酸化膜中への取り込み。
多結晶Ｓｉ膜中の不純物、特に、結晶粒界に偏析してい
た不純物が、酸化の際にＳｉＯ□中に取り込まれる結果
、準位が生じ、漏洩電流が増大する。
本発明の目的は、単結晶Ｓｉ基板上に形成した熱酸化膜
と同等の高い絶縁耐圧を有する酸化膜を、多結晶Ｓｉ膜
上に形成する方法を提供することにある。The present invention relates to a semiconductor device and a method for manufacturing the same. In particular, the present invention relates to a MOS type semiconductor device having high breakdown voltage and high reliability, and a method for manufacturing the same. [Prior Art] One of the technologies that has supported the development of today's LSI is polycrystalline silicon (Si) electrode/wiring formation technology. Polycrystalline Si films have extremely high resistance immediately after film deposition, so in subsequent steps, impurities are doped using ion implantation or thermal diffusion to obtain conductivity.-0 MO5 nonvolatile memory et al., the surface of the first polycrystalline Si film formed by the above method is thermally oxidized to form a kn film made of silicon dioxide (Sin), and a second polycrystalline Si film is further formed on this insulating film. is formed by the same method as the first polycrystalline Si film to constitute a transistor or a capacitor. Related to this type of semiconductor device manufacturing method, there can be mentioned IEICE Technical Research Report, Vol. 184, 1985, pages 43 to 48. [Problems to be Solved by the Invention] However, there was a problem in that the dielectric strength of the thermally oxidized film of polycrystalline Si formed by the above-mentioned conventional technique was significantly inferior to that of the thermally oxidized film of single-crystalline Si on the substrate. This is thought to be due to the following two reasons. (D Electric field concentration on the unevenness existing at the polycrystalline Si/5in2 interface. There are many unevenness on the surface of polycrystalline Si after film deposition. As a result of the electric field being locally concentrated on these unevenness, the Si
O, dielectric breakdown of the film occurs. Further, due to the unevenness, polycrystalline Si may be left behind in the SiO2 film without being oxidized, causing current leakage. To solve this problem, for example, the deposition of a Si film was
A method has also been proposed in which the unevenness of the Si film surface is reduced by performing the process at a lower temperature than conventionally in the range of 5×10 20 C to 575° C. and making the Si film in an amorphous state during film deposition. However, simply by smoothing the surface of the polycrystalline S1 film, a high dielectric strength voltage could not be obtained. ■Incorporation of impurities into the oxide film. Impurities in the polycrystalline Si film, particularly impurities segregated at grain boundaries, are incorporated into SiO□ during oxidation, resulting in generation of levels and an increase in leakage current. An object of the present invention is to provide a method for forming an oxide film on a polycrystalline Si film, which has a dielectric strength as high as that of a thermal oxide film formed on a single-crystal Si substrate.
【課題を解決するための手段］
上記目的は以下の構成。
（１）第１のＳｉ膜を、不純物をドーピングしながら堆
積する、
（２）第１のＳｉ膜の堆積温度を５５０℃以下とし、非
晶質状態で行なう。
（３）第１のＳｉ膜中の不純物濃度を、８Ｘ１０２ｆｌ
Ｃ「３以下とする、
ことにより達成される。
【作用】
上記製造方法によれば、第１のＳｉ膜とＳｉＯ２膜との
界面、及びＳ ｉ Ｏ２膜と第２のＳｉ膜の界面の凹凸
は５ｎｍ以下となり、極めて平滑となる。
従って、従来技術で生じていた、多結晶Ｓｉ膜の凹凸に
起因した局所的な電界集中がない。更に、本Ｓｉ膜の結
晶粒径は従来の多結晶Ｓｉ膜の約１０倍と大きいうえ、
不純物をドーピングしながら膜を堆積しているので、粒
界に偏析する不純物の濃度が小さい。従って、酸化によ
りＳ ｉ Ｏ２膜中に取り込まれる不純物の量が低減さ
れる。よって、高い絶縁耐圧を有する多結晶５ｉ−３ｉ
ｎ、−多結晶Ｓｉ構造を形成することが可能となる。
【実施例１
実施例１
まず、第２図を用いて、本発明の第一の実施例につき詳
細に説明する。本実施は以下の手順で作成した。
まず、抵抗率０．１ΩＱｍ、面方位（１００）のｎ型Ｓ
ｉ基板１０１の表面に、周知の選択酸化技術によりフィ
ールド酸化膜１０２を形成した。
次いで、第１のＳｉ膜１０３を、原料ガスにジシラン（
ｓｘａＨａ）とフォスフイン（ＰＨ，）を用い、減圧化
学気相成長法（ＬＰＣＶＤ法）により、リンをドーピン
グしながら５２５℃で２００ｎｍ堆積した。Ｓｉ膜１０
３は、膜堆積直後の状態は非晶質である。
Ｓｉ膜１０３の堆積に際しては、窒素を希釈ガスとして
用いた。これは、ＰＨ，の流量が小さいため、希釈ガス
を用いることにより、その制御を容易とするためである
。更に、希釈ガスを用いると、同一バッチ四のウェーハ
間の膜厚・濃度の均一性が向上するという効果もある。
希釈ガスとしては、窒素の他に、ヘリウム、アルゴン等
の不活性ガスを用いてもよい。
このＳｉ膜１０３を、周知のりソグラフイ技術とドライ
エツチング技術により加工し、第１の電極とした。
次いで、Ｓｉ膜表面に、熱酸化法により２０ｎｍのＳ
ｉ Ｏ２膜１０４を形成した。酸化は、１０００℃の温
度で、１０％の酸素を含有したアルゴンガス雰囲気中で
行なった。なお、この酸化の際。
第１のＳｉ膜は非晶質状態から多結晶状態に遷移し、同
時に不純物の活性化も完了する。続いて、厚さ２００ｎ
ｍの第２のＳｉ膜１０５を、第１のＳｉ膜１０３と同様
の条件により堆積した。そして、６５０℃の窒素雰囲気
で２０分間熱処理を行ない、第２のＳｉ膜の多結晶化と
不純物の活性化を行なった。その後、第２のＳｉ膜を加
工し、第２の電極とした。
上記方法により形成したＭＯ８型キャパシタの絶縁耐圧
（ｌＯ””Ａ／ｃｍ２の漏洩電流が生じたときの印加電
界強度）と第１のＳｉ膜中のリン濃度の関係を第１図に
示す。絶縁耐圧の測定においては、第１の電極１０３を
基準とし、第２の電極１０５に正の電圧を印加した。な
お、この場合の第２のＳｉ膜中のリン濃度は４Ｘ１×１
０２０ｃｍ−３とした。
図のように、第１のＳｉ膜中のリン濃度の増加とともに
絶縁耐圧は向上し、リン濃度が７×１０１０２０ａ’で
は７．８ＭＶ／ｃｍと、従来、約６ＭＶ／ｃｍが限界で
あったものが、単結晶Ｓｉ基板上に形成したＳ ｉ Ｏ
，膜と同等の値を示した。しかしながら、リン濃度が更
に増加すると、絶縁耐圧は急激に劣化した。従って、第
１のＳｉ膜中のリン濃度は、８Ｘ１×１０２０ｃｍ−”
以下とすべきである。なお、第１のＳｉ膜中のリン濃度
が１×１×１０２０Ｑｍ−”以下であると、膜のシート
抵抗が大きくなり、実用に適さない。
ここで、第１のＳｉ膜１０３を酸化する際の希釈ガスと
して、アルゴンの代わりに窒素を用いても、第１図と同
様の結果が得られた。しかし、絶縁耐圧は、各リン濃度
の値に対して、第１図より小さめであった。従って、希
釈用のガスとしては、窒素よりもアルゴン、ネオン等の
不活性ガスが望ましい。
比較のため、第１図には、従来法における結果も併せて
示した。従来法（ａ）は、Ｓ ｉ Ｈ４を原料ガスに用
い、６３０℃、すなわち多結晶状態で第１のＳｉ膜を２
００ｎｍ堆積し、続いてＬＰＣＶＤ法により１０ｎｍの
Ｓ ｉ Ｏ，膜を形成した後、４０ｋｅＶでリンイオン
を打込み、ＳｉＯ□膜を除去した後、１０００℃の温度
で、１０％の酸素を含有したアルゴン雰囲気中で酸化を
行なったものである。従来法（ｂ）は、従来法（ａ）の
Ｓｉ膜の堆積を５２５℃、つまり非晶質状態としたもの
である。なお、従来法（ａ）、従来法（ｂ）ともに、第
２のＳｉ膜の堆積は、本発明の方法によった。同図から
明らかなように、第１のＳｉ膜の堆積を多結晶、非晶質
いずれの状態で行なっても、リンのドーピングを膜堆積
後に行なったのでは、高いＭ緑耐圧は得られず、６．６
ＭＶ／ｃｍが最高であった。
本実施例によれば、Ｓｉ、ＨｓとＰＨ３を用いて、リン
をドーピングしながら、非晶質状態で第１及び第２のＳ
ｉ膜を堆積することにより、Ｓｉ電極間のＳｉＯ２膜の
絶縁耐圧を向上する効果がある。
なお、Ｓ ｉ Ｏ，膜として、ＣＶＤ法で形成した膜を
用いても、同様の効果を得ることができる。
実施例２
第３図に、本発明の第２の実施例の断面概略図を示す。
本実施例は一括消去型ＥＥＰＲＯＭであり、以下に示す
手順で作成した。
まず、抵抗率１０Ωａｍ、面方位（１００）のｐ型Ｓｉ
基板２０１の表面に、周知の選択酸化技術によりフィー
ルド酸化膜２０２を形成した。次いで、酸素雰囲気中で
Ｓｉ基板を酸化し、１５ｎｍのゲート酸化膜２０３を形
成した。続いて、５ｉｚＨ＝とＰＩ（３を原料ガスに用
い、ＬＰＣＶＤ法によりリンをドーピングしながら、５
２５℃で第１のＳｉ膜２０４を２００ｎｍ堆積した。Ｓ
ｉ膜中のリン濃度は５−Ｘ １×１０２０ ｃ ｍ−３
である。次に、公知の技術を用いて第１のＳｉ膜２０４
を加工し、フローティングゲートとした。
次に、１０００℃の温度で、１０％の酸素を含有したア
ルゴン雰囲気中で第１のＳ ｉ ｒＪ！Ａ２０４の表面
を酸化し、２０ｎｍのＳｉＯ２膜２０膜製０５した。続
いて、第２のＳｉ膜２０６を第１のＳｉ膜と同様の方法
で２００ｎｍ堆積した後、公知の技術により第２のＳｉ
膜を加工し、コントロールゲートとした。その後、リン
及びヒ素イオンを順次打込んでソース、ドレイン領域２
０７を形成した後、ＬＰＣＶＤ法により眉間酸化膜２０
８を形成し、これに接続孔を開け、Ａ１膜２０９を堆積
して引出し配線とした。
本方法により形成したＥＥＰＲＯＭのフローティングゲ
ート２０４とコントロールゲート２０６間のＳ ｉ Ｏ
，膜２０５の絶縁耐圧は、従来法に比べ、２０％以上向
上した。これとともに、フローティングゲートの電荷保
持時間が一桁向上した。
なお、本実施例において第１のＳｉ膜２０４の堆積の際
、膜中のリン濃度を、膜堆積の進行に従い０から５ Ｘ
１×１０２０ ｃ ｍ””へと漸次増加させる実験も
併せて行なった。この場合、Ｓ ｉ Ｏ，膜２０５の絶
縁耐圧は、上記方法と同一であったにもかかわらず、ゲ
ート酸化膜２０３の耐圧は１５％向上し、消去後のしき
い値電圧が２ｖから１ｖに低減した。
本実施例によれば、−括消去型Ｅ Ｅ Ｐ ＲＯＭのフ
ローティングゲート及びコントロールゲートを、５ｉ２
ＨＧとＰＨ，を用いて、リンをドーピングしながら、非
晶質状態で堆積することにより、電荷保持特性を大幅に
向上できるという効果がある。
なお、実施例１及び２では、第１及び第２のＳｉ膜の堆
積に際し、ドーピングガスにフォスフインを用い、リン
を不純物として導入したが、ドーピングガスにアルシン
を用い、ヒ素を導入しても同様の効果が得られる。
【発明の効果］
本発明によれば、多結晶Ｓｉ膜上に高い絶縁耐圧を有す
るＳｉＯ２膜を形成することができる。
これにより、ＬＳＩデバイスの高信頼化が図れる。
更に、従来室なわれていた熱拡散やイオン打込みが不要
となるので、ＬＳＩデバイス製造工程の大幅な簡略化が
図れる。[Means for solving the problem] The above purpose has the following structure. (1) The first Si film is deposited while doping with impurities. (2) The first Si film is deposited at a deposition temperature of 550° C. or less in an amorphous state. (3) Set the impurity concentration in the first Si film to 8×102fl
This is achieved by making C'3 or less. [Operation] According to the above manufacturing method, the unevenness of the interface between the first Si film and the SiO2 film and the interface between the SiO2 film and the second Si film is is less than 5 nm, making it extremely smooth.Therefore, there is no local electric field concentration caused by the unevenness of the polycrystalline Si film, which occurs in the conventional technology.Furthermore, the crystal grain size of the present Si film is smaller than that of the conventional polycrystalline Si film. It is approximately 10 times larger than a Si film, and
Since the film is deposited while doping with impurities, the concentration of impurities that segregate at grain boundaries is small. Therefore, the amount of impurities incorporated into the SiO2 film due to oxidation is reduced. Therefore, polycrystalline 5i-3i with high dielectric strength
It becomes possible to form an n,-polycrystalline Si structure. Example 1 Example 1 First, a first example of the present invention will be described in detail with reference to FIG. This implementation was created using the following steps. First, an n-type S with a resistivity of 0.1ΩQm and a plane orientation of (100)
A field oxide film 102 was formed on the surface of the i-substrate 101 by a well-known selective oxidation technique. Next, the first Si film 103 is coated with disilane (
sxaHa) and phosphine (PH, ) were deposited to a thickness of 200 nm at 525° C. by low pressure chemical vapor deposition (LPCVD) while doping with phosphorus. Si film 10
No. 3 is amorphous immediately after film deposition. When depositing the Si film 103, nitrogen was used as a diluent gas. This is because since the flow rate of PH is small, it can be easily controlled by using diluent gas. Furthermore, the use of a diluent gas has the effect of improving the uniformity of film thickness and concentration among wafers of the same batch. In addition to nitrogen, an inert gas such as helium or argon may be used as the diluent gas. This Si film 103 was processed using well-known lamination techniques and dry etching techniques to form a first electrode. Next, 20 nm of S was deposited on the surface of the Si film using a thermal oxidation method.
An iO2 film 104 was formed. The oxidation was carried out at a temperature of 1000° C. in an argon gas atmosphere containing 10% oxygen. Note that during this oxidation. The first Si film transitions from an amorphous state to a polycrystalline state, and at the same time, activation of impurities is completed. Next, a thickness of 200n
A second Si film 105 of m was deposited under the same conditions as the first Si film 103. Then, heat treatment was performed in a nitrogen atmosphere at 650° C. for 20 minutes to polycrystallize the second Si film and activate impurities. Thereafter, the second Si film was processed to form a second electrode. FIG. 1 shows the relationship between the dielectric strength of the MO8 type capacitor formed by the above method (the applied electric field strength when a leakage current of 1O""A/cm2 occurs) and the phosphorus concentration in the first Si film. In measuring the dielectric strength, a positive voltage was applied to the second electrode 105 using the first electrode 103 as a reference. Note that the phosphorus concentration in the second Si film in this case is 4×1×1
020 cm-3. As shown in the figure, the dielectric strength voltage improves as the phosphorus concentration in the first Si film increases, and when the phosphorus concentration is 7×101020a', it is 7.8 MV/cm, whereas the conventional limit was about 6 MV/cm. However, S i O formed on a single crystal Si substrate
, showed a value equivalent to that of the membrane. However, when the phosphorus concentration further increased, the dielectric strength deteriorated rapidly. Therefore, the phosphorus concentration in the first Si film is 8×1×1020 cm-”
It should be: Note that if the phosphorus concentration in the first Si film is less than 1 x 1 x 1020Qm-'', the sheet resistance of the film becomes large and is not suitable for practical use.Here, when oxidizing the first Si film 103, Even when nitrogen was used instead of argon as the diluent gas, the same results as in Fig. 1 were obtained.However, the dielectric strength voltage was smaller than in Fig. 1 for each phosphorus concentration value. Therefore, as a diluent gas, an inert gas such as argon or neon is preferable to nitrogen.For comparison, Figure 1 also shows the results of the conventional method.Conventional method (a) , using S i H4 as the raw material gas, the first Si film was heated at 630°C, that is, in a polycrystalline state.
After forming a 10 nm SiO film by LPCVD, phosphorus ions were implanted at 40 keV, the SiO□ film was removed, and an argon atmosphere containing 10% oxygen was deposited at a temperature of 1000°C. Oxidation was carried out inside. In the conventional method (b), the Si film of the conventional method (a) is deposited at 525° C., that is, in an amorphous state. In both conventional method (a) and conventional method (b), the second Si film was deposited by the method of the present invention. As is clear from the figure, regardless of whether the first Si film is deposited in a polycrystalline or amorphous state, a high M green breakdown voltage cannot be obtained if phosphorus doping is performed after the film is deposited. , 6.6
MV/cm was the highest. According to this embodiment, Si, Hs and PH3 are used to form the first and second S in an amorphous state while doping phosphorus.
Depositing the i film has the effect of improving the dielectric strength of the SiO2 film between the Si electrodes. Note that the same effect can be obtained even if a film formed by a CVD method is used as the S i O film. Embodiment 2 FIG. 3 shows a schematic cross-sectional view of a second embodiment of the present invention. This example is a batch erasing type EEPROM, which was created according to the procedure shown below. First, p-type Si with a resistivity of 10 Ωam and a plane orientation of (100)
A field oxide film 202 was formed on the surface of the substrate 201 by a well-known selective oxidation technique. Next, the Si substrate was oxidized in an oxygen atmosphere to form a 15 nm gate oxide film 203. Subsequently, using 5izH= and PI (3 as raw material gases) and doping phosphorus by the LPCVD method, 5
A first Si film 204 was deposited to a thickness of 200 nm at 25°C. S
The phosphorus concentration in the i film is 5-X 1 x 1020 cm-3
It is. Next, a first Si film 204 is formed using a known technique.
was processed into a floating gate. Next, a first S i rJ! was performed at a temperature of 1000° C. in an argon atmosphere containing 10% oxygen. The surface of A204 was oxidized to form 20 20 nm SiO2 films. Subsequently, a second Si film 206 is deposited to a thickness of 200 nm in the same manner as the first Si film, and then a second Si film 206 is deposited using a known technique.
The membrane was processed and used as a control gate. After that, phosphorus and arsenic ions are sequentially implanted into the source and drain regions 2.
After forming 07, a glabellar oxide film 20 is formed by LPCVD method.
8 was formed, a connection hole was opened in this, and an A1 film 209 was deposited to form a lead wiring. S i O between the floating gate 204 and the control gate 206 of the EEPROM formed by this method.
, the dielectric strength of the film 205 was improved by more than 20% compared to the conventional method. Along with this, the charge retention time of the floating gate has been improved by an order of magnitude. In this example, when depositing the first Si film 204, the phosphorus concentration in the film was varied from 0 to 5X as the film deposition progressed.
Experiments were also conducted in which the thickness was gradually increased to 1 x 1020 cm''. In this case, although the dielectric strength voltage of the SiO film 205 was the same as in the above method, the withstand voltage of the gate oxide film 203 was improved by 15%, and the threshold voltage after erasing was increased from 2V to 1V. Reduced. According to this embodiment, the floating gate and control gate of the bulk erase type EEPROM are 5i2
By using HG and PH and depositing in an amorphous state while doping phosphorus, there is an effect that charge retention characteristics can be significantly improved. In Examples 1 and 2, when depositing the first and second Si films, phosphine was used as the doping gas and phosphorus was introduced as an impurity, but the same result could be obtained even if arsine was used as the doping gas and arsenic was introduced. The effect of this can be obtained. [Effects of the Invention] According to the present invention, a SiO2 film having a high dielectric strength can be formed on a polycrystalline Si film. This makes it possible to improve the reliability of the LSI device. Furthermore, since thermal diffusion and ion implantation, which were conventionally performed in a chamber, are no longer necessary, the LSI device manufacturing process can be greatly simplified.
第１図は１本発明の実施例と従来例によるＳ１膜中の不
純物濃度と絶縁耐圧の関係を示す曲線図、第２図及び第
３図は、本発明の実施例を示す半導体装置の断面図であ
る。
符号の説明
１０１．２０１・・・Ｓｉ基板、１０２，２０２・・・
フィールド酸化膜、２０３・・・ゲート酸化膜、１０３
．２０４・・・第１のＳｉ膜、１０４．２０５・・・Ｓ
ｉＯ２膜、１０５．２０６・・・第２のＳｉ膜、２０７
・・・拡散層、２０８・・層間酸化膜、２０９・・・Ａ
Ｉ膜遁
口
猶
スFIG. 1 is a curve diagram showing the relationship between impurity concentration in the S1 film and dielectric strength voltage according to an embodiment of the present invention and a conventional example, and FIGS. 2 and 3 are cross-sections of a semiconductor device showing an embodiment of the present invention. It is a diagram. Explanation of symbols 101.201...Si substrate, 102,202...
Field oxide film, 203... Gate oxide film, 103
．． 204...first Si film, 104.205...S
iO2 film, 105.206... second Si film, 207
...Diffusion layer, 208...Interlayer oxide film, 209...A
I-membrane evacuation
Claims (1)
おいて、該シリコン膜中に、粒径が少なくとも膜厚の１
０倍以上の結晶粒を含むことを特徴とする半導体装置。 ２、上記シリコン膜中の不純物としてリンもしくはヒ素
を含み、その濃度が、１×１０＾２＾０ｃｍ＾−＾３以
上、８×１０＾２＾０ｃｍ＾−＾３以下であることを特
徴とする請求項第１項記載の半導体装置。 ３、上記シリコン膜上に、二酸化シリコンからなる絶縁
膜を形成した請求項第１項ないし第２項記載の半導体装
置。 ４、上記絶縁膜上に第２のシリコン膜を形成した請求項
第３項記載の半導体装置。 ５、上記シリコン膜と絶縁膜の界面の凹凸が５ｎｍ以下
であることを特徴とする請求項第３項ないし第４項記載
の半導体装置。 ６、１０＾−＾６Ａ／ｃｍ＾２の漏洩電流が生じる際の
絶縁耐圧が７ＭＶ／ｃｍ以上である多結晶シリコンの熱
酸化膜を具備した半導体装置。 ７、上記半導体装置がＭＯＳ型不揮発性メモリであるこ
とを特徴とする請求項第１項ないし第６項記載の半導体
装置。 ８、上記シリコン膜内の下層側領域における不純物濃度
が、内部もしくは上層側領域における不純物濃度よりも
小さいことを特徴とする請求項第１項ないし第７項記載
の半導体装置。 ９、任意の段差を有する半導体基板上に、不純物をドー
ピングしながら第１のシリコン膜を堆積し、その後、第
１のシリコン膜上に、二酸化シリコンから成る絶縁膜を
形成する半導体装置の製造方法において、第１のシリコ
ン膜の堆積を、ジシランもしくはトリシランとフォスフ
ィンとを含む原料ガスを用い、減圧化学気相成長法によ
り、４５０℃以上、５５０℃以下の範囲で行なうことを
特徴とする半導体装置の製造方法。 １０、上記絶縁膜上に第２のシリコン膜を、第１のＳｉ
膜の堆積と同種の原料ガスを用い、同様の温度範囲で堆
積することを特徴とする請求項第９項記載の半導体装置
の製造方法。 １１、上記第１及び第２のＳｉ膜の堆積のいずれか一方
もしくは双方を、フォスフィンにかえてアルシンを原料
ガスに用いて行なうことを特徴とする請求項第９項ない
し第１０項記載の半導体装置の製造方法。 １２、上記絶縁膜が、第１のシリコン膜を酸化して形成
した二酸化シリコン膜であることを特徴とする請求項第
９項ないし第１１項記載の半導体装置の製造方法。 １３、上記第１のシリコン膜の酸化の一部分を、アルゴ
ン、ネオン等の不活性ガスで希釈された酸素雰囲気中で
行なうことを特徴とする請求項第９項ないし第１２項記
載の半導体装置の製造方法。 １４、上記絶縁膜が、化学気相成長法により形成した二
酸化シリコン膜であることを特徴とする請求項第９項な
いし第１１項記載の半導体装置の製造方法。[Claims] 1. In a semiconductor device comprising a silicon film containing impurities, the silicon film contains grains with a particle size of at least 1 film thickness.
A semiconductor device characterized by containing 0 times or more crystal grains. 2. The silicon film contains phosphorus or arsenic as an impurity, and its concentration is 1 x 10^2^0 cm^-^3 or more and 8 x 10^2^0 cm^-^3 or less. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1 or 2, wherein an insulating film made of silicon dioxide is formed on the silicon film. 4. The semiconductor device according to claim 3, wherein a second silicon film is formed on the insulating film. 5. The semiconductor device according to claim 3 or 4, wherein the unevenness of the interface between the silicon film and the insulating film is 5 nm or less. 6. A semiconductor device comprising a polycrystalline silicon thermal oxide film having a dielectric strength of 7 MV/cm or more when a leakage current of 10^-^6 A/cm^2 occurs. 7. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is a MOS type nonvolatile memory. 8. The semiconductor device according to claim 1, wherein the impurity concentration in the lower region of the silicon film is lower than the impurity concentration in the internal or upper region. 9. A method for manufacturing a semiconductor device in which a first silicon film is deposited on a semiconductor substrate having arbitrary steps while doping with impurities, and then an insulating film made of silicon dioxide is formed on the first silicon film. A semiconductor device characterized in that the first silicon film is deposited by a low pressure chemical vapor deposition method using a source gas containing disilane or trisilane and phosphine at a temperature of 450° C. or higher and 550° C. or lower. manufacturing method. 10. Place a second silicon film on the insulating film, and place a second silicon film on the first silicon film.
10. The method of manufacturing a semiconductor device according to claim 9, wherein the deposition is performed using the same type of source gas as that used for film deposition and in the same temperature range. 11. The semiconductor according to claim 9 or 10, wherein either or both of the first and second Si films are deposited using arsine as a raw material gas instead of phosphine. Method of manufacturing the device. 12. The method of manufacturing a semiconductor device according to claim 9, wherein the insulating film is a silicon dioxide film formed by oxidizing a first silicon film. 13. The semiconductor device according to any one of claims 9 to 12, wherein a part of the oxidation of the first silicon film is performed in an oxygen atmosphere diluted with an inert gas such as argon or neon. Production method. 14. The method of manufacturing a semiconductor device according to claim 9, wherein the insulating film is a silicon dioxide film formed by chemical vapor deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01268926A JP3140023B2 (en) | 1989-10-18 | 1989-10-18 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01268926A JP3140023B2 (en) | 1989-10-18 | 1989-10-18 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03132078A true JPH03132078A (en) | 1991-06-05 |
| JP3140023B2 JP3140023B2 (en) | 2001-03-05 |
Family
ID=17465200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01268926A Expired - Lifetime JP3140023B2 (en) | 1989-10-18 | 1989-10-18 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3140023B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004023559A1 (en) * | 2002-08-30 | 2004-03-18 | Fujitsu Amd Semiconductor Limited | Semiconductor storage device and its manufacturing method |
| JP2004096093A (en) * | 2002-07-18 | 2004-03-25 | Hynix Semiconductor Inc | Manufacture of semiconductor memory element |
| JP2008047870A (en) * | 2006-07-19 | 2008-02-28 | Toshiba Corp | Nonvolatile semiconductor memory device |
| JP2012044229A (en) * | 2006-07-19 | 2012-03-01 | Toshiba Corp | Nonvolatile semiconductor memory device |
-
1989
- 1989-10-18 JP JP01268926A patent/JP3140023B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004096093A (en) * | 2002-07-18 | 2004-03-25 | Hynix Semiconductor Inc | Manufacture of semiconductor memory element |
| JP4669655B2 (en) * | 2002-07-18 | 2011-04-13 | 株式会社ハイニックスセミコンダクター | Manufacturing method of semiconductor memory device |
| WO2004023559A1 (en) * | 2002-08-30 | 2004-03-18 | Fujitsu Amd Semiconductor Limited | Semiconductor storage device and its manufacturing method |
| JP2008047870A (en) * | 2006-07-19 | 2008-02-28 | Toshiba Corp | Nonvolatile semiconductor memory device |
| JP2012044229A (en) * | 2006-07-19 | 2012-03-01 | Toshiba Corp | Nonvolatile semiconductor memory device |
| US8133782B2 (en) | 2006-07-19 | 2012-03-13 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and manufacturing method thereof |
| US8330206B2 (en) | 2006-07-19 | 2012-12-11 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3140023B2 (en) | 2001-03-05 |
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