JPH03155630A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03155630A JPH03155630A JP29552189A JP29552189A JPH03155630A JP H03155630 A JPH03155630 A JP H03155630A JP 29552189 A JP29552189 A JP 29552189A JP 29552189 A JP29552189 A JP 29552189A JP H03155630 A JPH03155630 A JP H03155630A
- Authority
- JP
- Japan
- Prior art keywords
- film
- sog
- polymer
- oxygen
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000001301 oxygen Substances 0.000 claims abstract description 12
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- 239000012298 atmosphere Substances 0.000 claims abstract description 4
- 239000002904 solvent Substances 0.000 claims abstract 2
- 239000010408 film Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 9
- 239000003960 organic solvent Substances 0.000 abstract description 9
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229920000642 polymer Polymers 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 7
- 238000001312 dry etching Methods 0.000 abstract description 6
- 229910000838 Al alloy Inorganic materials 0.000 abstract description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 2
- 239000007789 gas Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 5
- 238000000576 coating method Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 244000025254 Cannabis sativa Species 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法、特にＳＯＧ塗布の前
処理に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a pretreatment for SOG coating.
従来微細化された半導体装置の配線方法は、例えば第２
図の如く、半導体素子が形成された半導体基板２１上の
フィールド絶縁膜２２にコンタクトホールを形成した後
、配線用のアルミニウム合金（例えばＡｌ−８ｉ）を０
．５〜１．０μｍスパッタする。次にフォトレジストを
マスクにして、前記アルミニウム合金薄膜をドライエツ
チングによりバターニングして一層目の配線２３を形成
する。続いて層間絶縁膜２４をＣＶＤ等により積層する
が、平坦性を高めるために、必要膜厚よりも厚く堆積し
た後、全面を異方性のドライエツチングによってエッチ
バックする。その後、表面のポリマー除去のためにフェ
ノール系の有機溶剤による洗浄、さらに純水による洗浄
を行なう。さらに、平坦性を高めるために、５ＯＧ２５
を全面塗布し、４００℃前後でキュアを行なっている。Conventional wiring methods for miniaturized semiconductor devices include, for example, the second
As shown in the figure, after forming a contact hole in a field insulating film 22 on a semiconductor substrate 21 on which a semiconductor element is formed, an aluminum alloy (for example, Al-8i) for wiring is removed.
．． Sputter 5 to 1.0 μm. Next, using a photoresist as a mask, the aluminum alloy thin film is patterned by dry etching to form the first layer wiring 23. Subsequently, an interlayer insulating film 24 is laminated by CVD or the like, but in order to improve flatness, the interlayer insulating film 24 is deposited thicker than necessary, and then the entire surface is etched back by anisotropic dry etching. Thereafter, cleaning with a phenolic organic solvent and further cleaning with pure water are performed to remove the polymer from the surface. Furthermore, in order to improve flatness, 5OG25
was applied to the entire surface and cured at around 400°C.
続いて、−層目の配線２３等とのコンタクトをとるため
にスルーホール２６を開孔後、二層目の配線２７を形成
している。最終的にパシベーション膜として窒化シリコ
ン膜２８を成長させた後、外部電極取り出し用のポンデ
ィングパッド２９を開孔している。Subsequently, a through hole 26 is opened to make contact with the -th layer wiring 23, etc., and then a second layer wiring 27 is formed. After finally growing a silicon nitride film 28 as a passivation film, a bonding pad 29 for taking out an external electrode is opened.
しかしながら従来技術では、層間絶縁膜堆積後のエッチ
バックで発生するポリマーをフェノール系の有機溶剤に
よって処理しているが、完全には除去できない。また、
フェノール系の有機溶剤によって酸化シリコン膜の表面
状態が変化して、つづ＜ＳＯＧの塗布工程で、ＳＯＧと
のぬれ性が悪く、塗布膜厚の部分的なばらつきが発生し
ていた。However, in the prior art, polymer generated during etch-back after deposition of an interlayer insulating film is treated with a phenolic organic solvent, but cannot be completely removed. Also,
The surface state of the silicon oxide film was changed by the phenol-based organic solvent, resulting in poor wettability with SOG during the subsequent SOG coating process, and local variations in coating film thickness occurred.
また、ＳＯＧのキュア時に下層のＣＶＤ酸化シリコン膜
との収縮率の違いからクラック３０等を生じていた。Furthermore, during curing of the SOG, cracks 30 and the like were generated due to the difference in shrinkage rate with the underlying CVD silicon oxide film.
しかるに本発明は、かかる課題を解決するものであり、
その目的とするところは、多層配線間の層間絶縁膜のＳ
ＯＧ膜厚の均一性の向上と、クラック発生の防止により
、信頼性の高い微細半導体装置を安定供給することであ
る。However, the present invention solves these problems,
The purpose of this is to
The objective is to stably supply highly reliable fine semiconductor devices by improving the uniformity of the OG film thickness and preventing cracks from occurring.
本発明の半導体装置の製造方法は、
ａ）アルミニウムもしくはその合金薄膜による配線を形
成する工程と、
ｂ）層間絶縁膜を形成する工程と、
Ｃ）層間絶縁膜を全面エッチバックする工程とｄ）フェ
ノール系の有機溶剤によって洗浄する工程と、
ｅ）表面を少なくとも数％のオゾンを含む酸素雰囲気ま
たは、酸素プラズマ中で熱処理する工程と、ｆ）ＳＯＧ
（Ｓｐｉｎ Ｏｎ Ｇｒａｓｓ）を塗布する工程
と、
う
、ｔｈ）ＳＯＧをキュアする工程とからなることを特徴
とする。The method for manufacturing a semiconductor device of the present invention includes: a) forming a wiring using a thin film of aluminum or its alloy; b) forming an interlayer insulating film; C) etching back the entire surface of the interlayer insulating film; and d) a step of cleaning with a phenolic organic solvent; e) a step of heat-treating the surface in an oxygen atmosphere containing at least several percent ozone or in an oxygen plasma; and f) a step of SOG.
The method is characterized by comprising a step of applying (Spin On Grass) and a step of curing SOG.
以下本発明の実施例における工程を、第１図に基づいて
詳細に説明する。Hereinafter, steps in an embodiment of the present invention will be explained in detail based on FIG.
まず（ａ）図の如く、サブミクロンルールの集積回路製
造において、トランジスタや抵抗等の半導体素子が形成
された半導体基板１１上のフィールド絶縁膜１２にコン
タクトホールを開孔する。First, as shown in FIG. 1(a), in manufacturing an integrated circuit according to the submicron rule, a contact hole is formed in a field insulating film 12 on a semiconductor substrate 11 on which semiconductor elements such as transistors and resistors are formed.
続いて（ｂ）図のごとく、配線用のアルミニウムーシリ
コン合金を０．５〜１．０μｍスパッタする。次にフォ
トレジストをマスクにして、前記アルミニウム合金薄膜
をドライエツチングによりパターニングして一層目の配
線１３を形成する。続いて層間絶縁膜１４を、モノシラ
ンと酸素を原料とした減圧ＣＶＤ等により約１μｍ堆積
する。続いて（ｃ）図のごとく全面をＣＦ４等のガスを
用いた異方性のドライエツチングによって約０．４μｍ
エッチバックする。その後、表面のポリマー除去のため
にフェノール系の有機溶剤による洗浄及び、純水による
洗浄を行なう。次に、有機溶剤によって除去できなかっ
たポリマーの除去及び、ＳＯＧとのぬれ性を高めるため
に、約３００℃の炉内で、 ９６のオゾンを含んだ酸
素を流して約５分間、常圧で熱処理を行なう。さらに、
平坦性を高めるために、５ＯＧ１５を全面塗布し、窒素
雰囲気中で４００℃前後で３０分間キュアを行なってい
る。続いて、−層目の配線１３等とのコンタクトをとる
ためにスルーホール１６を開孔後、二層目の配線１７を
形成している。最終的にパシベーション膜として窒化シ
リコン膜１８を成長させた後、外部電極取り出し用のポ
ンディングパッド１９を開孔し、（ｄ）図のごとく完成
する。Subsequently, as shown in the figure (b), an aluminum-silicon alloy for wiring is sputtered to a thickness of 0.5 to 1.0 μm. Next, using a photoresist as a mask, the aluminum alloy thin film is patterned by dry etching to form the first layer wiring 13. Subsequently, an interlayer insulating film 14 of about 1 μm is deposited by low pressure CVD using monosilane and oxygen as raw materials. Next, as shown in (c), the entire surface is etched by anisotropic dry etching using a gas such as CF4 to a thickness of approximately 0.4 μm.
Have sex back. Thereafter, cleaning with a phenolic organic solvent and pure water are performed to remove the polymer from the surface. Next, in order to remove the polymer that could not be removed with the organic solvent and to improve the wettability with SOG, it was heated in a furnace at about 300°C and heated with oxygen containing 96 ozone for about 5 minutes at normal pressure. Perform heat treatment. moreover,
In order to improve flatness, 5OG15 was applied over the entire surface and cured at around 400° C. for 30 minutes in a nitrogen atmosphere. Subsequently, a through hole 16 is opened to make contact with the -th layer wiring 13, etc., and then a second layer wiring 17 is formed. Finally, after growing a silicon nitride film 18 as a passivation film, a bonding pad 19 for taking out an external electrode is opened to complete the process as shown in FIG.
この様にしてなる半導体装置のＳＯＧ膜厚の部分的な膜
厚のばらつきを激減し、平坦性不良による配線の断線や
ステップカバレッジの不足等、信頼性上における問題は
なくなった。また、ＳＯＧに起因するクラックの発生も
なくなり歩留りが向上した。In this manner, local variations in the SOG film thickness of the semiconductor device are drastically reduced, and reliability problems such as wire breakage and insufficient step coverage due to poor flatness are eliminated. In addition, cracks caused by SOG were no longer generated, and the yield was improved.
ここで、オゾンによる処理温度は、高い方が除去の効果
が良好であったが、４５０℃以上ではアルミニウム配線
の変形等を生じ好ましくない。また、圧力に関しては、
常圧のみならず減圧でも効果が認められた。また、実施
例ではオゾンについて述べているが、酸素プラズマ中で
の熱処理に於いても同様の結果が得られた。Here, the higher the ozone treatment temperature, the better the removal effect, but if it is higher than 450° C., the aluminum wiring may be deformed, which is not preferable. Also, regarding pressure,
The effect was observed not only at normal pressure but also at reduced pressure. Further, although ozone is described in the examples, similar results were obtained in heat treatment in oxygen plasma.
なお、実施例では、酸化シリコン膜の製造方法としてモ
ノシラン−酸素系の減圧ＣＶＤＩＩを例としたが、ＴＥ
０１ ［Ｓ ｉ （ＯＣ２Ｈｓ ） ａ ］系のプラ
ズマＣＶＤ膜、ＴＥ０１−０３系の酸化シリコン膜でも
同様の効果が認められた。In the examples, monosilane-oxygen-based low-pressure CVDII was used as an example of a method for manufacturing a silicon oxide film, but TE
Similar effects were observed for the 01 [S i (OC2Hs) a ]-based plasma CVD film and the TE01-03-based silicon oxide film.
以上の如く本発明によれば、酸化シリコン膜のエッチバ
ック、フェノール系の有機溶剤によるポリマー除去後に
オゾンまたは、酸素プラズマを含む雰囲気中で熱処理す
ることによって、ＳＯＧとのぬれ性を改善することがで
き、信頼性を向上する効果があり、微細半導体装置の実
用化と安定供給が可能となる。As described above, according to the present invention, the wettability with SOG can be improved by heat-treating the silicon oxide film in an atmosphere containing ozone or oxygen plasma after etching back the silicon oxide film and removing the polymer with a phenolic organic solvent. This has the effect of improving reliability, and enables the practical application and stable supply of fine semiconductor devices.
１Ｌ２１ ・ ・ １２．２２・ ・ １３．２３φ 拳 １４．２４嗜 ・ １５．２５ ・ ・ １６．２６ゆ 命 １７．２７拳 ・ １８．２８φ 拳 １９．２９・ Φ １０．２０・ ・ ３０・ ・ ・ ・ ・ 半導体基板 フィールド絶縁膜 第一層目の配線 層間絶縁膜 ＳＯＧ スルーホール 第二層目の配線 プラズマ窒化膜 ポンディングパッド ０ＧＯＳ クラック 以1L21 ・・ 12.22・・ 13.23φ fist 14.24 ・ 15.25 ・・ 16.26 life 17.27 fist・ 18.28φ fist 19.29・ Φ 10.20・・ 30・・・・・・ semiconductor substrate field insulation film First layer wiring interlayer insulation film SOG through hole Second layer wiring plasma nitride film pounding pad 0GOS crack Below
第１図（ａ）〜（ｄ）は、本発明の一実施例による半導
体装置の製造工程を示す概略断面図である。
第２図は、従来の半導体装置の製造工程を示す概略断面
図である。FIGS. 1(a) to 1(d) are schematic cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing the manufacturing process of a conventional semiconductor device.
Claims (1)
成する工程と、 ｂ）層間絶縁膜を形成する工程と、 ｃ）層間絶縁膜を全面エッチバックする工程とｄ）フェ
ノール系の有機溶剤によって洗浄する工程と、 ｅ）表面を少なくとも数％のオゾンを含む酸素雰囲気ま
たは、酸素プラズマ中で熱処理する工程と、ｆ）ＳＯＧ
（ＳｐｉｎＯｎＧｒａｓｓ）を塗布する工程と、 ｇ）ＳＯＧをキュアする工程とからなることを特徴とす
る半導体装置の製造方法。[Claims] a) a step of forming a wiring using aluminum or its alloy thin film; b) a step of forming an interlayer insulating film; c) a step of etching back the entire surface of the interlayer insulating film; and d) a step of etching back the entire surface of the interlayer insulating film; a step of cleaning with a solvent; e) a step of heat treating the surface in an oxygen atmosphere containing at least several percent ozone or in an oxygen plasma; and f) a step of SOG.
1. A method for manufacturing a semiconductor device, comprising the steps of: applying (SpinOnGrass); and g) curing SOG.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29552189A JPH03155630A (en) | 1989-11-14 | 1989-11-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29552189A JPH03155630A (en) | 1989-11-14 | 1989-11-14 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03155630A true JPH03155630A (en) | 1991-07-03 |
Family
ID=17821700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29552189A Pending JPH03155630A (en) | 1989-11-14 | 1989-11-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03155630A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5882425A (en) * | 1997-01-23 | 1999-03-16 | Semitool, Inc. | Composition and method for passivation of a metallization layer of a semiconductor circuit after metallization etching |
| JP2016162848A (en) * | 2015-02-27 | 2016-09-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
-
1989
- 1989-11-14 JP JP29552189A patent/JPH03155630A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5882425A (en) * | 1997-01-23 | 1999-03-16 | Semitool, Inc. | Composition and method for passivation of a metallization layer of a semiconductor circuit after metallization etching |
| JP2016162848A (en) * | 2015-02-27 | 2016-09-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
| CN105931984A (en) * | 2015-02-27 | 2016-09-07 | 瑞萨电子株式会社 | Method Of Manufacturing Semiconductor Device |
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