JPH03142952A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH03142952A JPH03142952A JP1282396A JP28239689A JPH03142952A JP H03142952 A JPH03142952 A JP H03142952A JP 1282396 A JP1282396 A JP 1282396A JP 28239689 A JP28239689 A JP 28239689A JP H03142952 A JPH03142952 A JP H03142952A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- groove
- recess
- semiconductor substrate
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 239000000463 material Substances 0.000 claims description 19
- 239000011810 insulating material Substances 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims 1
- 239000000945 filler Substances 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000011259 mixed solution Substances 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- UOCLXMDMGBRAIB-UHFFFAOYSA-N 1,1,1-trichloroethane Chemical compound CC(Cl)(Cl)Cl UOCLXMDMGBRAIB-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 125000005372 silanol group Chemical group 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置およびその製造方法に関するもの
で、特に高耐圧素子の素子間分離に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to isolation between high voltage elements.
従来、例えば高耐圧パワー素子と論理回路とを１チツプ
上に搭載する複合素子を形成する場合にはパワー素子と
論理回路の素子間分離が必要となる。なお、パワー素子
において駆動可能な電流量を向上させるには論理部を形
成するのと同じ面にソース及びゲートをまた反対の面に
はドレインを形成する、いわゆる縦型の素子が不可欠で
ある。Conventionally, when forming a composite device in which, for example, a high-voltage power device and a logic circuit are mounted on one chip, it is necessary to separate the power device and the logic circuit. Note that in order to improve the amount of current that can be driven in a power element, it is essential to use a so-called vertical element in which the source and gate are formed on the same side where the logic section is formed, and the drain is formed on the opposite side.
すなわち、この縦型のパワー素子と論理部を電気的に分
離することのできる構造が必要とされる。That is, a structure is required that can electrically isolate the vertical power element and the logic section.
いわゆる素子間分離技術としてはＰＮ接合による素子間
分離が一般的に知られている。このＰＮ接合による素子
間分離方法は、Ｐ型半導体素子上にＮ型エピタキシャル
層を形成し、このエピタキシャル層の表面からＰ型基板
に達するまで拡散によってＰ″層を設け、このＰ″層に
よってパワー素子部と論理回路部を分離するものである
。これにより、論理回路部をＰ″層により囲んだ状態で
ＰＮ接合が形成され、高電圧発生時にはこのＰＮ接合が
逆バイアスされ、論理部は他の領域と電気的に分離する
ことができる。As a so-called element isolation technique, element isolation using a PN junction is generally known. In this method of isolation between elements using a PN junction, an N-type epitaxial layer is formed on a P-type semiconductor element, a P'' layer is provided by diffusion from the surface of this epitaxial layer to a P-type substrate, and this P'' layer provides power. This separates the element section and the logic circuit section. As a result, a PN junction is formed with the logic circuit section surrounded by the P'' layer, and when a high voltage is generated, this PN junction is reverse biased, and the logic section can be electrically isolated from other regions.
しかしながら、この方法は３００ｖ以上のパワー素子を
形成する場合には分離用拡散層の拡散−深さが４０μｍ
以上となり、素子間分離構造形成のための拡散により横
方向の拡散幅が増大し、素子形成に利用できる面積の損
失が大きくなってしまう、更にパワー素子部の外周上に
は、高耐圧を保持するための、フィールドプレート或い
はガードリングといった高耐圧素子構造を形成しなけれ
ばならず、前記の素子分離の拡散に加えて更に面積の損
失を増大させてしまうことになる。また、ＰＮ接合分離
は熱的に不安定であり、１００°Ｃ以上の高温になると
リーク電流によりランチアップが発生しやすくなるとい
う問題点も有している。However, when forming a power element of 300 V or more, this method requires a diffusion depth of 40 μm for the isolation diffusion layer.
As a result, the lateral diffusion width increases due to diffusion to form an isolation structure between elements, resulting in a large loss of area that can be used for element formation.Furthermore, a high withstand voltage is maintained on the outer periphery of the power element part. For this purpose, a high voltage element structure such as a field plate or a guard ring must be formed, which results in an increase in area loss in addition to the above-mentioned element isolation diffusion. Furthermore, PN junction isolation is thermally unstable, and has the problem that launch-up is likely to occur due to leakage current at high temperatures of 100° C. or higher.
本発明は上記種々の問題に鑑みてなされたものであり、
基板表面を電流経路とする縦型のパワー素子の形成が可
能であるとともに、パワー素子の耐圧構造に要する基板
面積によりパワー素子部の素子寸法が大きくなることの
ない素子間分離が実現できる半導体装置およびその製造
方法を提供することを目的とする。The present invention has been made in view of the various problems mentioned above,
A semiconductor device that enables the formation of a vertical power element with the substrate surface as a current path, and also achieves isolation between elements without increasing the element dimensions of the power element part due to the substrate area required for the voltage-resistant structure of the power element. The purpose is to provide a method for producing the same.
本発明は上記目的を達成するために、
請求項１記載の発明では、いわゆる基板接合法を応用し
、
第１半導体基板および第２半導体基板の各々鏡面研磨面
を接合面として密着接合した接合基板において、
前記接合面の所定領域に配設された凹部と、少なくとも
前記第１半導体基板に設けられ、前記接合面から前記第
２半導体基板に対向する面方向に対して垂直方向の断面
積が徐々に小さくなる形状の溝部と、
前記凹部および溝部の内壁を被覆する絶縁層と、前記凹
部および溝部を埋込む充填材料と、前記溝部および凹部
にて区画され、前記絶縁層と前記充填材料にて電気的に
絶縁分離された前記接合基板の一領域に形成された第１
の機能素子部と、
前記溝部に隣接する前記接合基板の他領域に形成された
第２の機能素子部と、
を具備することを特徴とする半導体装置を提供する。In order to achieve the above object, the present invention provides a bonded substrate in which a so-called substrate bonding method is applied, and a first semiconductor substrate and a second semiconductor substrate are closely bonded using mirror-polished surfaces of each as a bonding surface. A recess provided in a predetermined region of the bonding surface, and a cross-sectional area of a recess provided in at least the first semiconductor substrate in a direction perpendicular to a surface facing from the bonding surface to the second semiconductor substrate gradually increases. a groove having a shape that becomes smaller in size; an insulating layer that covers the inner wall of the recess and the groove; a filling material that fills the recess and the groove; A first
Provided is a semiconductor device comprising: a functional element portion; and a second functional element portion formed in another region of the bonded substrate adjacent to the groove portion.
また、請求項２記載の発明においては、第１半導体基板
の一方の面の一領域に凹部を形成し、
この凹部の周縁部に前記凹部よりも深い溝部を形成し、
前記凹部および溝部を形威した面を全て絶縁物で被覆し
た後、前記凹部および溝部を充填材料で埋設し、
前記一方の面を鏡面研磨して、前記一方の面の他領域を
面出させ、
この鏡面研磨された前記第１半導体の一方の面と、少な
くとも一方の面が鏡面研磨された第２半導体基板の鏡面
研磨面とを接合することにより接合基板とし、
前記第１半導体基板の他方の面から前記溝部を表出させ
、
前記溝部および凹部にて区画され、前記絶縁物と前記充
填材料で電気的に分離された領域を前記接合基板の前記
第１半導体基板に形成することを特徴とする半導体装置
の製造方法を提供する。Further, in the invention according to claim 2, a recess is formed in a region of one surface of the first semiconductor substrate, a groove deeper than the recess is formed in a peripheral portion of the recess, and the recess and the groove are shaped. After covering all the exposed surfaces with an insulating material, the recesses and grooves are filled with a filling material, and the one surface is mirror-polished to expose the other area of the one surface. A bonded substrate is obtained by bonding one surface of the first semiconductor and a mirror-polished surface of a second semiconductor substrate whose at least one surface is mirror-polished, and the groove portion is opened from the other surface of the first semiconductor substrate. Manufacturing a semiconductor device characterized in that a region is formed in the first semiconductor substrate of the bonded substrate, and is defined by the groove and the recess and is electrically isolated by the insulator and the filling material. provide a method.
すなわち、請求項１記載の発明を採用することによって
、接合基板には絶縁層および充填材料にて埋設された溝
部および凹部にて電気的に絶縁分離された第１の機能素
子部が構成される。That is, by employing the invention set forth in claim 1, the first functional element section is configured in the bonded substrate, which is electrically insulated and isolated by the groove and the recess filled with the insulating layer and the filling material. .
また、この第１の機能素子部以外の領域においては、第
１および第２半導体基板が電気的に導通しているため、
第２の機能素子部として縦型のパワー素子が形成可能で
ある。In addition, since the first and second semiconductor substrates are electrically connected in a region other than the first functional element section,
A vertical power element can be formed as the second functional element section.
さらに、その縦型のパワー素子は、溝部の形状が例えば
いわゆる逆メサ状に形成可能であるために、その耐圧構
造に要する基板面積を小さくすることができる。Further, in the vertical power element, the groove can be formed into a so-called inverted mesa shape, so that the substrate area required for the voltage-resistant structure can be reduced.
従って、請求項１記載の発明によれば、基板裏面を電流
経路とする縦型のパワー素子の形成が可能であるととも
に、パワー素子の耐圧構造に要する基板面積によりパワ
ー素子部の素子寸法が大きくなることのない素子間分離
が実現できるという優れた効果がある。Therefore, according to the invention described in claim 1, it is possible to form a vertical power element with the back surface of the substrate as a current path, and the element size of the power element portion can be increased due to the substrate area required for the voltage-resistant structure of the power element. This has the excellent effect of realizing isolation between elements without causing damage.
また、請求項２記載の発明によれば、上記効果を有する
半導体装置を製造できるという優れた効果がある。Further, according to the second aspect of the invention, there is an excellent effect that a semiconductor device having the above-mentioned effects can be manufactured.
以下本発明を図に示す実施例に基づいて説明する。 The present invention will be described below based on embodiments shown in the drawings.
第１図は本発明第１実施例を適用した半導体装置の断面
図である。FIG. 1 is a sectional view of a semiconductor device to which a first embodiment of the present invention is applied.
以下、第１図に示す半導体装置を第２図（ａ）〜（ロ）
に示す製造工程に従って説明する。Below, the semiconductor device shown in FIG. 1 is shown in FIGS. 2(a) to (b).
This will be explained according to the manufacturing process shown in .
まず、第２図（ａ）の如く、低濃度の第１半導体基板１
の一方の面に所定のパターンを有する例えばＳｉｎ、膜
によるマスク２を形威し、第２図（ｂ）の如く、将来Ｓ
ｏｌ構造に論理部４０を構成する論理部構成予定領域を
選択的にエツチングし、凹部３を形成する。凹部３の深
さは後述するようにシリコンのラップポリッシュの精度
及び素子の耐圧とも関係するが２μｍ以上あればよい。First, as shown in FIG. 2(a), a first semiconductor substrate 1 with a low concentration
A mask 2 made of, for example, a Sin film having a predetermined pattern is formed on one surface of the S, as shown in FIG.
The region where the logic section 40 is to be formed is selectively etched in the OL structure to form the recess 3. The depth of the recess 3 is related to the accuracy of silicon lap polishing and the withstand voltage of the element, as will be described later, but it is sufficient if it is 2 μm or more.
次に、第２図（Ｃ）に示す如く、凹部３の周縁およびパ
ワー素子構成領域５の周縁に沿って楔状の、すなわち深
くなる程幅の狭くなる溝４を形成する。Next, as shown in FIG. 2(C), a wedge-shaped groove 4 is formed along the periphery of the recess 3 and the periphery of the power element forming region 5, that is, the groove becomes narrower as it gets deeper.
溝４形成法としては、例えば角度付ブレードによりダイ
ジグで溝を形成した後、溝側面の結晶欠陥除去のためＩ
ＴＦ、ＨＮＯｓ、ＣＨ３ＣＯ０Ｈ？ｌｉ合液により化学
エツチングを施す。そして、第２図（ｄ）に示す如く、
この凹部３及び溝４を形成した面に絶縁膜６を形成する
。絶縁膜材料としては例えば熱酸化、ＣＶＤ等により形
成したシリコン酸化膜、或いはＣＶＤ、 スパッタ法等
により形成した窒化珪素膜等が適当である。更に、ゲッ
タリング効果を付加するためにＰＳＧ膜、或いはＢＰＳ
Ｃ膜を絶縁膜６の形成後形成するようにしてもよい。The method for forming the groove 4 is, for example, to form the groove with a die jig using an angled blade, and then to remove crystal defects on the sides of the groove.
TF, HNOs, CH3CO0H? Chemical etching is performed using a li mixture. Then, as shown in Figure 2(d),
An insulating film 6 is formed on the surface where the recesses 3 and grooves 4 are formed. Suitable materials for the insulating film include, for example, a silicon oxide film formed by thermal oxidation, CVD, etc., or a silicon nitride film formed by CVD, sputtering, etc. Furthermore, in order to add a gettering effect, a PSG film or BPS film is used.
The C film may be formed after the insulating film 6 is formed.
しかる後、第２図（ｅ）に示す如く、凹部３及び溝４が
埋まるようにＣＶＤ法、スパック法、蒸着法等により多
結晶シリコン、酸化シリコン、窒化珪素等のシールド用
充填材料７を堆積させる。この時、第１半導体基板１の
反り等をできるだけ低減させるため、堆積する充填材料
は熱膨張係数が第１半導体基板１に近いことが望ましく
、単一材料では多結晶シリコンが適当である。Thereafter, as shown in FIG. 2(e), a filling material 7 for shielding such as polycrystalline silicon, silicon oxide, silicon nitride, etc. is deposited by CVD, spacing, vapor deposition, etc. so as to fill the recesses 3 and grooves 4. let At this time, in order to reduce warpage of the first semiconductor substrate 1 as much as possible, it is desirable that the deposited filling material have a coefficient of thermal expansion close to that of the first semiconductor substrate 1, and polycrystalline silicon is suitably used as a single material.
次に充填材料７をラップポリッシュ法によりパワ一部形
成領域５の第１半導体基板ｌの面が露出するまで鏡面研
磨を行い、第２図（ｆ）に示す如く、鏡面研磨面１ａを
形成する。Next, the filler material 7 is lap-polished until the surface of the first semiconductor substrate l in the power part formation region 5 is exposed, thereby forming a mirror-polished surface 1a as shown in FIG. 2(f). .
この鏡面研磨面１ａを有する第１半導体基板１と、少な
くとも一方の面を鏡面研磨した高濃度の第２半導体１ｖ
ｉｓとを、例えばトリクロルエタン煮沸、アセトン超音
波洗浄、ＮＨｚ、ＨｔＯｚ、ＨｚＯの混合液による有機
物の除去、Ｈ（１，Ｈ□０□。A first semiconductor substrate 1 having a mirror-polished surface 1a and a highly concentrated second semiconductor 1v having at least one mirror-polished surface.
is, for example, by boiling in trichloroethane, ultrasonic cleaning in acetone, removal of organic matter with a mixed solution of NHz, HtOz, and HzO, H(1, H□0□.
１１．０の混合液による金属汚染の除去および純水洗浄
を順次施すことにより充分洗浄する。その後、ＨＦ、ｔ
ｒｇｏ混合液により自然酸化膜を除去した後、例えばＨ
ｔＳｏ、−ＨｚＯｚの混合液に浸漬することにより、ウ
ェハ表面に１５Å以下の酸化膜を形成し、親水性を持た
せ、純水にて洗浄する。Thorough cleaning is performed by sequentially removing metal contamination with the mixed solution of No. 11.0 and washing with pure water. After that, HF,t
After removing the natural oxide film with rgo mixed solution, for example, H
By immersing the wafer in a mixed solution of tSo and -HzOz, an oxide film of 15 Å or less is formed on the wafer surface to make it hydrophilic, and the wafer is washed with pure water.
次に乾燥窒素等による乾燥を行い、基板表面に吸着する
水分量を制御した後、第２図（濁に示す如く、２枚の半
導体基板１．８の鏡面研摩面同士を密着させる。これに
より、２枚の基板１．８は表面に形成されたシラノール
基゛及び表面に吸着した水分子の水素結合により接着さ
れる。更に、この接着した基板ｌおよび８を例えば窒素
、アルゴン等の不活性ガス雰囲気中で１１００°Ｃ以上
、１時間以上の熱処理を施すことにより、Ｓｉ原子同士
の結合ができ、２枚の基板ｌおよび８は強固に接合され
、接合基板ｌＯが形成される。Next, after drying with dry nitrogen or the like to control the amount of moisture adsorbed on the substrate surface, as shown in FIG. , the two substrates 1.8 are bonded together by hydrogen bonds between silanol groups formed on the surfaces and water molecules adsorbed on the surfaces.Furthermore, the bonded substrates 1 and 8 are treated with an inert gas such as nitrogen or argon. By performing heat treatment in a gas atmosphere at 1100° C. or more for one hour or more, Si atoms are bonded to each other, and the two substrates 1 and 8 are firmly bonded to form a bonded substrate 10.
この後、第２図（ロ）に示す如く、第１半導体基板ｌの
第２半導体基板８に対向する側の表面１ｂに溝４が露出
するまでラップポリッシュを行う。これにより絶縁膜６
で電気的に絶縁され、充填材料７により埋められた基板
内部に空洞のない、ＳＯ■領域２０を有する半導体基板
１０が形成される。Thereafter, as shown in FIG. 2(b), lap polishing is performed until the grooves 4 are exposed on the surface 1b of the first semiconductor substrate 1 on the side facing the second semiconductor substrate 8. As a result, the insulating film 6
A semiconductor substrate 10 is formed having an SO2 region 20 which is electrically insulated from the wafer and filled with the filler material 7 and without a cavity inside the substrate.
この得られた基板１０に所定の素子を通常のプロセスに
従って形成することにより、第１図に示す半導体装置が
製造される。By forming predetermined elements on the obtained substrate 10 according to a normal process, the semiconductor device shown in FIG. 1 is manufactured.
第１図は、上記製造工程において基板ｌとしてＮ−型、
基板８としてＮ°型を用いて接合したもので、縦型パワ
ートランジスタ３０とこれを制御ゴ■する論理回路部４
０が１つの半導体基板ＩＯに形成されている。FIG. 1 shows that the substrate l used in the above manufacturing process is an N-type,
It is bonded using an N° type substrate 8, and includes a vertical power transistor 30 and a logic circuit section 4 that controls it.
0 is formed on one semiconductor substrate IO.
この縦型パワートランジスタ３０は接合基板１０の第１
半導体基板ｌ側の表面１ｂにソース電極３１、ゲート電
極３２が形成され、基板８の表面すなわち接合基＋７ｉ
１０の裏面にはドレイン電極３３が形成されている。ま
た、前述のごとく分離溝４は基板ｌの裏面すなわち接合
基板１０内部の接合面から楔状に形成しであるため、基
板１側から見た場合、Ｎ−層は逆台形（逆メサ）形状と
なっている。従って、素子の耐圧を保持するＰＮ接合面
は平坦とされて、絶縁膜６で保護された溝４による所定
の傾斜側面により、そのＰＮ接合面周縁部においても湾
曲した部分すなわち電界集中のおこりやすい領域のない
平坦面とされ、かつ逆メサ構造を構成するため、ＰＮ接
合面の端部の電界は弱められ、基板濃度に対応した理論
的に予想される高耐圧化が可能である。しかも、前述の
ようにＰＮ接合面に湾曲部がないため、ガードリングの
ような水平方向に空乏層を広げて電界を緩和する余分な
耐圧構造が不用であるため、パワー素子部の面積が低減
可能である。さらに、絶縁膜６および基板内部の空洞の
無により、吸湿等が原因となるパワー素子部の表面漏れ
電流が生じることはなく、経時変化の少ない安定した耐
圧が得られる。This vertical power transistor 30 is connected to the first
A source electrode 31 and a gate electrode 32 are formed on the surface 1b on the semiconductor substrate l side, and the surface of the substrate 8, that is, the junction group +7i
A drain electrode 33 is formed on the back surface of 10. Furthermore, as described above, since the separation groove 4 is formed in a wedge shape from the back surface of the substrate 1, that is, the bonding surface inside the bonded substrate 10, the N- layer has an inverted trapezoid (inverted mesa) shape when viewed from the substrate 1 side. It has become. Therefore, the PN junction surface that maintains the withstand voltage of the element is flat, and due to the predetermined inclined side surface formed by the groove 4 protected by the insulating film 6, curved portions, that is, electric field concentration are likely to occur even at the periphery of the PN junction surface. Since it is a flat surface with no regions and has an inverted mesa structure, the electric field at the end of the PN junction is weakened, making it possible to achieve a theoretically high breakdown voltage corresponding to the substrate concentration. Moreover, as mentioned above, since there is no curved part on the PN junction surface, there is no need for an extra voltage-resistant structure such as a guard ring that expands the depletion layer in the horizontal direction and alleviates the electric field, reducing the area of the power element part. It is possible. Furthermore, since there are no cavities inside the insulating film 6 and the substrate, surface leakage current in the power element section caused by moisture absorption, etc. does not occur, and a stable breakdown voltage with little change over time is obtained.
また、接合基板の内部は前述のように充填材料７により
埋められて空洞部が存在しないため、製造工程時に基板
１例の表面１ｂをラップポリッシュしても論理部４０と
パワー素子部３０の境界において欠けなどの発生する心
配はない、さらに境界部を表面１ｂに露出させることが
可能となるため、各領域への素子位置合わせは非常に容
易である。Further, since the inside of the bonded substrate is filled with the filling material 7 as described above and there is no cavity, even if the surface 1b of one example of the substrate is lap-polished during the manufacturing process, the boundary between the logic section 40 and the power element section 30 is There is no fear of chipping, etc., and since the boundary portion can be exposed on the surface 1b, alignment of the element to each region is very easy.
また、領域２０は単結晶基板により形成されているため
、素子特性が良好であり、また、絶縁層６によってパワ
一部３０と絶縁分離されているため、分離耐圧が大きく
耐熱性にも優れている。Further, since the region 20 is formed of a single crystal substrate, the device characteristics are good, and since the region 20 is insulated from the power part 30 by the insulating layer 6, it has a high isolation voltage and excellent heat resistance. There is.
次に第３図に本発明第２実施例を適用した複合化素子の
断面構造を示す。以下、本実施例を第４図（ａ）〜（ｆ
）に示す製造工程に従って説明する。Next, FIG. 3 shows a cross-sectional structure of a composite element to which the second embodiment of the present invention is applied. Hereinafter, this example will be explained in Figs. 4(a) to (f).
) will be explained according to the manufacturing process shown in ().
まず第４図（ａ）の如く、第１半導体基板５０にマスク
５１を形成した後Ｓ ＯＩ ｒｆｌ域及びパワ一部の端
部に対応する領域に窓５２を開ける。次にＨＦ。First, as shown in FIG. 4(a), a mask 51 is formed on a first semiconductor substrate 50, and then a window 52 is opened in a region corresponding to the S OI rfl region and the end of the power part. Next is HF.
ＨＮＯ３，ＣＨｆｆＣＯＯＨ混合液の北側酢酸系エツチ
ング液により窓５２の部分をエツチングする。The window 52 is etched using an acetic acid-based etching solution on the north side of a mixed solution of HNO3 and CHffCOOH.
この時、北側酢酸は窓の端部のエツチング速度が速く、
第４図（ｂ）のごとく窓に沿って溝部５３が形成される
ことになる。エツチング量を所定の耐圧が得られるまで
の深さにまで行った後、マスク材５１を除去し、第１実
施例と同様の方法で第１半導体基板５０のエツチングを
行った面５０ａに酸化膜等の絶縁膜５４を形成し、第４
図（Ｃ）に示す如く、充填材料５５を堆積する。しかる
後、第４図（ｄ）に示す如く、パワ一部に対応する領域
５６が露出するまでラップポリッシュを行う、更に前記
第２図（濁に示す工程と同様の方法で第４図（ｅ）に示
す如く第１半導体基板５０と第２半導体基板６０を接合
し、−枚の基板とする。そして最後に、第４図（「）に
示す如く、第１半導体基板５０の表面を第４図（ｂ）で
形威した凹部５３が表面上に現れるまでラップポリッシ
ュを行い、３０１６Ｕ域２０を形成する。そして、通常
のプロセスに従って所定の素子を形威し、第３図に示す
半導体装置が製造される。At this time, the northern acetic acid has a faster etching speed at the edge of the window.
A groove 53 is formed along the window as shown in FIG. 4(b). After etching has been performed to a depth that provides a predetermined breakdown voltage, the mask material 51 is removed and an oxide film is formed on the etched surface 50a of the first semiconductor substrate 50 in the same manner as in the first embodiment. A fourth insulating film 54 is formed.
As shown in Figure (C), a filling material 55 is deposited. Thereafter, as shown in FIG. 4(d), lap polishing is performed until a region 56 corresponding to a part of the power is exposed, and further, as shown in FIG. ), the first semiconductor substrate 50 and the second semiconductor substrate 60 are bonded together to form a second substrate.Finally, as shown in FIG. Lap polishing is performed until the recesses 53 shaped as shown in FIG. Manufactured.
上記方法によれば、素子間分離用の溝を形成する工程が
北側酢酸のエツチングというｌ工程だけで行えるため、
工程が簡略化可能であり、容易にウェハを形成すること
が可能である。なお、第３図において、第１実施例と同
−構成には第１図と同一符号が付しである。According to the above method, the step of forming grooves for isolation between elements can be performed with only one step of etching with acetic acid on the north side.
The process can be simplified, and wafers can be easily formed. In FIG. 3, the same components as in the first embodiment are given the same reference numerals as in FIG. 1.
なお、上記種々の実施例においては、ＭＯ３型構造のも
のについて説明したが、バイポーラ型素子を複合化する
ようにしたものに適用してもよい。In the various embodiments described above, MO3 type structures have been described, but the present invention may also be applied to structures in which bipolar type elements are combined.
また、基板の導電型もＮ型で説明したが、Ｐ型であって
もよい。また、接合基板と高耐圧部についての組み合わ
せもＰ−Ｎ、Ｐ−Ｐ、Ｎ−Ｐ、ＮＮのいずれでも構わな
い。Furthermore, although the conductivity type of the substrate has been described as N type, it may also be P type. Further, the combination of the bonded substrate and the high voltage part may be any of PN, PP, NP, and NN.
第１図は本発明第１実施例を適用した複合素子の断面図
、第２図（ａ）〜（ロ）は本発明第１実施例の製造工程
順断面図、第３図は本発明第２実施例を適用した複合素
子の断面図、第４図（ａ）〜（ｆ）は本発明第２実施例
の製造工程順断面図である。
１・・・第１半導体基板、３・・・凹部、４・・・溝、
６・・・絶縁膜、７・・・充填材料、８・・・第２半導
体基板、１０・・・接合基板、２０・・・ＳＯＩ領域、
３０・・・縦型パワー素子部、４０・・・論理回路部、
５０・・・第１半導体基板、５３・・・溝、５４・・・
絶縁膜、５５・・・充填材料、６０・・・第２半導体基
板。FIG. 1 is a sectional view of a composite element to which the first embodiment of the present invention is applied, FIGS. 4(a) to 4(f) are sectional views of a composite element to which the second embodiment is applied, and FIGS. 4(a) to 4(f) are sectional views in the order of manufacturing steps of the second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... First semiconductor substrate, 3... Recessed part, 4... Groove,
6... Insulating film, 7... Filling material, 8... Second semiconductor substrate, 10... Bonding substrate, 20... SOI region,
30... Vertical power element section, 40... Logic circuit section,
50... First semiconductor substrate, 53... Groove, 54...
Insulating film, 55... Filling material, 60... Second semiconductor substrate.
Claims (2)
研磨面を接合面として密着接合した接合基板において、 前記接合面の所定領域に配設された凹部と、少なくとも
前記第１半導体基板に設けられ、前記接合面から前記第
２半導体基板に対向する面方向に対して垂直方向の断面
積が徐々に小さくなる形状の溝部と、 前記凹部および溝部の内壁を被覆する絶縁層と、前記凹
部および溝部を埋込む充填材料と、 前記溝部および凹部にて区画され、前記絶縁層と前記充
填材料にて電気的に絶縁分離された前記接合基板の一領
域に形成された第１の機能素子部と、 前記溝部に隣接する前記接合基板の他領域に形成された
第２の機能素子部と、 を具備することを特徴とする半導体装置。(1) In a bonded substrate in which a first semiconductor substrate and a second semiconductor substrate are closely bonded using mirror-polished surfaces of each as a bonding surface, a recess provided in a predetermined area of the bonding surface and a recess provided in at least the first semiconductor substrate. a groove portion having a shape in which the cross-sectional area in a direction perpendicular to a surface direction facing the second semiconductor substrate from the bonding surface gradually decreases; an insulating layer covering the inner wall of the recess portion and the groove portion; a filling material for filling the groove; a first functional element portion formed in a region of the bonded substrate defined by the groove and the recess and electrically isolated by the insulating layer and the filling material; A semiconductor device comprising: a second functional element portion formed in another region of the bonded substrate adjacent to the groove portion.
し、 この凹部の周縁部に前記凹部よりも深い溝部を形成し、 前記凹部および溝部を形成した面を全て絶縁物で被覆し
た後、前記凹部および溝部を充填材料で埋設し、 前記一方の面を鏡面研磨して、前記一方の面の他領域を
面出させ、 この鏡面研磨された前記第１半導体の一方の面と、少な
くとも一方の面が鏡面研磨された第２半導体基板の鏡面
研磨面とを接合することにより接合基板とし、 前記第１半導体基板の他方の面から前記溝部を表出させ
、 前記溝部および凹部にて区画され、前記絶縁物と前記充
填材料で電気的に分離された領域を前記接合基板の前記
第１半導体基板に形成することを特徴とする半導体装置
の製造方法。(2) A recess is formed in a region of one surface of the first semiconductor substrate, a groove deeper than the recess is formed at the periphery of the recess, and the entire surface on which the recess and the groove are formed is covered with an insulating material. After that, the recesses and grooves are filled with a filling material, and the one surface is mirror-polished to expose the other area of the one surface, and the mirror-polished one surface of the first semiconductor and , a bonded substrate is obtained by bonding a mirror-polished surface of a second semiconductor substrate whose at least one surface is mirror-polished, the groove is exposed from the other surface of the first semiconductor substrate, and the groove and the recess are A method of manufacturing a semiconductor device, comprising forming a region on the first semiconductor substrate of the bonding substrate, which is partitioned by the insulating material and the filling material.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1282396A JPH0687480B2 (en) | 1989-10-30 | 1989-10-30 | Method for manufacturing semiconductor device |
| US07/731,268 US5164218A (en) | 1989-05-12 | 1991-07-17 | Semiconductor device and a method for producing the same |
| US07/844,889 US5313092A (en) | 1989-05-12 | 1992-03-03 | Semiconductor power device having walls of an inverted mesa shape to improve power handling capability |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1282396A JPH0687480B2 (en) | 1989-10-30 | 1989-10-30 | Method for manufacturing semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5238039A Division JP2746075B2 (en) | 1993-09-24 | 1993-09-24 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03142952A true JPH03142952A (en) | 1991-06-18 |
| JPH0687480B2 JPH0687480B2 (en) | 1994-11-02 |
Family
ID=17651864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1282396A Expired - Lifetime JPH0687480B2 (en) | 1989-05-12 | 1989-10-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0687480B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5298449A (en) * | 1992-03-06 | 1994-03-29 | Nec Corporation | Semiconductor substrate having a silicon-on-insulator structure and method of fabricating the same |
| JPH06204331A (en) * | 1993-09-24 | 1994-07-22 | Nippon Soken Inc | Semiconductor device |
| US5374582A (en) * | 1994-04-28 | 1994-12-20 | Nec Corporation | Laminated substrate for semiconductor device and manufacturing method thereof |
| US5847438A (en) * | 1995-03-31 | 1998-12-08 | Nec Corporation | Bonded IC substrate with a high breakdown voltage and large current capabilities |
| US5985681A (en) * | 1995-10-13 | 1999-11-16 | Nec Corporation | Method of producing bonded substrate with silicon-on-insulator structure |
| US6930359B2 (en) | 1999-11-18 | 2005-08-16 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| JP2006128230A (en) * | 2004-10-27 | 2006-05-18 | Fuji Electric Holdings Co Ltd | Semiconductor device and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01251635A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Dielectric isolation type semiconductor device |
-
1989
- 1989-10-30 JP JP1282396A patent/JPH0687480B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01251635A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Dielectric isolation type semiconductor device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5298449A (en) * | 1992-03-06 | 1994-03-29 | Nec Corporation | Semiconductor substrate having a silicon-on-insulator structure and method of fabricating the same |
| JPH06204331A (en) * | 1993-09-24 | 1994-07-22 | Nippon Soken Inc | Semiconductor device |
| US5374582A (en) * | 1994-04-28 | 1994-12-20 | Nec Corporation | Laminated substrate for semiconductor device and manufacturing method thereof |
| US5847438A (en) * | 1995-03-31 | 1998-12-08 | Nec Corporation | Bonded IC substrate with a high breakdown voltage and large current capabilities |
| US5985681A (en) * | 1995-10-13 | 1999-11-16 | Nec Corporation | Method of producing bonded substrate with silicon-on-insulator structure |
| US6930359B2 (en) | 1999-11-18 | 2005-08-16 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US7588973B2 (en) | 1999-11-18 | 2009-09-15 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| JP2006128230A (en) * | 2004-10-27 | 2006-05-18 | Fuji Electric Holdings Co Ltd | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0687480B2 (en) | 1994-11-02 |
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