JPH0314264A - Semiconductor storage device and its manufacture - Google Patents
Semiconductor storage device and its manufactureInfo
- Publication number
- JPH0314264A JPH0314264A JP1148447A JP14844789A JPH0314264A JP H0314264 A JPH0314264 A JP H0314264A JP 1148447 A JP1148447 A JP 1148447A JP 14844789 A JP14844789 A JP 14844789A JP H0314264 A JPH0314264 A JP H0314264A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- film
- insulating film
- silicon film
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000003990 capacitor Substances 0.000 claims abstract description 27
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000015654 memory Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 230000003416 augmentation Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
この発明は半導体記憶装置に係り、特にトレンチキャパ
シタを持つ半導体記憶装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a trench capacitor.
（従来の技術）
半導体記憶装置の高集積化が進むにつれてダイナミック
メモリ等では、寸法を微細化する必要が生じてきており
このため面積も縮小化されキャパシタ容量が小さくなっ
てしまうという不具合が生じてきた。そこで、この不具
合を改善するためにキャパシタ領域に溝を形成し、この
溝に形成された酸化）摸全利用することによりキャパシ
タのＳ！全増大させる技術が用いられるようになった。(Prior Art) As semiconductor memory devices become more highly integrated, it becomes necessary to miniaturize the dimensions of dynamic memories and the like, which leads to problems such as reduction in area and reduction in capacitor capacity. Ta. Therefore, in order to improve this problem, a groove is formed in the capacitor region, and by fully utilizing the oxide formed in this groove, the S of the capacitor is improved. Total augmentation techniques are now being used.
紀３図に従来例の溝堀り型（トレンチ）キャパシタの製
造方法を示す。Figure 3 shows a method for manufacturing a conventional trench capacitor.
ｐ型シリコン基板２１にレジストを塗布後パターングし
、これをマスクにして異方性エツチングにより溝２２を
形成する。次に熱酸化により、この溝２２全覆ってｐ型
シリコン基板２１全面に５ｉｎ２膜２３を形成する。（
第３図（ａ））次に、溝２２内の表面全面を覆ってｐ型
シリコン基板２１全面に電極としての第１の多結晶シリ
コン膜２４を形成する。次にこの溝２２内の第１の多結
晶シリコン膜２４にリンを拡散させる。After coating a p-type silicon substrate 21 with a resist, patterning is performed, and using this as a mask, grooves 22 are formed by anisotropic etching. Next, a 5in2 film 23 is formed on the entire surface of the p-type silicon substrate 21, completely covering the trench 22, by thermal oxidation. (
(FIG. 3(a)) Next, a first polycrystalline silicon film 24 as an electrode is formed on the entire surface of the p-type silicon substrate 21, covering the entire surface inside the groove 22. Next, phosphorus is diffused into the first polycrystalline silicon film 24 within this groove 22.
次に、熱酸化により第１の多結晶シリコン膜２４の表面
にＳｉＯ□膜２５ｆ：形成する。（第３図（ｂ））
次に、ｐ型シリコン基板２１全而に厚く第２の多結晶シ
リコン膜２６全形成し、エッチバンクして溝２２内に第
２の多結晶シリコン膜２６を埋め込み平坦化する。（第
３ン１（Ｃ１）
次に、この平坦化された多結晶シリコン膜２４゜２６の
表面よｆｉ １１７全拡散させる。（第３図（ｄ））以
上の様にトレンチ型ギヤバッタの製造方法においては、
電極としての第１の多結晶シリコン膜２４表面を酸化後
、更に第２の多結晶シリコン膜２６を堆積し溝２２内に
のみ第２の多結晶シリコン膜２６を残置させるためドラ
イエツチング等によるエッチパックを行なうという複雑
な工程を取っていた。捷だ、多結晶シリコン膜２４．２
６に不純物を導入するだめ、２度のリン拡散が必要であ
った。Next, a SiO□ film 25f is formed on the surface of the first polycrystalline silicon film 24 by thermal oxidation. (FIG. 3(b)) Next, a thick second polycrystalline silicon film 26 is entirely formed on the entire p-type silicon substrate 21, and the second polycrystalline silicon film 26 is buried in the groove 22 by etching banks. Flatten. (3rd N1 (C1)) Next, fi 117 is completely diffused from the surface of this flattened polycrystalline silicon film 24°26. (Fig. 3(d)) As described above, the trench type gear batter is manufactured. In,
After oxidizing the surface of the first polycrystalline silicon film 24 serving as an electrode, a second polycrystalline silicon film 26 is further deposited and etched by dry etching or the like to leave the second polycrystalline silicon film 26 only in the groove 22. It involved a complicated process of packing. Good luck, polycrystalline silicon film 24.2
In order to introduce impurities into 6, two phosphorus diffusions were required.
（発明が解決しようとする課題）
以上の様に従来のトレンチ型キャパシタの製造方法にお
いては、第１の多結晶シリコン膜形成後の酸化工程及び
第２の多結晶シリコンの埋め込み工程等が必要となり、
製造工程が多くなり、また２度のリン拡散全必要とし、
製造コストを増大させるという問題点があった。(Problems to be Solved by the Invention) As described above, in the conventional trench capacitor manufacturing method, an oxidation step after forming the first polycrystalline silicon film, a second polycrystalline silicon filling step, etc. are required. ,
The number of manufacturing steps is increased, and two phosphorus diffusion steps are required.
There was a problem in that the manufacturing cost increased.
本発明は、この様な課題を解決するトレンチキャパシタ
の構造及び製造方法を提供することを目的とする。An object of the present invention is to provide a trench capacitor structure and manufacturing method that solves these problems.
（課題を解決するための手段）
本発明は上記事情に鑑みて為されたもので、第１の発明
は、半導体基板に形成された溝と、この溝を含む基板表
面に絶縁膜を介して溝巾の１／２より薄い膜厚で形成さ
れた多結晶シリコン膜からなるキャパシタ電極と、前記
溝内の前記多結晶シリコン膜表面に形成された高濃度に
不純物を含む絶縁膜と、前記半導体基板の平坦部上にゲ
ート絶縁膜を介して形成されたゲート電極と、前記キャ
パシタ電極とゲート電極間、及びゲート電極に対して前
記キャパシタ電極とけ反対側の前記半導体基板表面に形
成されたソース、ドレイン領域とを具備したことを特徴
とする半導体記憶装置を提供する。(Means for Solving the Problems) The present invention has been made in view of the above-mentioned circumstances, and the first invention is based on a groove formed in a semiconductor substrate and an insulating film formed on the surface of the substrate including the groove. a capacitor electrode made of a polycrystalline silicon film formed with a film thickness thinner than 1/2 of the trench width; an insulating film containing impurities at a high concentration formed on the surface of the polycrystalline silicon film in the trench; and the semiconductor a gate electrode formed on a flat part of the substrate via a gate insulating film, a source formed between the capacitor electrode and the gate electrode, and on the surface of the semiconductor substrate on the opposite side of the capacitor electrode with respect to the gate electrode; Provided is a semiconductor memory device characterized by comprising a drain region.
寸だ、第２の発明は、半導体基板に溝を形成する工程と
、この満を含む基板表面に絶縁ｊ］いを介して溝巾の１
／２より薄い膜厚でキャパシタ電極となる多結晶シリコ
ン膜を形成する工程と、この多結晶シリコン膜表面に高
濃度に不純物を含む絶縁膜を形成する工程と、熱処理に
より前記多結晶シリコン膜に不純物を導入する工程と、
エツチング処理により前記不純物を含む絶縁膜全前記溝
にのみ残置させる工程と、前記半導体基板の平坦部上に
ゲート絶縁膜を介してゲート電極を形成する工程と、前
記キャパシタ電極とゲート電極間、及びゲート電極に対
して前記キャパシタ電極とは反対側の前記半導体基板表
面にソース、ドレイン領域を形成する工程とを具備した
ことを特徴とする半導体記憶装置の製造方法を提供する
。The second invention involves the process of forming a groove in a semiconductor substrate, and the process of forming a groove by one part of the width of the groove through an insulating layer on the surface of the substrate including the semiconductor substrate.
A process of forming a polycrystalline silicon film to serve as a capacitor electrode with a film thickness thinner than /2, a process of forming an insulating film containing impurities at a high concentration on the surface of this polycrystalline silicon film, and a heat treatment to transform the polycrystalline silicon film into a step of introducing impurities;
a step of leaving the entire insulating film containing impurities only in the trench by etching; a step of forming a gate electrode on a flat part of the semiconductor substrate via a gate insulating film; There is provided a method of manufacturing a semiconductor memory device, comprising the step of forming source and drain regions on the surface of the semiconductor substrate on the opposite side of the capacitor electrode with respect to the gate electrode.
（作用）
この様に、第１．第２の発明によれば、トレンチ型キャ
パシタの製造工程において埋め込み工程を簡略化できる
。(Effect) In this way, the first. According to the second invention, the embedding process can be simplified in the trench type capacitor manufacturing process.
（実施例）
以下、本発明の実施例について図面全参照して説明する
。(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to all the drawings.
第１図は本発明の実施例のトレンチ型キャパシタを有す
るダイナミックメモリの断面図である。FIG. 1 is a sectional view of a dynamic memory having a trench type capacitor according to an embodiment of the present invention.
ｐ型シリコン基板１上には素子分離のだめのフィールド
酸化膜２が形成されている。また、ｐ型シリコン基板１
の素子形成領域には、レジストバクーンをマスクに異方
性エツチングを用いて幅１μｍ程度の溝３が形成されて
いる。また、ｐ型シリコン基板１表面には熱酸化により
熱酸化膜４が形成されている。更に、この熱酸化膜４表
面には膜厚４０００Ａ程度の多結晶シリコン膜５が形成
されている。更にこの溝３中の多結晶シリコン膜５表面
には、高濃度、の不純物としてリンを含んだＰＳＧ膜６
が形成され、この溝３が埋め込まれている。A field oxide film 2 for element isolation is formed on a p-type silicon substrate 1. In addition, p-type silicon substrate 1
In the element forming region, a groove 3 having a width of about 1 μm is formed by anisotropic etching using a resist film as a mask. Further, a thermal oxide film 4 is formed on the surface of the p-type silicon substrate 1 by thermal oxidation. Furthermore, a polycrystalline silicon film 5 having a thickness of about 4000 Å is formed on the surface of this thermal oxide film 4. Further, on the surface of the polycrystalline silicon film 5 in this groove 3, a PSG film 6 containing phosphorus as an impurity at a high concentration is formed.
is formed, and this groove 3 is filled.
この多結晶シリコン膜５に隣接した部分には、ＭＯＳト
ランジスタが形成されている。即ち、露出したｐ型シリ
コン基板１上には、ゲート酸化膜７が形成され、更にそ
の上には、多結晶シリコン膜より成るゲート電極８が設
けられている。また、ヒ素のイオン注入によりｐ型シリ
コン基板表面にソース／ドレイン領域９が形成されてい
る。また、ＭＯＳトランジスタ、トレンチキャパシタ上
全面にわたって層間絶縁膜１０が形成されている。また
ドレイン／ソース領域９のいずれか一方にはコンタクト
孔が設けられＡｔから成るビット線１１が形成されてい
る。A MOS transistor is formed in a portion adjacent to this polycrystalline silicon film 5. That is, a gate oxide film 7 is formed on the exposed p-type silicon substrate 1, and a gate electrode 8 made of a polycrystalline silicon film is further provided thereon. Furthermore, source/drain regions 9 are formed on the surface of the p-type silicon substrate by arsenic ion implantation. Further, an interlayer insulating film 10 is formed over the entire surface of the MOS transistor and trench capacitor. Further, a contact hole is provided in either one of the drain/source regions 9, and a bit line 11 made of At is formed.
第２図は本発明の実施例のトレンチ型キャパシタ全有す
るダイナミックメモリの製造工程を工程順に断面図で示
したものである。FIG. 2 is a cross-sectional view showing the manufacturing process of a dynamic memory having all trench type capacitors according to an embodiment of the present invention.
ｐ型シリコン基板１上に素子分離のだめのフィールド酸
化膜２を形成する。次にレジス）ｋ塗布後パターニング
しこれをマスクにして素子形成領域に幅１μｍ程度の溝
３を設ける。次に、ｐ型シ〕コン基板１表面を熱酸化す
ることにより幅１００穴程度のゲート酸化膜４を形成す
る。（第２図（ａ））次に、このゲート酸化膜４表面に
幅４０００Ａ程度の多結晶シリコン膜５全形成し、更に
リン全ｌＸ１０２１ｍ−３程度含ムＰ Ｓ ＧＩＩＫ
６ ｋ ４０００ｃｋ程１ｉ形成する。（第２図（ｂ）
）
次に、例えは９５０℃、６０分間、Ｐ ＯＣｔ ３によ
るリンの雰囲気下で熱処理を加える。この熱処理により
多結晶シリコン膜５には、リンが拡散され、同時に溝３
内のＰＳＧ膜６はリフローにより完全に埋め込まれ表面
平坦部のＰＳＧ膜６は形成時に比べ薄くなる。（第２図
（Ｃ））
次に、ＮＨ４Ｆ液等を用いて溝３以外に形成されたＰＳ
Ｇ膜６を除去する。続いて、ＭＯＳトランジスタ形成域
の多結晶シリコン膜５、熱酸化膜４を除去し、ｐ型シリ
コン基板１を露出させる。次に熱酸化によりｐ型シリコ
ン基板１上にゲート酸化膜７を形成する。次に多結晶シ
リコン膜からなるゲート電極８を形成する。次にヒ素の
イオン注入によりソース／ドレイン領域９を形成する。A field oxide film 2 for element isolation is formed on a p-type silicon substrate 1. Next, after applying a resist (resist) k, patterning is performed, and using this as a mask, grooves 3 having a width of about 1 μm are formed in the element formation region. Next, the surface of the p-type silicon substrate 1 is thermally oxidized to form a gate oxide film 4 having a width of about 100 holes. (FIG. 2(a)) Next, the entire polycrystalline silicon film 5 with a width of about 4000 A is formed on the surface of this gate oxide film 4, and a polycrystalline silicon film 5 containing about 1×1021 m−3 of phosphorus is further formed on the surface of this gate oxide film 4.
6k 4000ck of 1i is formed. (Figure 2(b)
) Next, heat treatment is applied, for example, at 950° C. for 60 minutes in an atmosphere of phosphorus using P OCt 3 . Through this heat treatment, phosphorus is diffused into the polycrystalline silicon film 5, and at the same time, the grooves 3
The inner PSG film 6 is completely buried by reflow, and the PSG film 6 on the flat surface becomes thinner than when it was formed. (Fig. 2 (C)) Next, PS formed in areas other than groove 3 using NH4F liquid etc.
G film 6 is removed. Subsequently, the polycrystalline silicon film 5 and thermal oxide film 4 in the MOS transistor formation region are removed to expose the p-type silicon substrate 1. Next, a gate oxide film 7 is formed on the p-type silicon substrate 1 by thermal oxidation. Next, a gate electrode 8 made of a polycrystalline silicon film is formed. Next, source/drain regions 9 are formed by arsenic ion implantation.
次に、トレンチキャバシク、ＭＯＳトランジスタ上全面
に層間絶縁膜１０を形成する。次に、ドレイン／ソース
領域９上のいずれか一方にコンタクト孔を設け、Ｍから
成るビット線１１を形成する。（第２図（ｄ））
以上の様なトレンチ型キャパシタダイナミックメモリの
製造方法においては、従来例と異なり、多結晶シリコン
膜形成後の酸化工程及び落２の多結晶シリコンの埋め込
み工程等がなく、捷だリン拡散も一度で済むため製造工
程の簡略化をはかυながら信頼性の高い製品を得ること
が可能となる。Next, an interlayer insulating film 10 is formed over the entire surface of the trench cabassic and MOS transistor. Next, a contact hole is provided on either side of the drain/source region 9, and a bit line 11 made of M is formed. (Fig. 2(d)) Unlike the conventional method, the method for manufacturing a trench type capacitor dynamic memory as described above does not require an oxidation process after forming a polycrystalline silicon film and a process of embedding polycrystalline silicon in step 2. Since only one phosphorus diffusion is required, it is possible to simplify the manufacturing process and obtain highly reliable products.
以上の様に本発明によればトレンチ型キャパシタの製造
工程を簡略化でき、信頼性の渦い製品を得ることが可能
となる。As described above, according to the present invention, the manufacturing process of a trench type capacitor can be simplified and a reliable product can be obtained.
第１図は、本発明の実施例の半導体記憶装置の断面図、
第２図は本発明の実施例の半導体記憶装置の製造工程図
、第３図は、従来例の半導体記憶装置の製造工程図であ
る。
図において、
１・・・ｐ型シリコン基板、２・・・フィールド酸化膜
、３・・・溝、４・・・熱酸化膜、５・・・多結晶シリ
コン膜、６・・・ＰＳＧ膜、７・・・ゲート酸化膜、８
・・・ゲート電極、９・・・ソース／ドレイン領域、１
０・・・層間絶縁膜、１１・・・ビット線、２１・・ｐ
型／リコン基板、２２・・・溝、２３・・・５ｉ０２１
逆、２４・・・第１の多結晶シリコン膜、
２
５・・・ＳｉＯ□膜、
６・・・第２の多結
晶シリコン膜、
７・・・ＰＳＧ膜。FIG. 1 is a sectional view of a semiconductor memory device according to an embodiment of the present invention;
FIG. 2 is a manufacturing process diagram of a semiconductor memory device according to an embodiment of the present invention, and FIG. 3 is a manufacturing process diagram of a conventional semiconductor memory device. In the figure, 1...p-type silicon substrate, 2...field oxide film, 3...trench, 4...thermal oxide film, 5...polycrystalline silicon film, 6...PSG film, 7... Gate oxide film, 8
...gate electrode, 9...source/drain region, 1
0...Interlayer insulating film, 11...Bit line, 21...p
Mold/recon board, 22...groove, 23...5i021
Reverse, 24...first polycrystalline silicon film, 25...SiO□ film, 6...second polycrystalline silicon film, 7...PSG film.
Claims (2)
表面に絶縁膜を介して溝巾の１／２より薄い膜厚で形成
された多結晶シリコン膜からなるキャパシタ電極と、前
記溝内の前記多結晶シリコン膜表面に形成された高濃度
に不純物を含む絶縁膜と、前記半導体基板の平坦部上に
ゲート絶縁膜を介して形成されたゲート電極と、前記キ
ャパシタ電極とゲート電極間、及びゲート電極に対して
前記キャパシタ電極とは反対側の前記半導体基板表面に
形成されたソース、ドレイン領域とを具備したことを特
徴とする半導体記憶装置。(1) A groove formed in a semiconductor substrate, a capacitor electrode made of a polycrystalline silicon film formed with a film thickness thinner than 1/2 of the groove width on the substrate surface including the groove via an insulating film, and the groove an insulating film containing impurities at a high concentration formed on the surface of the polycrystalline silicon film; a gate electrode formed on the flat part of the semiconductor substrate via a gate insulating film; and between the capacitor electrode and the gate electrode. , and source and drain regions formed on the surface of the semiconductor substrate on the opposite side of the capacitor electrode with respect to the gate electrode.
基板表面に絶縁膜を介して溝巾の１／２より薄い膜厚で
キャパシタ電極となる多結晶シリコン膜を形成する工程
と、この多結晶シリコン膜表面に高濃度に不純物を含む
絶縁膜を形成する工程と、熱処理により前記多結晶シリ
コン膜に不純物を導入する工程と、エッチング処理によ
り前記不純物を含む絶縁膜を前記溝にのみ残置させる工
程と、前記半導体基板の平担部上にゲート絶縁膜を介し
てゲート電極を形成する工程と、前記キャパシタ電極と
ゲート電極間、及びゲート電極に対して前記キャパシタ
電極とは反対側の前記半導体基板表面にソース、ドレイ
ン領域を形成する工程とを具備したことを特徴とする半
導体記憶装置の製造方法。(2) a step of forming a groove in a semiconductor substrate; a step of forming a polycrystalline silicon film that will become a capacitor electrode with a thickness thinner than 1/2 of the groove width on the surface of the substrate including the groove, with an insulating film interposed therebetween; A step of forming an insulating film containing impurities at a high concentration on the surface of this polycrystalline silicon film, a step of introducing impurities into the polycrystalline silicon film by heat treatment, and a step of etching the insulating film containing the impurities only into the grooves. a step of forming a gate electrode on the flat part of the semiconductor substrate via a gate insulating film; A method for manufacturing a semiconductor memory device, comprising the step of forming source and drain regions on the surface of the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1148447A JPH0314264A (en) | 1989-06-13 | 1989-06-13 | Semiconductor storage device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1148447A JPH0314264A (en) | 1989-06-13 | 1989-06-13 | Semiconductor storage device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0314264A true JPH0314264A (en) | 1991-01-22 |
Family
ID=15452995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1148447A Pending JPH0314264A (en) | 1989-06-13 | 1989-06-13 | Semiconductor storage device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0314264A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9220376B2 (en) | 2008-12-17 | 2015-12-29 | Toto Ltd. | Shower apparatus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5818804U (en) * | 1981-07-30 | 1983-02-05 | 日産自動車株式会社 | strut type rear suspension |
| JPS61200013A (en) * | 1985-02-28 | 1986-09-04 | バイエリツシエ モートーレン ウエルケ アクチエンゲゼルシヤフト | Rear wheel suspension system, particularly, suspension system of driven rear wheel, for automobile |
| JPH0274408A (en) * | 1988-09-09 | 1990-03-14 | Mazda Motor Corp | Suspension device for vehicle |
-
1989
- 1989-06-13 JP JP1148447A patent/JPH0314264A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5818804U (en) * | 1981-07-30 | 1983-02-05 | 日産自動車株式会社 | strut type rear suspension |
| JPS61200013A (en) * | 1985-02-28 | 1986-09-04 | バイエリツシエ モートーレン ウエルケ アクチエンゲゼルシヤフト | Rear wheel suspension system, particularly, suspension system of driven rear wheel, for automobile |
| JPH0274408A (en) * | 1988-09-09 | 1990-03-14 | Mazda Motor Corp | Suspension device for vehicle |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9220376B2 (en) | 2008-12-17 | 2015-12-29 | Toto Ltd. | Shower apparatus |
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