JPH0314172B2 - - Google Patents
Info
- Publication number
- JPH0314172B2 JPH0314172B2 JP2871981A JP2871981A JPH0314172B2 JP H0314172 B2 JPH0314172 B2 JP H0314172B2 JP 2871981 A JP2871981 A JP 2871981A JP 2871981 A JP2871981 A JP 2871981A JP H0314172 B2 JPH0314172 B2 JP H0314172B2
- Authority
- JP
- Japan
- Prior art keywords
- resist
- layer
- pattern
- electron beam
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 25
- 239000011347 resin Substances 0.000 claims description 24
- 229920005989 resin Polymers 0.000 claims description 24
- 238000010894 electron beam technology Methods 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 10
- 239000000203 mixture Substances 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 59
- 239000007789 gas Substances 0.000 description 25
- 238000005530 etching Methods 0.000 description 17
- 239000010408 film Substances 0.000 description 17
- 239000010409 thin film Substances 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 238000000059 patterning Methods 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- -1 chalcogenide compound Chemical class 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 229910005866 GeSe Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- KYKAJFCTULSVSH-UHFFFAOYSA-N chloro(fluoro)methane Chemical compound F[C]Cl KYKAJFCTULSVSH-UHFFFAOYSA-N 0.000 description 1
- 125000004773 chlorofluoromethyl group Chemical group [H]C(F)(Cl)* 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000007733 ion plating Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000025 natural resin Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- 231100000331 toxic Toxicity 0.000 description 1
- 230000002588 toxic effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Drying Of Semiconductors (AREA)
- Electron Beam Exposure (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【発明の詳細な説明】
本発明は段差のある半導体基板上へのレジスト
パターンの形成方法に係り、更に詳しくは半導
体、IC、LSI、超LSI等の製造において、段差の
ある半導体基板上に解像度の高いレジストパター
ンを得るリソグラフイー方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a resist pattern on a semiconductor substrate with steps, and more specifically, in the production of semiconductors, ICs, LSIs, VLSIs, etc., the present invention relates to a method for forming a resist pattern on a semiconductor substrate with steps. The present invention relates to a lithographic method for obtaining resist patterns with high resistance.
半導体装置、特に大容量集積回路では多層配線
により内部接続を行ない集積度を向上させてい
る。多層配線は通常熱酸化又は気相成長のSiO2
を絶縁層としており、この絶縁層に層間接続用の
孔をあけて上層の配線を設けており、配線金属は
SiO2との密着性及び導電率の点からAlが多く用
いられている。一般に配線金属とSiO2は、それ
ぞれ1μｍ前後の厚さで層が形成されている。と
ころで、最近のLSI、超LSIの動きに伴い、1μｍ
前後の微細パターンが必要とされるようになつて
きた。通常、平坦な基板面上でのリソグラフイー
では、レジストと市販装置、例えば電子ビーム露
光装置などを用いることにより、レジスト層が均
一である限り1μｍ前後のパターニングは可能で
ある。 BACKGROUND ART In semiconductor devices, especially large-capacity integrated circuits, internal connections are made using multilayer wiring to improve the degree of integration. Multilayer wiring is usually made of SiO 2 by thermal oxidation or vapor phase growth.
is used as an insulating layer, and the upper layer wiring is provided by making holes for interlayer connections in this insulating layer, and the wiring metal is
Al is often used because of its adhesion to SiO 2 and its electrical conductivity. Generally, wiring metal and SiO 2 are each formed into layers with a thickness of about 1 μm. By the way, with the recent movement of LSI and super LSI, 1μm
Fine patterns on the front and back have come to be required. Normally, in lithography on a flat substrate surface, patterning of around 1 μm is possible as long as the resist layer is uniform by using a resist and a commercially available device such as an electron beam exposure device.
しかしながら、基板面の凹凸のある場合、例え
ば1μｍの段差を有するSiO2上にレジスト・パタ
ーニングをする場合には、レジスト厚はウエーハ
内で不均一となり、1μｍ前後のパターニングを
することは不可能であつた。一方、金属のような
反射率の大きい基板、例えばAlの上にレジスト
パターニングをする場合には、紫外線露光の際光
の定在波が発生し、露光強度が不均一化し、1μ
ｍ前後のパターニングをすることが困難である。 However, if the substrate surface is uneven, for example, when resist patterning is performed on SiO 2 with a step of 1 μm, the resist thickness will be uneven within the wafer, making it impossible to pattern around 1 μm. It was hot. On the other hand, when resist patterning is performed on a substrate with high reflectivity such as metal, such as Al, standing waves of light are generated during UV exposure, making the exposure intensity non-uniform.
It is difficult to pattern around m.
すなわち、高解像のレジスト画像を得るために
は、レジスト厚を凹凸のある表面を十分に平坦に
カバーするほど厚くせねばならず、一方逆にレジ
スト層が厚いと微細なパターンが解像しないとい
う欠点があり、段差のある基板上に高解像度のレ
ジスト・パターンを得ることは困難であり、かか
る欠点を解消することは重要な課題であつた。 In other words, in order to obtain a high-resolution resist image, the resist must be thick enough to cover the uneven surface sufficiently flatly, whereas on the other hand, if the resist layer is too thick, fine patterns cannot be resolved. This drawback makes it difficult to obtain a high-resolution resist pattern on a substrate with steps, and solving this drawback has been an important issue.
上記の欠点を解消した方法として、最近第１図
ａないしｃに図示するような三層構造法がとられ
ている。即ち、第１図ａに示す如く段差のある基
板１上に厚膜レジスト層２を厚さ２〜3μｍ塗布
して設けることにより、、ウエーハ表面に凹凸が
あつてもレジスト表面を平坦化し、この厚膜レジ
スト膜２上に、絶縁膜３、例えばSiO2、Si3N4、
B2N3を積層してマスキング層とし、更に最上層
に薄膜レジスト層４を設ける。最上層の薄膜レジ
スト層４をノンコンタクトでパターニング後、最
上層、パターン化した薄膜レジスト層４をマスク
として絶縁膜３をエツチング・ガス５を用いてド
ライ・エツチングする。次に絶縁膜３をマスクと
して、最下層の厚膜レジスト層２を酸素ガス６雰
囲気下でドライエツチングし、サイドエツチの少
ない食刻部分の側壁の急峻なレジストパターンを
得る。 As a method for solving the above-mentioned drawbacks, a three-layer structure method as shown in FIGS. 1a to 1c has recently been adopted. That is, by coating a thick film resist layer 2 to a thickness of 2 to 3 μm on a substrate 1 with steps as shown in FIG. An insulating film 3 such as SiO 2 , Si 3 N 4 ,
B 2 N 3 is laminated to form a masking layer, and a thin film resist layer 4 is further provided as the uppermost layer. After patterning the uppermost thin film resist layer 4 without contact, the insulating film 3 is dry etched using the etching gas 5 using the uppermost patterned thin film resist layer 4 as a mask. Next, using the insulating film 3 as a mask, the lowermost thick film resist layer 2 is dry etched in an atmosphere of oxygen gas 6 to obtain a resist pattern with a steep sidewall of the etched portion with little side etching.
しかしながら、前記したような三層構造法は工
程が長く複雑である欠点を有する。そこで更に工
程を短かくした二層構造法が行なわれた。即ち、
半導体基板上に２〜3μｍ厚のレジスト層を設け、
更にその上に感光性を有するカルコゲナイド化合
物、例えばGeSe2又はAg2Se等の薄膜層を設け
る。下層のレジスト層で平坦化を行ない、且つ上
層の薄膜層により微細パターニングを行なうこと
により、凹凸のある基板又は反射率の大きい基板
でも非常に高い解像度を得る。 However, the three-layer structure method described above has the disadvantage that the process is long and complicated. Therefore, a two-layer structure method was used that further shortened the process. That is,
A resist layer with a thickness of 2 to 3 μm is provided on the semiconductor substrate,
Furthermore, a thin film layer of a photosensitive chalcogenide compound such as GeSe 2 or Ag 2 Se is provided thereon. By performing planarization with the lower resist layer and performing fine patterning with the upper thin film layer, extremely high resolution can be obtained even on substrates with irregularities or high reflectance.
しかし、上記カルコゲナイド化合物を用いる二
層方法は、カルコゲナイド化合物が人体に対して
毒性を有すること、シリコン・ウエーハに対して
不純物として作用し、半導体、IC、LSIの特性を
劣化させる危険性があることなど大きな欠点を有
する。 However, the two-layer method using chalcogenide compounds has the disadvantage that chalcogenide compounds are toxic to the human body, act as impurities on silicon wafers, and risk deteriorating the characteristics of semiconductors, ICs, and LSIs. It has major drawbacks such as:
本発明者は叙上の欠点を解消すべく研究の結
果、段差のある半導体基板の表面に段差がなくな
り、表面が平坦化するように樹脂を塗布し、しか
るのち、形成された樹脂層上にシリコンとシリコ
ン酸化物の混合物を主成分とする電子線感応性無
機レジスト層を設け、前記無機レジスト層に電子
線をパターン照射、即ち、パターン状に部分照射
した後、前記無機レジストを現像して、パターン
化した無機レジスト層を得、次いでこのパターン
化した無機レジスト層をマスクとして露出した樹
脂層部分をドライエツチングして前記樹脂層部分
を除去する方法によれば、レジスト材料による汚
染を生ぜしめることなく、高解像度で且つ高加工
精度にレジストパターンを段差のある半導体基板
上に形成することができることを見いだし、かか
る知見にもとづいて本発明を完成したものであ
る。 As a result of research to eliminate the above-mentioned drawbacks, the inventor of the present invention applied a resin so that the surface of a semiconductor substrate with a step has no steps and the surface becomes flat, and then coats the resin layer on the formed resin layer. An electron beam-sensitive inorganic resist layer containing a mixture of silicon and silicon oxide as a main component is provided, and after the inorganic resist layer is irradiated with an electron beam in a pattern, that is, partially irradiated in a pattern, the inorganic resist is developed. According to the method of obtaining a patterned inorganic resist layer and then dry etching the exposed resin layer portion using the patterned inorganic resist layer as a mask to remove the resin layer portion, contamination by the resist material may occur. The inventors have discovered that it is possible to form a resist pattern with high resolution and high processing accuracy on a semiconductor substrate with steps without any problems, and have completed the present invention based on this knowledge.
即ち、本発明の要旨は段差のある半導体基板の
表面に段差がなくなり、表面が平坦化するように
樹脂を塗布し、しかるのち、形成された樹脂層上
にシリコンとシリコン酸化物の混合物を主成分と
する電子線感応性無機レジスト層を設け、前記無
機レジスト層に電子線をパターン照射した後、前
記無機レジストを現像してパターン化した無機レ
ジスト層を得、次いでこのパターン化した無機レ
ジスト層をマスクとして露出した樹脂層部分をド
ライエツチングして前記樹脂層部分を除去するこ
とを特徴とする段差のある半導体基板上へのレジ
ストパターンの形成方法である。 That is, the gist of the present invention is to apply a resin to the surface of a semiconductor substrate with steps so that the steps are eliminated and the surface becomes flat, and then to coat the formed resin layer with a mixture of silicon and silicon oxide. After providing an electron beam-sensitive inorganic resist layer as a component and irradiating the inorganic resist layer with an electron beam in a pattern, the inorganic resist is developed to obtain a patterned inorganic resist layer, and then this patterned inorganic resist layer This method of forming a resist pattern on a semiconductor substrate having steps is characterized in that the exposed resin layer portion is removed by dry etching using the resist pattern as a mask.
以下、本発明について詳細に説明する。本発明
に係る方法について第２図の如く図面を用いて説
明すると、第２図ａに示す如く、段差のある半導
体基板１上に樹脂溶液を塗布した後、溶剤を乾燥
させて、２〜3μｍ程度の膜厚を有する樹脂層７
をを形成する。樹脂層７を形成する材料として
は、通常の天然樹脂及び合成樹脂が用いられる
が、半導体基板へのNa等による不純物汚染防止、
ゴミ、異物を含まない等の条件が必要とされるの
で、一般に半導体関係で用いられるフオトレジス
ト、電子線レジスト等が望ましい。例えば、フオ
トレジストとして、AZ−1450J（シツプレー社製）
OMR−85（東京応化工業社製）、電子線レジスト
として例えばポリメチルメタアクリレートがあげ
られる。樹脂層７を半導体基板１に塗布するには
種々の方法があるが、塗布膜を均一にする点でス
ピンナー塗布が最適である。次に第２図ｂに示す
如く、樹脂層７上に無機レジスト層８を形成す
る。無機レジスト層８はシリコンとシリコン酸化
物との混合物を主成分とする電子線感応性薄膜層
であり、蒸着又はスパッタリング又はイオンプレ
ーテイング等通常の方法により形成する。無機レ
ジスト層８においてはシリコン１に対しシリコン
酸化物（SiOx；Ｏ＜ｘ＜２）が重量比で５以下
であることが好ましく、且つ無機レジスト層８は
膜厚500〜5000Åの範囲で用いることが可能であ
り、又、電子線照射量10-2〜10-6クーロン／cm2の
範囲で用いることができる。第２図ｃは無機レジ
スト層８を電子線９でパターン描画している状態
を示す。次に第２図ｄに示す如く、電子線でパタ
ーン描画した無機レジスト層８を現像する。現像
は、ウエツトエツチング又はドライエツチングの
いずれでも可能であるが、工程的にはドライエツ
チングの方が望ましい。ドライエツチングプロセ
スとしてはプラズマエツチング、反応性イオンエ
ツチング等が使用可能である。プラズマエツチン
グは、シリコンのエツチングガスが全て使用可能
であり、CF4、CHClF2、CCl2F2、CHCl2F、
CClF3等のフレオンガス及びフレオンガスとO2ガ
スの混合ガスが特に有効である。 The present invention will be explained in detail below. The method according to the present invention will be explained using a drawing as shown in FIG. 2. As shown in FIG. 2a, a resin solution is applied onto a semiconductor substrate 1 having a step, and then the solvent is dried to form a layer of 2 to 3 μm. Resin layer 7 having a film thickness of about
to form. As the material for forming the resin layer 7, ordinary natural resins and synthetic resins are used, but it is necessary to prevent impurity contamination by Na etc. on the semiconductor substrate,
Since conditions such as not containing dust or foreign matter are required, photoresists, electron beam resists, etc., which are generally used in semiconductors, are desirable. For example, as a photoresist, AZ-1450J (manufactured by Situpre Co., Ltd.)
Examples of the electron beam resist include OMR-85 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) and polymethyl methacrylate. Although there are various methods for applying the resin layer 7 to the semiconductor substrate 1, spinner application is optimal in terms of making the applied film uniform. Next, as shown in FIG. 2b, an inorganic resist layer 8 is formed on the resin layer 7. The inorganic resist layer 8 is an electron beam sensitive thin film layer mainly composed of a mixture of silicon and silicon oxide, and is formed by a conventional method such as vapor deposition, sputtering, or ion plating. In the inorganic resist layer 8, it is preferable that the weight ratio of silicon oxide (SiOx; O<x<2) to 1 silicon is 5 or less, and the inorganic resist layer 8 is used in a thickness range of 500 to 5000 Å. It is also possible to use an electron beam irradiation amount in the range of 10 -2 to 10 -6 coulombs/cm 2 . FIG. 2c shows a state in which a pattern is drawn on the inorganic resist layer 8 using an electron beam 9. Next, as shown in FIG. 2d, the inorganic resist layer 8 pattern-drawn with an electron beam is developed. Development can be done by either wet etching or dry etching, but dry etching is more desirable from a process standpoint. As the dry etching process, plasma etching, reactive ion etching, etc. can be used. All silicon etching gases can be used for plasma etching, including CF 4 , CHClF 2 , CCl 2 F 2 , CHCl 2 F,
Freon gas such as CClF 3 and a mixed gas of Freon gas and O 2 gas are particularly effective.
プラズマエツチングに用いる装置は、円筒型で
も平行平板型でも良く、ベルジヤー、ガス導入
管、ベルジヤー内でプラズマを発生させる為の高
周波発生装置及び真空ポンプからなつているもの
である。 The apparatus used for plasma etching may be of a cylindrical type or a parallel plate type, and consists of a bell gear, a gas introduction tube, a high frequency generator for generating plasma in the bell gear, and a vacuum pump.
本発明によるパターニング方法を用いた時のシ
リコンとシリコン酸化物との混合物を主成分とす
る薄膜の感度は、ドライエツチング時のガスの種
類及び組成比によつて若干異なるが、１例とし
て、CF4とO2ガスの混合ガスによるプラズマエツ
チングを用いると、CF4とO2の混合比が55対30の
時が最も好ましい条件であつた。ここにおいて無
機レジスト８がパターン化される機構は明らかで
はないが電子線エネルギーによつて照射部分のシ
リコンとシリコン酸化物の混合物の結晶性度合が
変化し、エツチング速度の差が生じて部分的にエ
ツチングされパターン形成されるものと思料され
る。 The sensitivity of a thin film mainly composed of a mixture of silicon and silicon oxide when using the patterning method according to the present invention varies slightly depending on the type and composition ratio of the gas used during dry etching. When using plasma etching with a mixed gas of CF 4 and O 2 gas, the most favorable conditions were when the mixing ratio of CF 4 and O 2 was 55:30. The mechanism by which the inorganic resist 8 is patterned here is not clear, but the degree of crystallinity of the mixture of silicon and silicon oxide in the irradiated area changes depending on the electron beam energy, resulting in a difference in etching rate and partial patterning. It is assumed that the pattern is formed by etching.
次に第２図ｅに示す如く、パターン化した無機
レジスト層８をマスクとして、樹脂層７をエツチ
ングガス１０によりドライエツチングする。樹脂
層７のドライエツチング条件としては、エツチン
グガスとして酸素又は酸素を含む混合ガスを、ガ
ス圧１×10-3〜１×10-2Torrで高周波パワー密
度0.1〜0.5W／cm2で用いるのが適切である。樹脂
層７のドライエツチング速度は、樹脂層の種類、
エツチング装置、エツチング条件により若干異な
るが、一般に1000〜3000Å／minである。樹脂層
７のドライエツチングが完了すれば、第２図ｆに
示す如く、段差のある半導体基板１上にサイドエ
ツチの少ないシヤープなレジストパターンを得
る。 Next, as shown in FIG. 2e, the resin layer 7 is dry-etched with an etching gas 10 using the patterned inorganic resist layer 8 as a mask. The dry etching conditions for the resin layer 7 include using oxygen or a mixed gas containing oxygen as the etching gas at a gas pressure of 1×10 -3 to 1×10 -2 Torr and a high frequency power density of 0.1 to 0.5 W/cm 2 . is appropriate. The dry etching speed of the resin layer 7 depends on the type of resin layer,
Although it varies slightly depending on the etching equipment and etching conditions, it is generally 1000 to 3000 Å/min. When the dry etching of the resin layer 7 is completed, a sharp resist pattern with less side etching is obtained on the semiconductor substrate 1 having steps, as shown in FIG. 2(f).
以上詳記した通り、本発明の方法によれば、レ
ジスト材料による汚染を生ぜしめることなく、高
解像度で且つ高加工精度に、サイドエツチの少な
い、食刻部分の側壁が急峻なレジストパターンを
段差のある半導体基板上に形成することができ
る。又、本発明の方法によれば、最小線巾1μｍ
に至る迄線輻制御を容易に行なうことができる。
更に又、プロセス全体をドライプロセス化するこ
とが可能であり、それ故自動化及び省力化が可能
である。 As described in detail above, according to the method of the present invention, resist patterns with steep sidewalls in etched portions can be formed with high resolution and high processing accuracy without causing contamination by the resist material, and with little side etching. It can be formed on a certain semiconductor substrate. Furthermore, according to the method of the present invention, the minimum line width is 1 μm.
It is possible to easily perform line congestion control up to .
Furthermore, the entire process can be made into a dry process, thus allowing for automation and labor savings.
以下、本発明を実施例をあげて具体的に説明す
る。 Hereinafter, the present invention will be specifically explained with reference to Examples.
実施例 １
シリコン基板上の1μｍの段差を有するSiO2上
にフオトレジストAZ−1450Jを塗布し、乾燥して
厚さ2.5μｍのレジスト膜を得た。次にレジスト膜
上に電子ビーム蒸着法により、シリコンとシリコ
ン酸化物との混合物を主成分とする無機レジスト
薄膜を5000Åの厚さに設けた。電子ビーム蒸着時
の真空度は、１×10-4Torrであり、蒸発源と基
板との距離は50cm、蒸着速度は1000Å／hrであつ
た。Example 1 Photoresist AZ-1450J was coated on SiO 2 having a step of 1 μm on a silicon substrate and dried to obtain a resist film with a thickness of 2.5 μm. Next, an inorganic resist thin film mainly composed of a mixture of silicon and silicon oxide was formed on the resist film by electron beam evaporation to a thickness of 5000 Å. The degree of vacuum during electron beam evaporation was 1×10 −4 Torr, the distance between the evaporation source and the substrate was 50 cm, and the evaporation rate was 1000 Å/hr.
次に電子線照射装置を用いて、無機レジスト薄
膜を加速電圧10kV、照射量１×10-3クーロン／
cm、電子線径0.25μｍでパターン照射した後反応
性イオンエツチング装置によりドライ現像を行つ
た。使用したガスはCF4とO2の55対30の混合ガス
で圧力300ｍTorrである。13.56MH高周波を電力
200Wで用い10分間現像を行い、レジスト残膜厚
2000Å、パターン最小線巾1μｍの平行線パター
ンを歪みなく得た。次にパターン化した無機レジ
スト薄膜をエツチングマスクとして高周波出力
13.56MHz、パワー密度0.3W／cm2、ガス圧４×
10-3Torrの酸素雰囲気中で、露出したフオトレ
ジストAZ−1450Jをドライエツチングし、シリコ
ン基板上のSiO2層を最小線巾1μｍでパターン状
に露出させた。得られたフオトレジストパターン
はサイドエツチが少なく急峻なレジストパターン
であつた。 Next, using an electron beam irradiation device, the inorganic resist thin film was deposited at an acceleration voltage of 10 kV and a radiation dose of 1 × 10 -3 coulombs/
After pattern irradiation with an electron beam diameter of 0.25 μm, dry development was performed using a reactive ion etching device. The gas used was a 55:30 mixture of CF 4 and O 2 at a pressure of 300 mTorr. 13.56MH high frequency power
Developed at 200W for 10 minutes to determine the remaining resist film thickness.
A parallel line pattern of 2000 Å and a minimum pattern line width of 1 μm was obtained without distortion. Next, high frequency output is performed using the patterned inorganic resist thin film as an etching mask.
13.56MHz, power density 0.3W/cm 2 , gas pressure 4×
The exposed photoresist AZ-1450J was dry etched in an oxygen atmosphere of 10 -3 Torr to expose the SiO 2 layer on the silicon substrate in a pattern with a minimum line width of 1 μm. The photoresist pattern obtained was a steep resist pattern with little side etching.
実施例 ２
1μｍの凹凸を有するシリコン基板上の配線用
アルミニウム上に電子線レジストポリメチルメタ
アクリレートを塗布し、乾燥して厚さ2μｍのレ
ジスト膜を得た。次にレジスト膜上に高周波スパ
ツタリング法によりシリコンとシリコンの酸化物
との混合物を主成分とする無機レジスト薄膜を
4000Åの厚さに設けた。スパツタリングガスはア
ルゴンガスを使用し、スパツタリング時のガス圧
は、７×10-2Torr基板とターゲツト電極間距離
は５cm、高周波電力600W、スパツタリング速度
は2000Å／hrであつた。Example 2 Electron beam resist polymethyl methacrylate was coated on aluminum for wiring on a silicon substrate having irregularities of 1 μm, and dried to obtain a resist film with a thickness of 2 μm. Next, a thin inorganic resist film mainly composed of a mixture of silicon and silicon oxide is formed on the resist film using a high-frequency sputtering method.
The thickness was 4000 Å. Argon gas was used as the sputtering gas, the gas pressure during sputtering was 7×10 -2 Torr, the distance between the substrate and the target electrode was 5 cm, the high frequency power was 600 W, and the sputtering speed was 2000 Å/hr.
この方法で作成した無機レジスト薄膜を電子線
照射装置を用いて加速電圧10kV、照射量１×
10-3クーロン／cm2、電子線径0.25μｍでパターン
照射した。次に電子線を照射した無機レジスト薄
膜をプラズマエツチング装置を用いて、エツチン
グガスにCCl2F2とO2の比が３対１の混合ガスを
使用して、ガス圧力500ｍTorr、高周波電力
300Wで20分間ドライ現像を行い、レジスト残膜
厚2000Å、パターン最小線巾1μｍの平行線パタ
ーンを歪みなく得た。 The inorganic resist thin film created by this method was processed using an electron beam irradiation device at an acceleration voltage of 10 kV and a irradiation dose of 1×.
Pattern irradiation was performed at 10 −3 coulombs/cm 2 and an electron beam diameter of 0.25 μm. Next, the inorganic resist thin film irradiated with an electron beam is etched using a plasma etching device using a mixed gas of CCl 2 F 2 and O 2 with a ratio of 3:1 as the etching gas, gas pressure of 500 mTorr, and high frequency power.
Dry development was performed at 300W for 20 minutes to obtain a parallel line pattern with a residual resist film thickness of 2000 Å and a minimum pattern line width of 1 μm without distortion.
次にパターン化した無機レジスト薄膜をエツチ
ングマスクとして高周波出力13.56MHz、パワー
密度0.2W／cm2、ガス圧１×10-2Torrの酸素雰囲
気中で、露出した電子線レジストをドライエツチ
ングし、高解像度のレジストパターンを形成し
た。 Next, using the patterned inorganic resist thin film as an etching mask, the exposed electron beam resist was dry etched in an oxygen atmosphere with a high frequency output of 13.56 MHz, a power density of 0.2 W/cm 2 , and a gas pressure of 1 × 10 -2 Torr. A high-resolution resist pattern was formed.
第１図ａないしｃは従来のレジストパターンの
形成方法の工程を示す断面図、第２図ａないしｆ
は本発明のレジストパターンの形成方法の工程を
示す断面図である。
１……半導体基板、２……厚膜レジスト層、３
……絶縁膜、４……薄膜レジスト層、５……絶縁
膜エツチングガス、６……酸素ガス、７……樹脂
層、８……無機レジスト層、９……電子線、１０
……樹脂層エツチングガス。
1A to 1C are cross-sectional views showing the steps of a conventional resist pattern forming method, and FIGS. 2A to 2F
1A and 1B are cross-sectional views showing steps of a method for forming a resist pattern according to the present invention. 1... Semiconductor substrate, 2... Thick film resist layer, 3
... Insulating film, 4 ... Thin film resist layer, 5 ... Insulating film etching gas, 6 ... Oxygen gas, 7 ... Resin layer, 8 ... Inorganic resist layer, 9 ... Electron beam, 10
...Resin layer etching gas.
Claims (1)
り、表面が平坦化するように樹脂を塗布し、しか
るのち、形成された樹脂層上にシリコンとシリコ
ン酸化物の混合物を主成分とする電子線感応性無
機レジスト層を設け、前記無機レジスト層に電子
線をパターン照射した後、前記無機レジストを現
像して、パターン化した無機レジスト層を得、次
いでこのパターン化した無機レジスト層をマスク
として露出した樹脂層部分をドライエツチングし
て前記樹脂層部分を除去することを特徴とする段
差のある半導体基板上へのレジストパターンの形
成方法。1. A resin is applied to the surface of a semiconductor substrate with steps so that there are no steps and the surface becomes flat, and then an electron beam sensitive layer containing a mixture of silicon and silicon oxide as the main component is applied on the resin layer formed. After providing an inorganic resist layer and irradiating the inorganic resist layer with an electron beam in a pattern, the inorganic resist was developed to obtain a patterned inorganic resist layer, and then this patterned inorganic resist layer was exposed as a mask. 1. A method for forming a resist pattern on a semiconductor substrate having steps, the method comprising dry etching the resin layer portion to remove the resin layer portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2871981A JPS57143826A (en) | 1981-02-28 | 1981-02-28 | Formation of resist pattern on gapped semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2871981A JPS57143826A (en) | 1981-02-28 | 1981-02-28 | Formation of resist pattern on gapped semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57143826A JPS57143826A (en) | 1982-09-06 |
| JPH0314172B2 true JPH0314172B2 (en) | 1991-02-26 |
Family
ID=12256246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2871981A Granted JPS57143826A (en) | 1981-02-28 | 1981-02-28 | Formation of resist pattern on gapped semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57143826A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59163828A (en) * | 1983-03-09 | 1984-09-14 | Toshiba Corp | Formation of fine pattern |
| JPS6097624A (en) * | 1983-11-01 | 1985-05-31 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS63129622A (en) * | 1986-11-20 | 1988-06-02 | Fujitsu Ltd | Manufacture of semiconductor device |
| JP2691175B2 (en) * | 1989-09-08 | 1997-12-17 | 日本電信電話株式会社 | Patterned oxide superconducting film formation method |
| US9632411B2 (en) * | 2013-03-14 | 2017-04-25 | Applied Materials, Inc. | Vapor deposition deposited photoresist, and manufacturing and lithography systems therefor |
| US20140272684A1 (en) | 2013-03-12 | 2014-09-18 | Applied Materials, Inc. | Extreme ultraviolet lithography mask blank manufacturing system and method of operation therefor |
-
1981
- 1981-02-28 JP JP2871981A patent/JPS57143826A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57143826A (en) | 1982-09-06 |
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