JPH03129833A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03129833A JPH03129833A JP26878789A JP26878789A JPH03129833A JP H03129833 A JPH03129833 A JP H03129833A JP 26878789 A JP26878789 A JP 26878789A JP 26878789 A JP26878789 A JP 26878789A JP H03129833 A JPH03129833 A JP H03129833A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- layer
- etching
- film
- resist film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 59
- 239000010408 film Substances 0.000 claims abstract description 58
- 239000010409 thin film Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000010030 laminating Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 91
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 36
- 239000002184 metal Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 13
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 10
- 239000000243 solution Substances 0.000 description 9
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 8
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 7
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 240000002329 Inga feuillei Species 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- IUVCFHHAEHNCFT-INIZCTEOSA-N 2-[(1s)-1-[4-amino-3-(3-fluoro-4-propan-2-yloxyphenyl)pyrazolo[3,4-d]pyrimidin-1-yl]ethyl]-6-fluoro-3-(3-fluorophenyl)chromen-4-one Chemical compound C1=C(F)C(OC(C)C)=CC=C1C(C1=C(N)N=CN=C11)=NN1[C@@H](C)C1=C(C=2C=C(F)C=CC=2)C(=O)C2=CC(F)=CC=C2O1 IUVCFHHAEHNCFT-INIZCTEOSA-N 0.000 description 1
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000120 microwave digestion Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
【発明の目的〕
（産業上の利用分野）
本発明は、半導体装置の製造方法に係り、詳しくは、エ
ツチングレートの異なった半導体層が積層された半導体
装置のメサエッチングの方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device, and more specifically, for mesa etching of a semiconductor device in which semiconductor layers having different etching rates are stacked. Regarding the method.
（従来の技術）
ＧａＡｓ等の化合物半導体基板上に形成された変調ドー
プド電界効果型トランジスタ （以下ＭＯＤＦＥＴと略
す）は、ヘテロ接合界面に生じる高移動度の２次元電子
ガスをキャリアとして用いているため、高い遮断周波数
が実現できマイクロ波素子及びＩＣへの研究、開発が進
められている。(Prior art) A modulation doped field effect transistor (hereinafter abbreviated as MODFET) formed on a compound semiconductor substrate such as GaAs uses a high-mobility two-dimensional electron gas generated at a heterojunction interface as a carrier. Research and development into microwave devices and ICs that can achieve high cutoff frequencies is progressing.
ＭＯＤＦＥＴはＡｌＧａＡｓ／ＧａＡｓ、 ＡｌＩｎＡ
ｓ／ＩｎＧａＡｓ、 ＩｎＧａＰ／ＧａＡｓあるいはＩ
ｎＧａＡＩＰ／ＧａＡｓ等バンドギャップの異なる半導
体層を接合したウェーハを使用して形成される。 ＭＯ
ＤＦＥＴは、製造過程においてウェーへ上の各素子を分
離する必要があり、ウェーハ上の素子間分離は一般にメ
サエッチングによって行なわれている、しかしながら、
ＭＯＯＦＥＴでは構成元素の異なった半導体層が積層
された構造になっているため、各半導体層のメサエッチ
ングに際して同一エッチャントでほぼ同じエツチングレ
ートが得られるとは限らない。MODFET is AlGaAs/GaAs, AlInA
s/InGaAs, InGaP/GaAs or I
It is formed using a wafer in which semiconductor layers having different band gaps such as nGaAIP/GaAs are bonded together. M.O.
DFET requires separation of each element on the wafer during the manufacturing process, and isolation between elements on the wafer is generally performed by mesa etching.
Since a MOOFET has a structure in which semiconductor layers with different constituent elements are stacked, it is not always possible to obtain approximately the same etching rate with the same etchant when mesa etching each semiconductor layer.
以下ＩｎＧａＡＩＰ／ＧａＡｓを例にとって説明する。The following explanation will be given using InGaAIP/GaAs as an example.
第３図は、ＩｎＧａＡＩＰ／ＧａＡｓｉｈＧａＡｓ１ｈ
に用いられるウェーハ構造め一例である。半絶縁性Ｇａ
Ａｓ基板１０１上にアンドープの高純度ＧａＡｓバッフ
ァ層１０２、 ｎ型の導電性を持った電子供給層ＩｎＧ
ａＡＩＰ層１０３及びオーミックコンタクト形成用の高
電子濃度のＧａＡｓ層１０４をエピタキシャル成長した
半導体層で構成され、バッファ層１０２と電子供給層１
０３とで形成されたヘテロ接合界面のバッファ層側に２
次元電子ガス１０５が生じチャンネルが形成される。Figure 3 shows InGaAIP/GaAsihGaAs1h
This is an example of a wafer structure used for. Semi-insulating Ga
An undoped high-purity GaAs buffer layer 102 on an As substrate 101, and an electron supply layer InG with n-type conductivity.
The semiconductor layer is composed of an aAIP layer 103 and a high electron concentration GaAs layer 104 for forming an ohmic contact that are epitaxially grown, and includes a buffer layer 102 and an electron supply layer 1.
2 on the buffer layer side of the heterojunction interface formed with 03.
Dimensional electron gas 105 is generated and a channel is formed.
第４図（ａ）〜（ｃ）は、従来のＩｎＧａＡＩＰ／Ｇａ
Ａｓ系ＭＯＤＦＥＴの製造工程を示す断面図である。第
４図（ａ）に示すように高電子濃度のＧａＡｓ層１０４
上に所定のパターン形状を持ったレジスト膜１０６を形
成する０次に、レジスト膜１０６をマスクとしてメサエ
ッチングを施し、高電子濃度のＧａＡｓ層１０４、電子
供給層１０３ＩｎＧａＡＩＰ及び高純度ＧａＡｓバッフ
ァ層１０２の一部を例えば燐酸：過酸化水素：水＝１＝
１＝３０．５０℃のエツチング液で除去する（第４図（
ｂ））、ここで、電子供給層１０３ＩｎＧａＡＩＰ層を
エツチング除去すれば、２次元電子ガス１０５は消滅す
るが、一般に素子間の電気的な分離をより確実なものに
するため、高純度ＧａＡｓバッファ層１０２の表層をエ
ツチング除去する。この、メサエッチングの際ＩｎＧａ
ＡＩＰとＧａＡｓとのエツチングレートの差でＩｎＧａ
ＡＩＰ層がＧａＡｓ層よりも張り出した形状になってし
まう０例えばＩｎＧａＡＩＰにおいてＧａとＡｌの混成
比が１＝１の場合、上記エツチング液でのエツチングレ
ートは毎分約０．０３．であるのに対して、ＧａＡｓで
は毎分約０．６−になる、このようにＩｎＧａＡＩＰと
ＧａＡｓではエツチングレートに２０倍もの差があるた
め、メサエッチングで電子供給層１０３ＩｎＧａＡＩＰ
のエツチングが進行中に高電子濃度１０４のＧａＡｓ層
がサイドエツチングを受け、更に電子供給層１０３Ｉｎ
ＧａＡＩＰのエツチングが終了し高純度ＧａＡｓバッフ
ァ層１０２のエツチング中、電子供給層１０３ＩｎＧａ
ＡＩＰはわずかじかエツチングされないため第４図（ｂ
）で示される形状となる０次に第４図（ｃ）に示すよう
に、高電子濃度のＧａＡｓ）１１１０４上にオーム性接
触からなるソース電極１０７５、ドレイン電極１０７Ｄ
を形成し、更にソース電極１０７Ｓドレイン電極１０７
０間の高電子濃度のＧａＡｓ層１０４をリセスエッチン
グしゲート電極１０７Ｇリセス内に形成してＭＯＤＰＩ
ＥＴが完成する。FIGS. 4(a) to (c) show conventional InGaAIP/Ga
FIG. 3 is a cross-sectional view showing the manufacturing process of an As-based MODFET. As shown in FIG. 4(a), a GaAs layer 104 with high electron concentration
A resist film 106 having a predetermined pattern shape is formed thereon.Next, mesa etching is performed using the resist film 106 as a mask to form the high electron concentration GaAs layer 104, the electron supply layer 103InGaAIP, and the high purity GaAs buffer layer 102. For example, phosphoric acid: hydrogen peroxide: water = 1 =
1 = 30.Remove with an etching solution of 50℃ (Figure 4 (
b)) Here, if the electron supply layer 103 InGaAIP layer is etched away, the two-dimensional electron gas 105 disappears, but in order to ensure more reliable electrical isolation between elements, a high purity GaAs buffer layer is generally used. The surface layer of 102 is removed by etching. During this mesa etching, InGa
Due to the difference in etching rate between AIP and GaAs, InGa
For example, when the mixture ratio of Ga and Al in InGaAIP is 1=1, the etching rate with the above etching solution is about 0.03 per minute. On the other hand, for GaAs, the etching rate is about 0.6 - per minute.As shown above, there is a 20 times difference in the etching rate between InGaAIP and GaAs, so mesa etching is used to remove the electron supply layer 103 from InGaAIP.
While the etching progresses, the GaAs layer with high electron concentration 104 undergoes side etching, and the electron supply layer 103In
After the etching of GaAIP is completed and while etching the high purity GaAs buffer layer 102, the electron supply layer 103 is
AIP is etched only slightly, so it is not etched in Figure 4 (b).
) As shown in FIG. 4(c), a source electrode 1075 and a drain electrode 107D made of ohmic contact are formed on GaAs (11104) with a high electron concentration.
, and further a source electrode 107S and a drain electrode 107.
A GaAs layer 104 with a high electron concentration between
ET is completed.
（発明が解決しようとする課題）
叙上の従来の製造方法では、メサエッチング後ＩｎＧａ
ＡＩＰ層１０３がＧａＡｓ層１０４．１０４よりも張り
出した形状になってしまうため以下に記す問題が生ずる
。まず、ＭＯＯＦＥＴでは各電極に電気信号を給電する
ための金属膜が高純度ＧａＡｓバッファ層上に配線され
る必要があり、この配線用の金属膜は、メサ上の各電極
からメサ端部を介して高純度ＧａＡｓバッファ層上に形
成する。あるいは各電極を形成する際、それぞれの電極
の金属膜そのものをバッファ層上に形成して配線用の金
属膜とすることもある。(Problem to be solved by the invention) In the conventional manufacturing method described above, InGa
Since the AIP layer 103 protrudes more than the GaAs layers 104 and 104, the following problem occurs. First, in a MOOFET, a metal film for feeding electrical signals to each electrode must be wired on a high-purity GaAs buffer layer, and this metal film for wiring is connected from each electrode on the mesa through the mesa end. and is formed on a high-purity GaAs buffer layer. Alternatively, when forming each electrode, the metal film of each electrode itself may be formed on the buffer layer to serve as a metal film for wiring.
この様な配線金属膜を従来のＭＯＯＦＥＴに形成した場
合、第５図に示すように、ＩｎＧａＡＩＰ層１０３端面
層下０３端
ているため、この部分で配線用金属膜１０９が薄膜化し
てしまい信頼性上問題がある．特に、ゲート電極１０７
Ｇについてはゲート電極の金属膜をそのまま高純度Ｇａ
Ａｓバッファ層１０２上に引き出すことが多く、ゲート
長が０．２５４以下の微細なゲート電極ではＩｎＧａＡ
ＩＰ層１０３端面層下０３端層１０２の空洞部１０８で
断線し，給電されなくなってしまう。When such a wiring metal film is formed in a conventional MOOFET, as shown in FIG. 5, since the InGaAIP layer 103 is located at the lower end of the end face layer, the wiring metal film 109 becomes thinner in this area, resulting in reliability problems. There is a problem above. In particular, the gate electrode 107
Regarding G, the metal film of the gate electrode is directly made of high-purity Ga.
InGaA is often used for fine gate electrodes with a gate length of 0.254 or less, which are often drawn out on the As buffer layer 102.
The wire breaks in the cavity 108 of the lower end layer 102 of the IP layer 103, and power is no longer supplied.
また、ＩｎＧａＡＩＰ層１０３の張層比０３防止する目
的で，第６図に示すように、高電子濃度のＧａＡｓ層１
０４を前記エツチング液でエツチング後、ＩｎＧａＡＩ
Ｐ層１０３を塩層比０３し，更に高純度ＧａＡｓバッフ
ァ層１０２を前記エツチング液でエツチングする方法も
考えられる．しかしこの方法では、ＩｎＧａＡＩＰ層１
０３のサ層比０３チングで高電子濃度のＧａＡｓ層１０
４のメサ端面のＩｎＧａＡＩＰ層１０３と高層比０３Ａ
ｓバッファ層１０２とに空洞部１１８が形成され，この
部分で前記同様の問題が生じてしまう、半導体層のサイ
ドエツチングが原因で生じる空洞の形成を防ぐ手段とし
ては、ＧａＡｓ層、ＩｎＧａＡＩＰ層をそれぞれ個別に
パターンニング、エツチングする方法がある０例えば、
高置−子濃度のＧａＡｓ層上に所定のパターン形状に従
ってレジスト膜を形成し、このレジスト膜をマスクにし
てメサエッチングを施した後、高電子濃度のＧａＡｓ層
を覆うように新たなレジスト膜のパータン形成を行い、
ＩｎＧａＡＩＰ層をメサエッチングする。更に、高電子
濃度のＧａＡｓ層、ＩｎＧａＡＩＰ層を覆うように新た
なレジスト膜のパターン形成を行い、高純度ＧａＡｓバ
ッファ層のメサエッチングを行い、第７図に示すような
断面形状を持ったメサパターンが形成される。上記メサ
パターン形成方法によれば、各半導体層のメサパターン
が個別にパターン形成、エツチングされしかも断面形状
が階段状に形成できるため、メサ端部で配線用の金属膜
が薄膜化あるいは断線する問題を解決できる。In addition, in order to prevent the tensile ratio of the InGaAIP layer 103 from 03, as shown in FIG.
After etching 04 with the above etching solution, InGaAI
It is also possible to consider a method in which the P layer 103 has a salt layer ratio of 03, and the high purity GaAs buffer layer 102 is further etched with the above etching solution. However, in this method, the InGaAIP layer 1
High electron concentration GaAs layer 10 with a layer ratio of 03
InGaAIP layer 103 on mesa end face of No. 4 and high-rise ratio 03A
A cavity 118 is formed in the s-buffer layer 102, and as a means to prevent the formation of a cavity caused by side etching of the semiconductor layer, in which the same problem as described above occurs, a GaAs layer and an InGaAIP layer are respectively formed. There are methods for individual patterning and etching. For example,
A resist film is formed according to a predetermined pattern shape on the GaAs layer with high electron concentration, and after mesa etching is performed using this resist film as a mask, a new resist film is formed to cover the GaAs layer with high electron concentration. Perform pattern formation,
Mesa etch the InGaAIP layer. Furthermore, a new resist film pattern is formed to cover the high electron concentration GaAs layer and the InGaAIP layer, and the high purity GaAs buffer layer is mesa etched to form a mesa pattern with a cross-sectional shape as shown in FIG. is formed. According to the above mesa pattern forming method, the mesa pattern of each semiconductor layer is individually patterned and etched, and the cross-sectional shape can be formed in a step-like shape, so there is a problem that the metal film for wiring becomes thin or disconnected at the mesa end. can be solved.
しかしながら、上記メサパターン形成方法では。However, in the above mesa pattern forming method.
メサエッチングの回数分だけガラスマスクを準備し、マ
スク合わせ、霧光、現像、エツチング処理を繰り返さな
ければならないため、組成の異なった半導体層が複雑に
組み合わされたＭＯＯＦＥＴにおいては、非常に繁雑な
製造工程となってしまう。Glass masks must be prepared as many times as the mesa etching process is performed, and the mask alignment, fog light, development, and etching processes must be repeated, making the manufacturing process extremely complicated for MOOFETs that have complex combinations of semiconductor layers with different compositions. It becomes a process.
加えて、各パターンの重ね合わせ誤差を考慮すると微細
なメサパターン形成、集積度の高いＩＣの製造に対して
は再現性良く形成できないという欠点がある。In addition, when the overlay error of each pattern is taken into account, there is a drawback that it is impossible to form fine mesa patterns or to manufacture highly integrated ICs with good reproducibility.
本発明は上記従来の問題点に鑑みてなされたもので、エ
ツチングレートの相違する半導体層が積層された半導体
装置の改良されたメサエッチング法を提供することを目
的とする。The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide an improved mesa etching method for a semiconductor device in which semiconductor layers having different etching rates are stacked.
（課題を解決するための手段）
本発明にかかる半導体装置の製造方法は、半導体基板上
に第１の薄膜、第２の薄膜及びレジスト膜を順次積層す
る工程と、該レジスト膜を所定のパターンに形成する工
程と、該レジスト膜をマスクとして前記第２の薄膜をエ
ツチング除去する工程と、更に該第２の薄膜をマスクと
して前記第１の薄膜をサイドエツチングを有するサイド
エツチング法でエツチング除去する工程と、前記第１の
薄膜をマスクとして前記半導体基板を所定の深さまでエ
ツチングした後、全面に新たなレジスト膜を塗布する工
程と、前記第１の薄膜のエツチングで生じた前記第２の
薄膜の下の前記第１の薄膜のサイドエツチングされた部
分に、前記新たなレジスト膜の一部を残す工程と、該レ
ジスト膜をマスクとして前記半導体基板を更に所定の深
さまでエツチングする工程とを含むことを特徴とする。(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes a step of sequentially laminating a first thin film, a second thin film, and a resist film on a semiconductor substrate, and forming the resist film in a predetermined pattern. a step of etching away the second thin film using the resist film as a mask, and further etching and removing the first thin film using the second thin film as a mask by a side etching method including side etching. a step of etching the semiconductor substrate to a predetermined depth using the first thin film as a mask, and then applying a new resist film to the entire surface; and etching the second thin film produced by etching the first thin film. a step of leaving a part of the new resist film on the side-etched portion of the first thin film under the etching process, and a step of further etching the semiconductor substrate to a predetermined depth using the resist film as a mask. It is characterized by
（作 用）
この発明は、簡単な製造工程で断面形状が階段状のメサ
パターンを形成することができ、メサ端部で配線用の金
属膜が薄膜化、あるいは断線の問題を解決できるもので
ある。また、各メサパターンはセルフアライメントで形
成できるため、組成の異なった半導体層が複雑に組み合
わされたＭＯＤＦＥＴの微細なメサパターン形成、集積
度の高いＩＣの製造に対して、容易にしかも再現性良く
形成できる。(Function) This invention can form a mesa pattern with a stepped cross-sectional shape through a simple manufacturing process, and can solve the problem of thinning of the metal film for wiring or disconnection at the mesa end. be. In addition, since each mesa pattern can be formed by self-alignment, it is easy to form fine mesa patterns for MODFETs in which semiconductor layers with different compositions are combined in a complex manner, and to manufacture highly integrated ICs with ease and good reproducibility. Can be formed.
（実施例）
以下、本発明にかかる半導体装置の製造方法の実施例に
つき図面を参照して説明する。(Example) Hereinafter, an example of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.
第１実施例
第１図（ａ）〜（ｇ）に第１実施例の半導体装置の製造
方法を工程順に各断面図で示す、まず、半絶縁性ＧａＡ
ｓ基板１０１上にアンドープの高純度ＧａＡｓバッファ
層１０２を例えば膜厚ＩＩａに、ｎ型の導電性を持った
電子供給層１０３ＩｎＧａＡＩＰ層を例えばドーピング
濃度Ｉ Ｘ １０”ｅｌｌ−”、膜厚０．０５７ａに、
さらにオーミツシコンタクト形成用の高電子濃度のＧａ
Ａｓ層１０４を例えばドーピング濃度３ Ｘ １０”ｃ
ｍ−” 、膜厚０．１７ｍでエピタキシャル成長した半
導体層上に、第１の薄膜１１として例えばＳｉｎ、膜を
０．５ｐ、第２の薄膜２１として例えばＳｉ、Ｎ４膜を
０．０３．、レジスト膜１２として例えばＡＺ１３５０
（商品名、シブレイ社）を０．５声厚さに順次積層する
（第１図（ａ））、次に第１図（ｂ）に示すように、レ
ジスト膜１２に霧光、現像処理を施し所定のパターンを
形成した後、第２の薄膜２１を例えばケミカルドライエ
ツチングで除去し、第１の薄膜１１を例えば弗化アンモ
ニューム水溶液を用いてエツチング除去する。第１の薄
膜１１のエツチングの際、弗化アンモニューム水溶液に
対して第２の薄膜２１． Ｓｉ、Ｎ４膜及び、ＧａＡｓ
層１０４はほとんど影響を受けない、従って、第１の薄
膜１１のサイドエツチング量は時間で精度良く制御でき
る０次に、高電子濃度のＧａＡｓ層１０４を例えば燐酸
：過酸化水素：水＝１ ： ｌ ：３０．５０℃のエツ
チング液でエツチング除去した後、レジスト膜１２を除
去する（第１図（Ｃ））。続いて、新たなレジスト膜２
２を全面に塗布した（第１図（ｄ））後、例えば０□ガ
スを用いた反応性イオンエツチングで第２の薄膜２１の
下の第１の薄膜１１のサイドエツチングされた部分に、
レジスト膜２２ａを残し、ＩｎＧａＡＩＰ層１０３を例
えば塩酸を用いたエツチング液でエツチング除去する。First Embodiment FIGS. 1(a) to 1(g) show cross-sectional views of the manufacturing method of the semiconductor device of the first embodiment in the order of steps. First, semi-insulating GaA
On the s-substrate 101, an undoped high-purity GaAs buffer layer 102 is formed, for example, with a film thickness of IIa, and an electron supply layer 103 with n-type conductivity, an InGaAIP layer, is formed with a doping concentration of, for example, I x 10"ell-" and a film thickness of 0.057a. To,
In addition, high electron concentration Ga for forming contact contacts
For example, the As layer 104 has a doping concentration of 3×10”c.
m-", on a semiconductor layer epitaxially grown to a film thickness of 0.17 m, the first thin film 11 is made of, for example, a Sin film of 0.5p, the second thin film 21 is made of, for example, Si, a N4 film of 0.03m, and a resist is formed. For example, AZ1350 is used as the membrane 12.
(trade name, Sibley Co., Ltd.) is sequentially laminated to a thickness of 0.5 mm (Fig. 1 (a)). Next, as shown in Fig. 1 (b), the resist film 12 is subjected to fog light and development treatment. After forming a predetermined pattern, the second thin film 21 is removed by, for example, chemical dry etching, and the first thin film 11 is removed by etching using, for example, an ammonium fluoride aqueous solution. During etching of the first thin film 11, the second thin film 21. Si, N4 film and GaAs
The layer 104 is almost unaffected, so the amount of side etching of the first thin film 11 can be controlled with high precision over time.The GaAs layer 104 with a high electron concentration is etched in the 0th order by, for example, phosphoric acid:hydrogen peroxide:water=1: 1: After etching with an etching solution at 30.50° C., the resist film 12 is removed (FIG. 1(C)). Next, a new resist film 2
2 on the entire surface (FIG. 1(d)), the side-etched portion of the first thin film 11 under the second thin film 21 is etched by reactive ion etching using, for example, 0□ gas.
The InGaAIP layer 103 is etched away with an etching solution using, for example, hydrochloric acid, leaving the resist film 22a.
この時、ＩｎＧａＡＩＰ層１０３のサイドエツチングは
高電子濃度のＧａＡｓＮ１１０４に達する前に止める（
第１図（ｅ））、また、 ＧａＡｓ層は塩酸に対して耐
性があるため高純度ＧａＡｓバッファ層１０２がエツチ
ングされることはない、再び、新たなレジスト膜（図示
省略）を全面に塗布した後、第２の薄膜２１の下の第１
の薄膜１１のサイドエツチングされた部分及び、ＩｎＧ
ａＡｓ層１０４のサイドエツチングを受けた部分に、レ
ジスト膜を残し、高純度Ｇａｐｓバッファ層１０２を所
定の深さまでエツチング除去した後。At this time, side etching of the InGaAIP layer 103 is stopped before it reaches GaAsN 1104 with high electron concentration (
In addition, since the GaAs layer is resistant to hydrochloric acid, the high-purity GaAs buffer layer 102 will not be etched.A new resist film (not shown) was applied over the entire surface again. After that, the first layer under the second thin film 21
The side-etched portion of the thin film 11 and the InG
After the resist film is left in the side etched portion of the aAs layer 104, the high purity Gaps buffer layer 102 is removed by etching to a predetermined depth.
このレジスト膜、第２の薄膜２１、第１の薄膜１１を除
去し断面形状が階段状のメサパターンが形成される（第
１図（ｆ））、引き続き、第１図（ｇ）に示すように、
高電子濃度のＧａＡｓ層１０４上にオーム性接触からな
るソース電極１０７ｓドレイン電極１０７Ｄを形成し、
更にソース電極１０７Ｓとドレイン電極１０７Ｄ間の高
電子濃度のＧａＡｓ層１０４をリセスエッチングを施し
てリセスを設けたのち、このりセス内にゲート電極１０
７Ｇを形成してＭＯＯＦＥＴが完成し、最終に配線用の
金属ｌ１１０９を形成する。This resist film, the second thin film 21, and the first thin film 11 are removed to form a mesa pattern with a stepped cross-sectional shape (FIG. 1(f)).Subsequently, as shown in FIG. 1(g), To,
A source electrode 107S and a drain electrode 107D made of ohmic contact are formed on the GaAs layer 104 with high electron concentration,
Furthermore, after performing recess etching on the high electron concentration GaAs layer 104 between the source electrode 107S and the drain electrode 107D to form a recess, the gate electrode 10 is formed in the recess.
7G is formed to complete the MOOFET, and finally a metal 1109 for wiring is formed.
なお、上記実施例ではＩｎＧａＡＩＰ／ＧａＡｓ系ＭＯ
ＤＦＥＴの場合について述べたが、ＩｎＰ基板上に結晶
成長したＡｌＩｎＡｓ／ＩｎＧａＡｓ系ＭＯＤＦＥＴで
は、燐酸、過酸化水素、水で構成されたエツチング液を
使用すれば、ＡｌＩｎＡｓ層とＩｎＧａＡｓ層とのエツ
チングレートがほぼ同じ事から以下の手順で実施できる
。これについて次に第２実施例として第２図（ａ）ない
しくｄ）を参照して説明する。In the above embodiment, InGaAIP/GaAs MO
As mentioned above in the case of a DFET, in an AlInAs/InGaAs MODFET crystal-grown on an InP substrate, the etching rate of the AlInAs layer and InGaAs layer can be reduced by using an etching solution composed of phosphoric acid, hydrogen peroxide, and water. Almost the same thing can be done by following the steps below. This will be explained next as a second embodiment with reference to FIGS. 2(a) to 2d).
第２実施例
半絶縁性ＩｎＰ基板１０１上にアンドープＩｎＰバッフ
ァ層１０２を例えば膜厚０．５Ｉｓ、高移動度の２次元
電子ガス１０５が形成されるアンドープ層ＩｎＧａｊｋ
ｓ層１１２を例えば膜厚Ｏ，ＯＳ、、電子供給層１０３
ＩｎＡＩＡｓ層を例えばドーピング濃度Ｉ ＸＩＯ”ｃ
ｍ−”、膜厚０．０５４及びオーミックコンタクト形成
用の高電子濃度のＩｎＧａＡｓ層１０４を例えばドーピ
ング濃度３Ｘ１０”ｃａｔ−’、膜厚ｏ、ｉ７ａでエピ
タキシャル成長した半導体層上に第１の実施例と同様に
、第１の薄膜１１、第２の薄膜２１、レジスト膜１２を
順次積層し、このレジスト膜１２及び各薄膜を第２図（
ａ）の如く形成する。Second Embodiment An undoped InP buffer layer 102 is formed on a semi-insulating InP substrate 101 with a film thickness of 0.5Is, for example, as an undoped layer InGajk in which a two-dimensional electron gas 105 with high mobility is formed.
For example, the s layer 112 has a film thickness of O, OS, and the electron supply layer 103.
For example, the InAIAs layer has a doping concentration of I
In the first embodiment, an InGaAs layer 104 with a high electron concentration for forming an ohmic contact is epitaxially grown with a doping concentration of 3 x 10''cat-', a film thickness of o, and i7a. Similarly, the first thin film 11, the second thin film 21, and the resist film 12 are sequentially laminated, and the resist film 12 and each thin film are stacked as shown in FIG.
Form as in a).
次ぎに、高電子濃度のＩｎＧａＡｓ層１０４．電子供給
層ＩｎＡｌＡｓ層１０３、アンドープ層ＩｎＧａＡｓ層
１１２を例えば燐酸、過酸化水素、水で構成されたエツ
チング液で除去し、続いて、新たなレジスト膜２２を全
面に塗布した後、例えば０２ガスを用いた反応性イオン
エツチングで第２の薄膜２１の下の第１の薄膜１１のサ
イドエツチングされた部分に、レジスト膜２２ａを残し
く第２図（ｂ））、アンドープＩｎＰバッファ層１０２
を例えば塩酸、燐酸で構成されたエツチング液でエツチ
ング除去した後、 レジスト膜２２ａ、第２の薄膜２１
．第１の薄１１１１を除去し断面形状が階段状のメサパ
ターンが形成される（第２図（Ｃ））。Next, a high electron concentration InGaAs layer 104. The electron supply layer InAlAs layer 103 and the undoped InGaAs layer 112 are removed using an etching solution composed of, for example, phosphoric acid, hydrogen peroxide, and water, and then a new resist film 22 is applied over the entire surface, and then, for example, 02 gas is applied. A resist film 22a is left in the side-etched portion of the first thin film 11 under the second thin film 21 by the reactive ion etching process used (FIG. 2(b)), and the undoped InP buffer layer 102 is left behind.
After removing the resist film 22a and the second thin film 21 by etching with an etching solution composed of, for example, hydrochloric acid and phosphoric acid.
．． The first thin layer 1111 is removed to form a mesa pattern with a stepped cross-sectional shape (FIG. 2(C)).
引き続き、第２図（ｄ）に示すように、高電子濃度のＩ
ｎＧａＡｓ層１０４上にオーム性接触からなるソース電
極１０７ｓ、ドレイン電極１０７０を形成し、更にソー
ス電極１０７ｓ、ドレイン電極１０７０間の高電子濃度
のＩｎＧａＡｓ層１０４をリセスエッチングしゲート電
極１０７Ｇをリセス内に形成してＡｌＩｎＡｓ／ＩｎＧ
ａＡｓ系ＭＯＯＦＥＴが完成し、最後に配線用の金属膜
１０９を形成する。Subsequently, as shown in FIG. 2(d), I
A source electrode 107s and a drain electrode 1070 made of ohmic contact are formed on the nGaAs layer 104, and the InGaAs layer 104 with a high electron concentration between the source electrode 107s and the drain electrode 1070 is recess-etched to form a gate electrode 107G in the recess. AlInAs/InG
After the aAs-based MOOFET is completed, a metal film 109 for wiring is finally formed.
叙上の第１、第２の実施例から明らかなように、本発明
の方法で形成したメサパターンは、断面形状が階段状に
なっていることから、配線用の金属膜がメサ端部で薄膜
化あるいは断線する事がない。As is clear from the first and second embodiments described above, the mesa pattern formed by the method of the present invention has a stepped cross-sectional shape, so that the metal film for wiring is not formed at the ends of the mesa. There will be no thinning or disconnection.
また、各メサパターンはセルフアライメントで形成でき
るため、組成の異なった半導体層が複雑に組み合わされ
たＭＯＤＦＥＴにおいても、容易に、しかも再現性良く
形成できる。Further, since each mesa pattern can be formed by self-alignment, even a MODFET in which semiconductor layers having different compositions are combined in a complex manner can be formed easily and with good reproducibility.
なお１本実施例で使用した薄膜Ｓｉｎ、、ＳＬ、 Ｎ４
の形成順序はどちらが先でもよく、他の薄膜例えばＡ１
□０３、ＡＩＮあるいはＴｉ、 Ａ１等であっても構わ
なく、３層以上の薄膜で構成しても良いことは、容易に
類推できる。また、サイドエツチング部にレジスト膜を
残す方法は全面露光後、現像処理を行なっても構わない
、更に、本発明はＭＯＯＦＥＴのみならずショットキ障
壁型電界効果トランジスタ等の多段メサの形成において
も有効である。Note that the thin film Sin, SL, N4 used in this example
The order of formation of the other thin films, for example A1, may be in any order.
It can be easily inferred that it may be made of □03, AIN, Ti, A1, etc., and may be composed of three or more thin films. Furthermore, the method of leaving a resist film in the side etched area may be carried out by performing a development process after the entire surface is exposed.Furthermore, the present invention is effective not only in the formation of MOOFETs but also in the formation of multi-stage mesas such as Schottky barrier field effect transistors. be.
以上述べたように本発明で形成した半導体装置は、簡単
な製造工程で断面形状が階段状のメサパターンを形成す
ることができ、メサ端部で配線用の金属膜が薄層化、あ
るいは断線する問題を解決できる。更に、各メサパター
ンはセルフアライメントで形成できるため、組成の異な
った半導体層が複雑に組み合わされたＭＯＤＦＥＴの微
細なメサパターン形成、集積度の高いＩＣの製造に対し
て、容易にしかも再現性良く形成できる顕著な効果があ
る。As described above, the semiconductor device formed according to the present invention can form a mesa pattern with a stepped cross-sectional shape through a simple manufacturing process, and the metal film for wiring becomes thinner or disconnected at the mesa end. can solve problems. Furthermore, since each mesa pattern can be formed by self-alignment, it is easy and reproducible to form fine mesa patterns for MODFETs that have complex combinations of semiconductor layers with different compositions, and to manufacture highly integrated ICs. There are noticeable effects that can be formed.
第１図（ａ）ないしくｇ）は本発明の第１実施例のＭＯ
ＤＦＥＴの製造方法を工程順に示すいずれも断面図、第
２図（ａ）ないしくｄ）は本発明の第２実施例のＭＯＤ
ＦＥＴの製造方法を工程順に示すいずれも断面図、第３
図はＭＯＤＦＥＴの製造に用いる半導体基板の断面図、
第４図（ａ）ないしくｃ）は従来例のＭＯＯＦＥＴの製
造方法を工程順に示すいずれも断面図、第５図ないし第
７図はいずれも夫々が従来例のＭＯＤＦＥＴの構造を示
す断面図である。
１１・・・第１の薄膜、２１・・・第２の薄膜、１２、
２２・・・レジスト膜。FIG. 1(a) to g) shows the MO of the first embodiment of the present invention.
All are cross-sectional views showing the manufacturing method of DFET in the order of steps, and FIGS. 2(a) to 2d) are MODs of the second embodiment of the present invention.
The third figure is a cross-sectional view showing the FET manufacturing method in the order of steps.
The figure is a cross-sectional view of a semiconductor substrate used for manufacturing MODFET,
4(a) to 4(c) are cross-sectional views showing the manufacturing method of a conventional MOOFET in order of process, and FIGS. 5 to 7 are cross-sectional views showing the structure of a conventional MODFET, respectively. be. 11... first thin film, 21... second thin film, 12,
22...Resist film.
Claims (1)
膜を順次積層する工程と、該レジスト膜を所定のパター
ンに形成する工程と、該レジスト膜をマスクとして前記
第２の薄膜をエッチング除去する工程と、更に該第２の
薄膜をマスクとして前記第１の薄膜をサイドエッチング
を有するサイドエッチング法でエッチング除去する工程
と、前記第１の薄膜をマスクとして前記半導体基板を所
定の深さまでエッチングした後、全面に新たなレジスト
膜を塗布する工程と、前記第１の薄膜のエッチングで生
じた前記第２の薄膜の下の前記第１の薄膜のサイドエッ
チングされた部分に、前記新たなレジスト膜の一部を残
す工程と、該レジスト膜をマスクとして前記半導体基板
を更に所定の深さまでエッチングする工程とを含むこと
を特徴とする半導体装置の製造方法。A step of sequentially laminating a first thin film, a second thin film, and a resist film on a semiconductor substrate, a step of forming the resist film into a predetermined pattern, and etching away the second thin film using the resist film as a mask. a step of etching away the first thin film by a side etching method using the second thin film as a mask; and etching the semiconductor substrate to a predetermined depth using the first thin film as a mask. After that, a step of applying a new resist film to the entire surface, and applying the new resist to the side-etched part of the first thin film under the second thin film generated by etching the first thin film. A method for manufacturing a semiconductor device, comprising the steps of leaving a portion of the film, and etching the semiconductor substrate further to a predetermined depth using the resist film as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26878789A JPH03129833A (en) | 1989-10-16 | 1989-10-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26878789A JPH03129833A (en) | 1989-10-16 | 1989-10-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03129833A true JPH03129833A (en) | 1991-06-03 |
Family
ID=17463274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26878789A Pending JPH03129833A (en) | 1989-10-16 | 1989-10-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03129833A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003074909A (en) * | 2001-09-05 | 2003-03-12 | Chofu Seisakusho Co Ltd | Outdoor air conditioner |
-
1989
- 1989-10-16 JP JP26878789A patent/JPH03129833A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003074909A (en) * | 2001-09-05 | 2003-03-12 | Chofu Seisakusho Co Ltd | Outdoor air conditioner |
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