JPH03128936U - - Google Patents

Info

Publication number
JPH03128936U
JPH03128936U JP40234290U JP40234290U JPH03128936U JP H03128936 U JPH03128936 U JP H03128936U JP 40234290 U JP40234290 U JP 40234290U JP 40234290 U JP40234290 U JP 40234290U JP H03128936 U JPH03128936 U JP H03128936U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP40234290U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP40234290U priority Critical patent/JPH03128936U/ja
Publication of JPH03128936U publication Critical patent/JPH03128936U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
JP40234290U 1990-12-27 1990-12-27 Pending JPH03128936U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP40234290U JPH03128936U (en) 1990-12-27 1990-12-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP40234290U JPH03128936U (en) 1990-12-27 1990-12-27

Publications (1)

Publication Number Publication Date
JPH03128936U true JPH03128936U (en) 1991-12-25

Family

ID=31699965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP40234290U Pending JPH03128936U (en) 1990-12-27 1990-12-27

Country Status (1)

Country Link
JP (1) JPH03128936U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105970A (en) * 1977-02-28 1978-09-14 Hitachi Ltd Assembling method for semiconductor device
JPS53123078A (en) * 1977-04-01 1978-10-27 Nec Corp Integrated circuit device
JPS57153442A (en) * 1981-02-20 1982-09-22 Siemens Ag Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105970A (en) * 1977-02-28 1978-09-14 Hitachi Ltd Assembling method for semiconductor device
JPS53123078A (en) * 1977-04-01 1978-10-27 Nec Corp Integrated circuit device
JPS57153442A (en) * 1981-02-20 1982-09-22 Siemens Ag Semiconductor device

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