JPH0312770B2 - - Google Patents
Info
- Publication number
- JPH0312770B2 JPH0312770B2 JP25418186A JP25418186A JPH0312770B2 JP H0312770 B2 JPH0312770 B2 JP H0312770B2 JP 25418186 A JP25418186 A JP 25418186A JP 25418186 A JP25418186 A JP 25418186A JP H0312770 B2 JPH0312770 B2 JP H0312770B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- alinas
- type
- impurities
- gainas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 239000012535 impurity Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 25
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 15
- 230000005669 field effect Effects 0.000 claims description 11
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 17
- 239000013078 crystal Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 229910008812 WSi Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- -1 aluminum-indium-arsenic Chemical compound 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000000171 gas-source molecular beam epitaxy Methods 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、高周波増幅回路、高速集積回路、光
電子集積回路等に作用される電界効果トランジス
タに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor used in high frequency amplifier circuits, high speed integrated circuits, optoelectronic integrated circuits, etc.
［従来の技術］
ヘテロ接合界面に形成される２次元電子を用い
たトランジスタとしては、従来より、いくつかの
ものが提案されている。たとえば、特公昭59−
53714、特開昭56−45079およびジヤパニーズ・ジ
ヤーナル・オブ・アプライド・フイジツクス
（Japanese Journal of Applied Physics）第19
巻、1980年、L225頁などに、このタイプのトラ
ンジスタが記載されている。これらに記載された
トランジスタでは、基板としてガリウム・砒素が
用いられている。ガリウム・砒素を基板として用
いた場合には、室温での２次元電子の移動度は
8000cm2／Ｖ・sec程度である。これに対して、イ
ンジウム・リン（以下InPと記す）を基板として
用いた場合には、室温での２次元電子の移動度と
しては12000cm2／Ｖ・sec程度が得られる。したが
つて高周波特性や増幅率の優れた電界効果トラン
ジスタを実現することができる。InPを基板とし
て用いる２次元電子トランジスタとしては、
IEEE・エレクトロン・デバイス・レタース
（EIectron Device Letters）C.Y.Chen等、EDL
−３巻、1982年、152頁に記載されているものが
知られている。[Prior Art] Several transistors have been proposed in the past that use two-dimensional electrons formed at a heterojunction interface. For example, the
53714, Japanese Patent Publication No. 56-45079 and Japanese Journal of Applied Physics No. 19
Vol., 1980, page L225, describes this type of transistor. In the transistors described in these documents, gallium arsenic is used as a substrate. When using gallium/arsenic as a substrate, the two-dimensional electron mobility at room temperature is
It is about 8000cm 2 /V·sec. On the other hand, when indium phosphide (hereinafter referred to as InP) is used as the substrate, a two-dimensional electron mobility of about 12000 cm 2 /V·sec can be obtained at room temperature. Therefore, a field effect transistor with excellent high frequency characteristics and amplification factor can be realized. As a two-dimensional electronic transistor using InP as a substrate,
IEEE Electron Device Letters CYChen et al. EDL
The one described in Volume 3, 1982, page 152 is known.
第２図は、InPを基板として用いた従来の２次
元電子トランジスタの構成を示す断面図である。
InP基板２１の上には、不純物無添加のアルミニ
ウム・インジウム・砒素混晶半導体層（以下
AlInAs層と記す）２２、ガリウム・インジウ
ム・砒素混晶半導体層（以下GaInAs層と記す）
２３、ｎ型不純物が添加されたAlInAs層２４が
順次形成されている。制御電極２６は、ｎ型
AlInAs層２４上に設けられており、該制御電極
２６の両側にソース電極２７およびドレイン電極
２８が設けられている。 FIG. 2 is a cross-sectional view showing the structure of a conventional two-dimensional electronic transistor using InP as a substrate.
On the InP substrate 21, an aluminum-indium-arsenic mixed crystal semiconductor layer (hereinafter referred to as
22, gallium-indium-arsenic mixed crystal semiconductor layer (hereinafter referred to as GaInAs layer)
23. AlInAs layers 24 doped with n-type impurities are successively formed. The control electrode 26 is an n-type
It is provided on the AlInAs layer 24, and a source electrode 27 and a drain electrode 28 are provided on both sides of the control electrode 26.
GaInAs層２３とｎ型AlInAs層２４の界面に
は、２次元電子層２５が形成されており、この２
次元電子層２５の電子密度を制御することによ
り、ソース電極２７とドレイン電極２８の間を流
れる電流が制御される。 A two-dimensional electronic layer 25 is formed at the interface between the GaInAs layer 23 and the n-type AlInAs layer 24.
By controlling the electron density of the dimensional electron layer 25, the current flowing between the source electrode 27 and the drain electrode 28 is controlled.
［発明が解決しようとする問題点］
しかしながら、以上説明したような従来の電界
効果トランジスタにおいては、意図的には不純物
の添加されていないAlInAs層２２中にInP基板２
１中の不純物が拡散し、得られたトランジスタの
特性として、良好なピンチオフが得られないとい
う問題点があつた。また、このように基板中の不
純物により影響を受けるため、トランジスタ特性
が基板のロツトによつてばらつきを生じるという
問題点もあつた。[Problems to be Solved by the Invention] However, in the conventional field effect transistor as described above, the InP substrate 2 is intentionally placed in the AlInAs layer 22 to which impurities are not added.
There was a problem in that the impurities in No. 1 were diffused and the resulting transistor did not have good pinch-off characteristics. In addition, since the transistor characteristics are affected by impurities in the substrate, there is a problem in that the transistor characteristics vary depending on the substrate lot.
それゆえに、本発明の目的は、ピンチオフ特性
が優れ、かつ基板のロツトごとにばらつくことの
ない高品質の電界効果トランジスタを提供するこ
とにある。 Therefore, an object of the present invention is to provide a high-quality field effect transistor that has excellent pinch-off characteristics and does not vary from substrate lot to substrate lot.
［問題点を解決するための手段および作用］
上記の目的を達成するための本発明の構成を、
実施例に対応する第１図を用いて説明する。InP
基板１上に、ｎ型不純物が添加された第１の
AlInAs層２が形成され、該第１のAlInAs層２上
には、不純物が添加されていないGaInAs層３が
形成され、さらに該GaInAs層３上に第２の
AlInAs層５が形成される。第１のAlInAs層２に
は、InP基板１から拡散する不純物の濃度に比べ
て非常に高い濃度のｎ型不純物が添加される。[Means and effects for solving the problems] The structure of the present invention for achieving the above object is as follows:
This will be explained using FIG. 1 which corresponds to an embodiment. InP
A first layer doped with n-type impurities is formed on the substrate 1.
An AlInAs layer 2 is formed, a GaInAs layer 3 to which no impurity is added is formed on the first AlInAs layer 2, and a second GaInAs layer 3 is formed on the GaInAs layer 3.
An AlInAs layer 5 is formed. The first AlInAs layer 2 is doped with n-type impurities at a much higher concentration than the concentration of impurities diffused from the InP substrate 1 .
以上の構成にすることにより、２次元電子層４
は、第１のAlInAs層２とGaInAs層３との間の界
面に形成され、従来と異なり基板に近い側に形成
される。しかし、GaInAs層には、一般的にシヨ
ツトキー接触を形成させることが難しい。そこ
で、本発明では、GaInAs層３上に制御電極を直
接形成させるのではなく、シヨツトキー接触を形
成させることが容易な材料をその上に形成した
後、制御電極を形成させている。このシヨツトキ
ー接触を形成させることが容易な材料としては
AlInAsが知られており、この理由から、本発明
において第２のAlInAs層が形成されている。第
１図に示すように、第２のAlInAs層５上に制御
電極６を設けるこにより、制御電極６から空乏層
が拡がり、２次元電子層４の電子密度を制御する
ことが可能となり、これによつてソース電極７と
ドレイン電極８の間を流れる電流を制御すること
ができる。 With the above configuration, the two-dimensional electronic layer 4
is formed at the interface between the first AlInAs layer 2 and the GaInAs layer 3, and is formed on the side closer to the substrate, unlike the conventional method. However, it is generally difficult to form Schottky contacts in GaInAs layers. Therefore, in the present invention, the control electrode is not formed directly on the GaInAs layer 3, but after a material on which it is easy to form a shot key contact is formed thereon. Materials that can easily form this shot key contact include
AlInAs is known and for this reason a second AlInAs layer is formed in the present invention. As shown in FIG. 1, by providing a control electrode 6 on the second AlInAs layer 5, a depletion layer expands from the control electrode 6, making it possible to control the electron density of the two-dimensional electron layer 4. Therefore, the current flowing between the source electrode 7 and the drain electrode 8 can be controlled.
また、本発明では、InP基板１上に、不純物濃
度の高いｎ型の第１のAlInAs層が形成されてい
るため、InP基板１から拡散する不純物による影
響を該第１のAlInAs層によつて少なくすること
ができる。 Furthermore, in the present invention, since the n-type first AlInAs layer with a high impurity concentration is formed on the InP substrate 1, the influence of impurities diffused from the InP substrate 1 is suppressed by the first AlInAs layer. It can be reduced.
［実施例］
以下、本発明の一実施例を第１図に基づいて説
明する。半絶縁性InP基板１上に、有機金属気相
長法あるいはガスソースMBE（Molecular−
beam epitaxy）法により、基板温度600℃〜650
℃において、ｎ型不純物を添加した第１の
AlInAs層２を形成する。ｎ型不純物としては、
Si，Ｓ，Seなどを水素化物の形で供給し、その
密度は１×1017〜５×1018cm-3程度にし、厚さは
500Å〜2000Åの範囲にする。一般に、InP基板
１から拡散する不純物の密度は、1016cm-3程度で
あり、また拡散深さも300Å程度であるので、第
１のAlInAs層２を、上述の不純物密度および厚
さとすることにより、InP基板１から拡散する不
純物の影響をほとんどなくすることができる。次
に、不純物無添加のGaInAs層３を200Å〜2000
Å程度の厚さで形成し、第２のAlInAs層５を200
Å〜1000Å程度の厚さで形成する。第１の
AlInAs層２、GaInAs層３および第２のAlInAs
層５の混晶組成は、InP基板１との格子不整が0.1
％以下となるように形成する。[Example] Hereinafter, an example of the present invention will be described based on FIG. On the semi-insulating InP substrate 1, metal organic vapor phase length method or gas source MBE (Molecular-
By the beam epitaxy method, the substrate temperature is 600℃~650℃.
℃, the first layer doped with n-type impurities
An AlInAs layer 2 is formed. As an n-type impurity,
Si, S, Se, etc. are supplied in the form of hydrides, with a density of about 1×10 17 to 5×10 18 cm -3 and a thickness of
Set it in the range of 500 Å to 2000 Å. Generally, the density of impurities diffused from the InP substrate 1 is about 10 16 cm -3 and the diffusion depth is about 300 Å. Therefore, by making the first AlInAs layer 2 have the above impurity density and thickness, , the influence of impurities diffused from the InP substrate 1 can be almost eliminated. Next, a GaInAs layer 3 with no impurities added is formed with a thickness of 200 Å to 2000 Å.
The second AlInAs layer 5 is formed to a thickness of about 200 Å.
It is formed with a thickness of approximately 1000 Å. first
AlInAs layer 2, GaInAs layer 3 and second AlInAs
The mixed crystal composition of layer 5 has a lattice mismatch of 0.1 with respect to InP substrate 1.
% or less.
第２のAlInAs層５は、トランジスタの所要特
性により、不純物無添加、ｐ型またはｎ型にす
る。すなわち、高入力耐圧が必要な場合には、不
純物無添加とし、高ドレイン電流が必要な場合に
はｎ型とし、しきい値電圧を正にする場合にはｐ
型とする。ｎ型はSi，Ｓ，Seなどの不純物を1016
cm-3〜1018cm-3添加し、ｐ型はZn，Mg，Mnなど
の不純物を1016cm-3〜1018cm-3程度添加する。 The second AlInAs layer 5 is doped with no impurities and is made p-type or n-type depending on the required characteristics of the transistor. In other words, if high input withstand voltage is required, do not add impurities, if high drain current is required, use n-type, and if the threshold voltage is positive, use p-type.
Make it into a mold. For n-type impurities such as Si, S, Se, etc. 10 16
cm -3 to 10 18 cm -3 is added, and for p-type, impurities such as Zn, Mg, and Mn are added to about 10 16 cm -3 to 10 18 cm -3 .
さらにAu・Ge合金からなる抵抗性接触金属を
蒸着し、たとえば400℃で合金化することにより、
ソース電極７およびドレイン電極８を形成する。
最後に、たとえばAl，Pt，Au，Ｗ，WSiなどか
ら選ばれた制御電極６を蒸着法などの方法により
形成し完成させる。 Furthermore, by depositing a resistive contact metal consisting of an Au/Ge alloy and alloying it at, for example, 400°C,
A source electrode 7 and a drain electrode 8 are formed.
Finally, a control electrode 6 selected from, for example, Al, Pt, Au, W, WSi, etc. is formed and completed by a method such as vapor deposition.
［発明の効果］
本発明の電界効果トランジスタでは、InP基板
上に意図的に高濃度のｎ型不純物を添加した第１
のAlInAs層が形成されているため、InP基板から
拡散する不純物の影響を著しく低減させることが
できる。したがつて、本発明によれば、再現性良
く、高周波特性・増幅特性の優れた電界効果トラ
ンジスタとすることができる。[Effects of the Invention] In the field effect transistor of the present invention, a first transistor in which a high concentration of n-type impurity is intentionally doped on an InP substrate is provided.
Since the AlInAs layer is formed, the influence of impurities diffusing from the InP substrate can be significantly reduced. Therefore, according to the present invention, a field effect transistor with good reproducibility and excellent high frequency characteristics and amplification characteristics can be obtained.
第１図は、本発明の一実施例を説明するための
断面図である。第２図は、従来の電界効果トラン
ジスタを示す断面図である。
図において、１はInP基板、２は第１のAlInAs
層、３はGaInAs層、４は２次元電子層、５は第
２のAlInAs層、６は制御電極、７はソース電極、
８はドレイン電極を示す。
FIG. 1 is a sectional view for explaining one embodiment of the present invention. FIG. 2 is a sectional view showing a conventional field effect transistor. In the figure, 1 is an InP substrate, 2 is a first AlInAs
3 is a GaInAs layer, 4 is a two-dimensional electronic layer, 5 is a second AlInAs layer, 6 is a control electrode, 7 is a source electrode,
8 indicates a drain electrode.
Claims (1)
のAlInAs層を形成し、該第１のAlInAs層上に不
純物が添加されていないGaInAs層を形成し、該
GaInAs層上に第２のAlInAs層を形成し、該第２
のAlInAs層上に制御電極を設け、該制御電極の
両側に前記GaInAs層に対して抵抗性接触となる
ソース電極およびドレイン電極を設けたことを特
徴とする、電界効果トランジスタ。 ２ 前記第２のAlInAs層に不純物が添加されて
いないことを特徴とする特許請求の範囲第１項記
載の電界効果トランジスタ。 ３ 前記第２のAlInAs層の伝導型がｐ型である
ことを特徴とする、特許請求の範囲第１項記載の
電界効果トランジスタ。 ４ 前記第２のAlInAs層の伝導型がｎ型である
ことを特徴とする、特許請求の範囲第１項記載の
電界効果トランジスタ。[Claims] 1. A first layer doped with n-type impurities on an InP substrate.
A GaInAs layer to which impurities are not added is formed on the first AlInAs layer.
A second AlInAs layer is formed on the GaInAs layer, and the second AlInAs layer is formed on the GaInAs layer.
A field effect transistor, characterized in that a control electrode is provided on the AlInAs layer, and a source electrode and a drain electrode that are in resistive contact with the GaInAs layer are provided on both sides of the control electrode. 2. The field effect transistor according to claim 1, wherein no impurity is added to the second AlInAs layer. 3. The field effect transistor according to claim 1, wherein the conductivity type of the second AlInAs layer is p-type. 4. The field effect transistor according to claim 1, wherein the conductivity type of the second AlInAs layer is n-type.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25418186A JPS63107173A (en) | 1986-10-24 | 1986-10-24 | Field effect transistor |
| EP87115444A EP0264932A1 (en) | 1986-10-24 | 1987-10-21 | Field effect transistor |
| CA000550121A CA1261977A (en) | 1986-10-24 | 1987-10-23 | Field effect transistor |
| KR1019870011772A KR900008154B1 (en) | 1986-10-24 | 1987-10-23 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25418186A JPS63107173A (en) | 1986-10-24 | 1986-10-24 | Field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63107173A JPS63107173A (en) | 1988-05-12 |
| JPH0312770B2 true JPH0312770B2 (en) | 1991-02-21 |
Family
ID=17261356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25418186A Granted JPS63107173A (en) | 1986-10-24 | 1986-10-24 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63107173A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0230149A (en) * | 1988-07-20 | 1990-01-31 | Sanyo Electric Co Ltd | Hetero junction field effect transistor |
| JP2529109Y2 (en) * | 1989-12-13 | 1997-03-19 | 株式会社シマノ | Double bearing reel |
-
1986
- 1986-10-24 JP JP25418186A patent/JPS63107173A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63107173A (en) | 1988-05-12 |
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