JPH03109350U - - Google Patents

Info

Publication number
JPH03109350U
JPH03109350U JP1623790U JP1623790U JPH03109350U JP H03109350 U JPH03109350 U JP H03109350U JP 1623790 U JP1623790 U JP 1623790U JP 1623790 U JP1623790 U JP 1623790U JP H03109350 U JPH03109350 U JP H03109350U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit chip
mounting
mounting structure
mounting board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1623790U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1623790U priority Critical patent/JPH03109350U/ja
Publication of JPH03109350U publication Critical patent/JPH03109350U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第1図は本考案の実施例を示す図、第2図はウ
エハを示す図、第3図は実装基板を示す図である
。 図において、1……ウエハ、2……集積回路チ
ツプ、3……実装基板、4……固定突起、5……
嵌合穴である。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) ウエハ1から切り出された集積回路チツプ
    2を実装基板3上に実装する集積回路チツプの実
    装構造であつて、 前記集積回路チツプ2を側縁に等ピツチで固定
    突起4を突出させて櫛形に切り出して形成すると
    ともに、該集積回路チツプ2の固定突起4を実装
    基板3に実装面に穿設した嵌合穴5に嵌合させて
    固定したことを特徴とする集積回路チツプの実装
    構造。 (2) 前記実装基板3は、実装面に配線パターン
    を生成したシリコンウエハにより形成されること
    を特徴とする請求項1記載の集積回路チツプの実
    装構造。
JP1623790U 1990-02-22 1990-02-22 Pending JPH03109350U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1623790U JPH03109350U (ja) 1990-02-22 1990-02-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1623790U JPH03109350U (ja) 1990-02-22 1990-02-22

Publications (1)

Publication Number Publication Date
JPH03109350U true JPH03109350U (ja) 1991-11-11

Family

ID=31519517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1623790U Pending JPH03109350U (ja) 1990-02-22 1990-02-22

Country Status (1)

Country Link
JP (1) JPH03109350U (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62293750A (ja) * 1986-06-13 1987-12-21 Nippon Telegr & Teleph Corp <Ntt> 配線板およびその製造方法
JPH02181465A (ja) * 1989-01-06 1990-07-16 Matsushita Electric Ind Co Ltd 半導体チップ実装方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62293750A (ja) * 1986-06-13 1987-12-21 Nippon Telegr & Teleph Corp <Ntt> 配線板およびその製造方法
JPH02181465A (ja) * 1989-01-06 1990-07-16 Matsushita Electric Ind Co Ltd 半導体チップ実装方法

Similar Documents

Publication Publication Date Title
JPH03109350U (ja)
JPH0350970U (ja)
JPH0298676U (ja)
JPS6447079U (ja)
JPH0448624U (ja)
JPS6371570U (ja)
JPS62193757U (ja)
JPS6338368U (ja)
JPS62182572U (ja)
JPH0351868U (ja)
JPH0180975U (ja)
JPH03113892U (ja)
JPH0351861U (ja)
JPS6190251U (ja)
JPH01157479U (ja)
JPH0238788U (ja)
JPH0339876U (ja)
JPS6265866U (ja)
JPH03117873U (ja)
JPS6190272U (ja)
JPH0434751U (ja)
JPH0220349U (ja)
JPH0369234U (ja)
JPS6212948U (ja)
JPS6389262U (ja)