JPH03108797A - Multilayer wiring board and manufacture thereof - Google Patents
Multilayer wiring board and manufacture thereofInfo
- Publication number
- JPH03108797A JPH03108797A JP24750089A JP24750089A JPH03108797A JP H03108797 A JPH03108797 A JP H03108797A JP 24750089 A JP24750089 A JP 24750089A JP 24750089 A JP24750089 A JP 24750089A JP H03108797 A JPH03108797 A JP H03108797A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- plating
- thin film
- multilayer wiring
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000007747 plating Methods 0.000 claims abstract description 52
- 239000010409 thin film Substances 0.000 claims abstract description 38
- 229920001721 polyimide Polymers 0.000 claims abstract description 18
- 239000009719 polyimide resin Substances 0.000 claims abstract description 16
- 239000000919 ceramic Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 230000000737 periodic effect Effects 0.000 claims abstract description 8
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 6
- 229910052737 gold Inorganic materials 0.000 claims abstract description 5
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- 239000000039 congener Substances 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 229910052804 chromium Inorganic materials 0.000 abstract description 5
- 238000009713 electroplating Methods 0.000 abstract 1
- 230000008719 thickening Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 14
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052770 Uranium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、セラミック基板の主面上に、ポリイミド樹脂
を絶縁層とする多層配線か施された多層配線基板および
その製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a multilayer wiring board in which multilayer wiring with polyimide resin as an insulating layer is provided on the main surface of a ceramic substrate, and a method for manufacturing the same.
［従来の技術］
基板主面上に多層配線を形成する場合に、その配線パタ
ーンの形成方法としては、絶縁層であるポリイミド樹脂
の表面上にＣｒ、Ｃｕ、Ｃｒのスパッタリングを順次行
い、そのスパッタ面にフォトレジストを塗布した後、パ
ターン露光、現像、エツチングを順次行うことで、所望
の配線パターンを得るエツチング法が一般的である。[Prior Art] When forming multilayer wiring on the main surface of a substrate, the wiring pattern is formed by sequentially sputtering Cr, Cu, and Cr on the surface of a polyimide resin that is an insulating layer, and then sputtering Cr, Cu, and Cr. A common etching method is to apply a photoresist to the surface and then sequentially perform pattern exposure, development, and etching to obtain a desired wiring pattern.
［発明が解決しようとする課題］
しかるに、上記したエツチング法では、配線パターンと
なる薄膜をスパッタリングで形成するため、スパッタ時
間か長く（例えば５μＴＴＩのスパッタで約２時間）、
コストかかかることから、配線の厚付は効率が悪い。[Problems to be Solved by the Invention] However, in the above-mentioned etching method, since the thin film that becomes the wiring pattern is formed by sputtering, the sputtering time is long (for example, about 2 hours for 5 μTTI sputtering).
Thick wiring is inefficient because it is costly.
また、エツチング液稈ては、エツチングか垂直方向に進
行するにつれて、基板表面と平行な方向にもエツチング
か進行するためオーバエツチングとなり、配線のパター
ン精度が低下する等の課題を崩していた。Furthermore, as etching progresses in the perpendicular direction, the etching solution also progresses in a direction parallel to the substrate surface, resulting in over-etching, which causes problems such as a decrease in wiring pattern accuracy.
本発明は上記事情に基ついてなされたもので、その目的
は、配線の厚付は効率、およびパターン精度を向」ニさ
せた多層配線基板およびその製造方法を提供することに
ある。The present invention has been made based on the above-mentioned circumstances, and an object thereof is to provide a multilayer wiring board and a method for manufacturing the same in which wiring thickness is improved in efficiency and pattern accuracy.
［課題を解決するための手段］
第１の発明である多層配線基板は、上記目的を達成する
ために、セラミック基板の主面上に、ポリイミド樹脂を
絶縁層とする多層配線か施された多層配線基板において
、
前記多層配線の各配線層は、薄膜層と、該薄膜層上にパ
ターンメッキにて形成されたメッキ層とから構成され、
前記薄膜層は、下層に周期表の４Ａ族（Ｔｉおよびその
同族）または６Ａ族（Ｃｒおよびその同族）に属するい
ずれかの金属、上層にＣｕの２層から成り、前記メッキ
層は、下層にＣ１」、上０層にＮｉ、Ａｕ、Ｐｄ、また
はＣｒの２層から成ることを技術的手段とする。[Means for Solving the Problems] In order to achieve the above object, the first invention, a multilayer wiring board, is a multilayer wiring board in which multilayer wiring is provided on the main surface of a ceramic substrate, using polyimide resin as an insulating layer. In the wiring board, each wiring layer of the multilayer wiring is composed of a thin film layer and a plating layer formed on the thin film layer by pattern plating,
The thin film layer consists of two layers: a lower layer of metal belonging to group 4A (Ti and its congeners) or 6A group (Cr and its congeners) of the periodic table, and an upper layer of Cu; C1'', the technical means is that the upper layer is made of two layers of Ni, Au, Pd, or Cr.
また、第２の発明である多層配線基板の製造方法は、セ
ラミック基板の主面上に、ポリイミド樹脂を絶縁層とす
る多層配線が施された多層配線基板であって、前記多層
配線の各配線層は、前記絶縁層−」−に、周期表の４Ａ
族または６Ａ族に属するいずれかの金属の薄膜および該
薄膜」二にＣｕの薄膜から成る薄膜層を形成し、該薄膜
上に、パターンメッキにてＣｕメッキおよび該ＣＩ４メ
ッキの」二にＮｉ、Ａｕ、Ｐｄ、またはＣ＋−メッキか
ら成るメッキ層を形成し、その後、エツチングにより不
要部分の前記薄膜層を除去することて形成されることを
技術的手段とする。A method for manufacturing a multilayer wiring board according to a second aspect of the present invention is a multilayer wiring board in which multilayer wiring with polyimide resin as an insulating layer is provided on the main surface of a ceramic substrate, wherein each wiring of the multilayer wiring 4A of the periodic table on the insulating layer.
A thin film layer consisting of a thin film of any metal belonging to Group 6A or Group 6A, and a thin film of Cu are formed on the thin film, and Cu plating is performed on the thin film by pattern plating, and Ni is plated on the CI4 plating. The technical means is to form a plating layer made of Au, Pd, or C+- plating, and then remove unnecessary portions of the thin film layer by etching.
なお、パターンメッキは、写真法または印刷法によって
、メッキ用しジス１〜での逆パターンを形成した後、そ
のパターン部にメッキを行う工程を言う。Note that pattern plating refers to a process in which a reverse pattern of plating resistors 1 to 1 is formed by a photographic method or a printing method, and then the pattern portion is plated.
Ｌｆｌ−用］
上記構成よりなる本発明は、多層配線の各配線層が、薄
膜層とパターンメッキによって形成されたメッキ層とか
ら構成されている。For Lfl-] In the present invention having the above configuration, each wiring layer of the multilayer wiring is comprised of a thin film layer and a plating layer formed by pattern plating.
薄膜層は、下層に形成された周期表の４Ａ族または６Ａ
族に属するいずれかの金属の薄膜が、絶縁層となるボリ
イミｌ−樹脂との密議性を確保し、上層に形成されたＣ
ｕの薄膜が、メッキ層のＣｕメッキとの密議性を確保す
る。The thin film layer is formed under the group 4A or 6A of the periodic table.
A thin film of one of the metals belonging to the group ensures secrecy with the polyimide resin that serves as the insulating layer, and the C
The thin film of u ensures confidentiality with the Cu plating of the plating layer.
メッキ層は、下層に形成されたＣｕメッキで各配線層の
厚みを確保し、上層に形成されたＮｉ、Ａ、ｕ、Ｐｄ、
またはＣｒのメッキか、不要部分の薄膜層を除去する際
に、エツチング液からＣｕメッキを保護する。The plating layer ensures the thickness of each wiring layer with Cu plating formed on the lower layer, and Ni, A, U, Pd, and
Alternatively, it protects the Cu plating from the etching solution when removing the Cr plating or unnecessary thin film layer.
［発明の効果］
本発明では、−１−記のように各配置１１７ｇの厚みを
メッキ層で確保することにより、各配線層の厚みをスパ
ッタリングで確保する従来技術と比較して、オーバエツ
チングの心配がなく、精度の良い配線パターンを形成す
ることができる。また、従来のスパッタ時間と比較して
、メッキに要する時間が短い（例えは５μｍのメッキで
約２５分）ため、配線の厚付は効率を向上させることか
できる。[Effects of the Invention] In the present invention, by ensuring a thickness of 117 g in each arrangement with a plating layer as described in -1-, over-etching is reduced compared to the conventional technology in which the thickness of each wiring layer is ensured by sputtering. A highly accurate wiring pattern can be formed without any worries. Furthermore, since the time required for plating is shorter than the conventional sputtering time (for example, about 25 minutes for 5 μm plating), thicker wiring can improve efficiency.
［実施例］
次に、本発明の多層配線基板およびその製造方法を図面
に示ず一実施例に基づき１悦明する。[Example] Next, a multilayer wiring board and a method for manufacturing the same according to the present invention will be described based on an example, not shown in the drawings.
第１図ないし第８図は、基板主面上への配線パターンの
形成過稈を示す説明図である。FIGS. 1 to 8 are explanatory diagrams showing over-formation of wiring patterns on the main surface of the substrate.
本実施例の多層配線基板は、セラミック基板１の主面上
に、ボリイミ１〜樹脂を各配線層間の絶縁層とする多層
配線が施されたものである。The multilayer wiring board of this embodiment has multilayer wiring formed on the main surface of a ceramic substrate 1 using polyimide 1 to resin as insulating layers between the wiring layers.
セラミック基板１は、例えば、アルミナを主原料として
作成された複数のクリーンシーＩ〜をｆｉ’＋上層して
、加湿雰囲気の水素炉中で高温ブ３“Ｌ成し゛（／ｊ（
られる多層基板である。For example, the ceramic substrate 1 is made by layering a plurality of clean sheets I~ made of alumina as the main raw material on fi'+, and forming a high-temperature bubble 3''L in a hydrogen furnace in a humidified atmosphere.
It is a multilayer board that can be used as a multilayer board.
以下に、セラミック基板１の主面上に配線パターンを形
成する過程を説明する。なお、第１図ないし第８図は、
多層配線の最下層の配線パターン（本発明の配線層）を
形成する過程を示すものである。The process of forming a wiring pattern on the main surface of the ceramic substrate 1 will be described below. In addition, Figures 1 to 8 are as follows:
It shows the process of forming the lowest layer wiring pattern (wiring layer of the present invention) of multilayer wiring.
ａ）あらかしめ研磨されたセラミック基板１の主面上に
、図示しない回転式塗布機（スピンコータ）により、−
・定精度に調整されたポリイミド樹脂を塗布し、加熱硬
イヒさせて、第１図に示すように、厚さ２５μｆｆ＋の
ポリイミド樹脂層２を形成する。a) On the main surface of the roughly polished ceramic substrate 1, -
- A polyimide resin adjusted to a certain precision is applied and hardened by heating to form a polyimide resin layer 2 with a thickness of 25 μff+, as shown in FIG.
ｂ）このポリイミド１カ脂層２の表面上に、ポリイミド
樹脂層２との密着性に優れるＣｒの薄膜（厚さ５００Ａ
、周期表の６Ａ族に属する）３と、後述するＣｕメッキ
（第６図参照）７との密着性を得るためのＣｕの薄膜（
厚さ５０００Ａ） 、４とをスパッタリングにより順
次形成する（第２図参照）。b) On the surface of this polyimide 1 resin layer 2, a thin Cr film (thickness 500A
, belonging to group 6A of the periodic table) 3 and Cu plating (see Figure 6) 7 described later.
5000A) and 4 are sequentially formed by sputtering (see FIG. 2).
Ｃ）次に、第３図に示すように、Ｃｕの薄膜４」二に、
６μｍの厚さてフオトレジス１〜５を塗布する。C) Next, as shown in FIG.
Photoresists 1 to 5 are applied to a thickness of 6 μm.
ｄ）そして、第４図に示すように、フォトマスク６を介
してパターン露光を行った後、現像処理により配線パタ
ーン部分のみフォトレジスト５を除去するく第５図参照
）。d) As shown in FIG. 4, after pattern exposure is performed through the photomask 6, the photoresist 5 is removed only from the wiring pattern portion by a development process (see FIG. 5).
ｅ）フォトレジス？−５が除去された部分に、電解メッ
キによって、配線の厚みを確保するＣｕメッキ（厚さ５
μｍ） ７と、上部配線層との絶縁層として形成され
るポリイミド樹脂く図示しない）との密着性を得るため
のＮｊメッキ（厚さ１μｍ）８とを順次形成するく第６
図参照）。e) Photoregis? The part where -5 was removed is electrolytically plated with Cu plating (thickness 5
(μm) 7 and Nj plating (1 μm thick) 8 to obtain adhesion to the polyimide resin (not shown) formed as an insulating layer with the upper wiring layer.
(see figure).
従って、本実施例の配線層は、Ｃｒの薄膜３とＣｕの薄
膜４の２層からなるＮＭ層と、Ｃｕメッキ７とＮｉメッ
キ８の２層からなるメッキ層とから構成されている。Therefore, the wiring layer of this embodiment is composed of an NM layer consisting of two layers, Cr thin film 3 and Cu thin film 4, and a plating layer consisting of two layers, Cu plating 7 and Ni plating 8.
ｆ）その後、第７図に示すように、残りのフォトレジス
ト５を除去し、さらに、エツチング処理によって不要部
分の薄膜層３．４を除去することて、所望の配線パター
ン９か形成される（第８図参照）。f) Thereafter, as shown in FIG. 7, the remaining photoresist 5 is removed, and the unnecessary portions of the thin film layer 3.4 are removed by etching to form a desired wiring pattern 9 ( (See Figure 8).
以後、」１下の配線層を導通させる導体柱（図示しない
）をパターンメッキにより形成するとともに、−に上層
配線層との絶縁層であるポリイミド樹脂層（図示しない
）を形成した後、上記ｂ）以降の工程を繰り返すことに
より多層配線か形成される。Thereafter, conductor pillars (not shown) that conduct the wiring layer below ``1'' are formed by pattern plating, and a polyimide resin layer (not shown) that is an insulating layer from the upper wiring layer is formed on ``1''. ) A multilayer wiring is formed by repeating the following steps.
このように、各配線層を、従来のようなエツチング法に
Ｊ：らず、パターンメッキ法によって形成したことによ
り、オーバエッチンクのおそれがなく、微細な配線パタ
ーンを精度良く形成することができる。また、メッキ層
を形成する際のメッキ時間（約２５分）が、従来のスパ
ッタ時間（約２時間）より短いため、配線の厚イ」け効
率を白土させることができる。In this way, each wiring layer is formed by pattern plating instead of the conventional etching method, so there is no risk of over-etching and fine wiring patterns can be formed with high precision. . Furthermore, since the plating time (approximately 25 minutes) for forming the plating layer is shorter than the conventional sputtering time (approximately 2 hours), the efficiency of wiring thickness can be improved.
さらには、エツチングで不要部分の薄膜層３．４を除去
する際に、ＣＩ４メッキ７の」１部にＮ〕メッキ８を形
成したため、エツチング液からＣＬＩメッキ７を保護す
ることがてき、配線の細りゃ配線強度の低下を防止する
ことかできる。Furthermore, when removing unnecessary portions of the thin film layer 3.4 by etching, N] plating 8 was formed on the first part of the CI4 plating 7, so the CLI plating 7 could be protected from the etching solution, and the wiring could be protected. If the wire is made thinner, a decrease in wiring strength can be prevented.
なお、上記実施例では、ポリイミド樹脂Ｊ＠ ２の上に
Ｃｒの薄ｊ摸３とＣｕの薄）模４の２層からなる薄膜層
を形成したが、Ｃｒの薄膜３の代わりに、周期表の４Ａ
族または６Ａ族に属するいずれかの金属を使用しても良
い。In the above example, a thin film layer consisting of two layers, Cr thin film 3 and Cu thin film 4, was formed on the polyimide resin J@2, but instead of the Cr thin film 3, the periodic table 4A of
Any metal belonging to Group 6A or Group 6A may be used.
また、Ｃｕメッキ７の」二部にＮｉメッキ８を形成した
が、Ｎｉメッキ８以外に、ＡｕメッキまたはＰｄメッキ
でも良い。なお、ポリイミド樹脂層２Ｆに形成する薄膜
層に、上記したＣｒの薄膜３以外の金属を使用した場合
には、Ｎ１メッキ８の代わりにＣｒメッキを形成しても
良い。Furthermore, although the Ni plating 8 is formed on the second part of the Cu plating 7, in place of the Ni plating 8, Au plating or Pd plating may be used. Note that if a metal other than the above-mentioned Cr thin film 3 is used for the thin film layer formed on the polyimide resin layer 2F, Cr plating may be formed instead of the N1 plating 8.
第１図ないし第８図は本発明の一実施例を示すものて、
基板］−画面上の配線パターンの形成過程を示す説明図
である。
図中
１・・セラミック基板
２・・ポリイミド樹脂層
３・・ Ｃｒの薄ｊ摸 （薄ＪＩ９Ｅ層）４・・・Ｃｕ
の薄膜（薄膜Ｍ）
７・・・Ｃｕメッキ（メッキ層）
８・・Ｎｉメッキ（メッキ層）
代
理
人
石
黒
健
１
へ −短 回
１１＋１． コ − ：ｌ づ ・−ヤ
易 ｏｏｏｚ
（Ｎ、−
く Ｃ）
Ｎ丁 Ｃコ1 to 8 show an embodiment of the present invention,
[Substrate] - An explanatory diagram showing a process of forming a wiring pattern on a screen. In the figure 1... Ceramic substrate 2... Polyimide resin layer 3... Thin Cr (JI9E layer) 4... Cu
Thin film (thin film M) 7...Cu plating (plating layer) 8...Ni plating (plating layer) To proxy Ken Ishiguro 1 - Short times 11+1. ko - :l zu ・-ya
Easy oooz (N, - く C) Ncho C co
Claims (1)
層とする多層配線が施された多層配線基板において、 前記多層配線の各配線層は、薄膜層と、該薄膜層上にパ
ターンメッキにて形成されたメッキ層とから構成され、 前記薄膜層は、下層に周期表の４Ａ族（Ｔｉおよびその
同族）または６Ａ族（Ｃｒおよびその同族）に属するい
ずれかの金属、上層にＣｕの２層から成り、 前記メッキ層は、下層にＣｕ、上層にＮｉ、Ａｕ、Ｐｄ
、またはＣｒの２層から成ることを特徴とする多層配線
基板。 ２）セラミック基板の主面上に、ポリイミド樹脂を絶縁
層とする多層配線が施された多層配線基板であって、 前記多層配線の各配線層は、 （ａ）前記絶縁層上に、周期表の４Ａ族または６Ａ族に
属するいずれかの金属の薄膜および該薄膜上にＣｕの薄
膜から成る薄膜層を形成し、 （ｂ）該薄膜上に、パターンメッキにてＣｕメッキおよ
び該Ｃｕメッキの上にＮｉ、Ａｕ、Ｐｄ、またはＣｒメ
ッキから成るメッキ層を形成し、（ｃ）その後、エッチ
ングにより不要部分の前記薄膜層を除去することで形成
されることを特徴とする多層配線基板の製造方法。[Scope of Claims] 1) A multilayer wiring board in which multilayer wiring with polyimide resin as an insulating layer is provided on the main surface of a ceramic substrate, wherein each wiring layer of the multilayer wiring includes a thin film layer and a thin film layer. and a plating layer formed by pattern plating on top, and the thin film layer has a lower layer containing any metal belonging to group 4A (Ti and its congeners) or group 6A (Cr and its congeners) of the periodic table, The plating layer consists of two layers of Cu on the upper layer, Cu on the lower layer and Ni, Au, and Pd on the upper layer.
A multilayer wiring board comprising two layers of , or Cr. 2) A multilayer wiring board in which multilayer wiring with polyimide resin as an insulating layer is provided on the main surface of a ceramic substrate, wherein each wiring layer of the multilayer wiring includes: (a) a periodic table on the insulating layer; (b) forming a thin film layer consisting of a thin film of any metal belonging to group 4A or group 6A on the thin film; A method for producing a multilayer wiring board, characterized by forming a plating layer made of Ni, Au, Pd, or Cr plating on the substrate, and (c) thereafter removing unnecessary portions of the thin film layer by etching. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24750089A JPH03108797A (en) | 1989-09-22 | 1989-09-22 | Multilayer wiring board and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24750089A JPH03108797A (en) | 1989-09-22 | 1989-09-22 | Multilayer wiring board and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03108797A true JPH03108797A (en) | 1991-05-08 |
Family
ID=17164393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24750089A Pending JPH03108797A (en) | 1989-09-22 | 1989-09-22 | Multilayer wiring board and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03108797A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5378310A (en) * | 1991-11-06 | 1995-01-03 | Fujitsu Limited | Method of producing conductive pattern layer structure |
| WO2008133369A1 (en) * | 2007-04-30 | 2008-11-06 | Top Engineering Co., Ltd | The manufacturing method of the thin film ceramic multi layer substrate |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51101864A (en) * | 1974-12-10 | 1976-09-08 | Western Electric Co | Hakumaku oyobi haiburitsudoshusekikaironotameno dodenshisutemu |
| JPS59151490A (en) * | 1983-02-18 | 1984-08-29 | 日本電気株式会社 | Wiring conductor of circuit board |
| JPS63143848A (en) * | 1986-12-08 | 1988-06-16 | Mitsubishi Electric Corp | Manufacture of microwave ic substrate |
| JPH01120094A (en) * | 1987-11-02 | 1989-05-12 | Ngk Spark Plug Co Ltd | Manufacture of high-strength thin-film wiring board |
-
1989
- 1989-09-22 JP JP24750089A patent/JPH03108797A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51101864A (en) * | 1974-12-10 | 1976-09-08 | Western Electric Co | Hakumaku oyobi haiburitsudoshusekikaironotameno dodenshisutemu |
| JPS59151490A (en) * | 1983-02-18 | 1984-08-29 | 日本電気株式会社 | Wiring conductor of circuit board |
| JPS63143848A (en) * | 1986-12-08 | 1988-06-16 | Mitsubishi Electric Corp | Manufacture of microwave ic substrate |
| JPH01120094A (en) * | 1987-11-02 | 1989-05-12 | Ngk Spark Plug Co Ltd | Manufacture of high-strength thin-film wiring board |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5378310A (en) * | 1991-11-06 | 1995-01-03 | Fujitsu Limited | Method of producing conductive pattern layer structure |
| US5415920A (en) * | 1991-11-06 | 1995-05-16 | Fujitsu Limited | Patterned chromium barrier layer with flange-like structure |
| WO2008133369A1 (en) * | 2007-04-30 | 2008-11-06 | Top Engineering Co., Ltd | The manufacturing method of the thin film ceramic multi layer substrate |
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