JPH03105915A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03105915A JPH03105915A JP24407989A JP24407989A JPH03105915A JP H03105915 A JPH03105915 A JP H03105915A JP 24407989 A JP24407989 A JP 24407989A JP 24407989 A JP24407989 A JP 24407989A JP H03105915 A JPH03105915 A JP H03105915A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- gas
- gaas
- layer
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 239000012495 reaction gas Substances 0.000 claims abstract description 29
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- 238000006243 chemical reaction Methods 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 14
- 239000007789 gas Substances 0.000 abstract description 84
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 52
- 238000010438 heat treatment Methods 0.000 abstract description 29
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000007493 shaping process Methods 0.000 abstract description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 44
- 150000002431 hydrogen Chemical class 0.000 description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 5
- 239000012159 carrier gas Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 125000004429 atom Chemical group 0.000 description 3
- 239000000376 reactant Substances 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 241000201776 Steno Species 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（概 要］
キャリアとなる電子ガスをｌ次元方向に移動させる半導
体装置の製造方法に関し、
ストライプ状に交互に形成される障壁層と導電層との境
界の断面を直線状に形成することを目的とし、
基板の表面に第一の反応ガスを供給すると同時に、前記
基板の温度を反応温度に上げ、この状態を所望時間保持
することにより、前記基板上に障壁層を形成し、この後
に、前記第一の反応ガスの供給を停止すると同時に、前
記基板の温度を低下させて前記基板表面の膜の戒長を停
止し、ついで第一の反応ガスを除去する第１の工程と、
前記基板の表面に第二の反応ガスを供給すると同時に、
前記基板の温度を反応温度に設定し、この状態を所望時
間保持することにより、前記基板上に導電層を形成し、
この後に、前記第二の反応ガスの供給を停止すると同時
に、前記基板温度を低下させて前記基板表面の膜の成長
を停止し、ついで、第二の反応ガスを除去する第２の工
程とを有するとともに、前記第ｌの工程と前記第２の工
程とを順に所望回数操り返すことによって障壁層と導電
層とを前記基板上に交互に形成することを含み構或する
。[Detailed Description of the Invention] (Summary) Regarding a method for manufacturing a semiconductor device in which electron gas serving as a carrier is moved in the l-dimensional direction, a cross section of a boundary between a barrier layer and a conductive layer that are alternately formed in a stripe shape is formed by straight lines. A barrier layer is formed on the substrate by supplying a first reaction gas to the surface of the substrate, raising the temperature of the substrate to the reaction temperature, and maintaining this state for a desired time. and then, at the same time, stopping the supply of the first reaction gas, lowering the temperature of the substrate to stop the formation of the film on the substrate surface, and then removing the first reaction gas. The process of
At the same time, supplying a second reaction gas to the surface of the substrate,
forming a conductive layer on the substrate by setting the temperature of the substrate to a reaction temperature and maintaining this state for a desired time;
After this, a second step of stopping the supply of the second reaction gas, simultaneously lowering the substrate temperature to stop the growth of the film on the substrate surface, and then removing the second reaction gas. and forming barrier layers and conductive layers alternately on the substrate by repeating the first step and the second step a desired number of times.
［産業上の利用分野〕
本発明は半導体装置の製造方法に関し、より詳しくは、
キャリアとなる電子ガスを１次元方向に移動させる半導
体装置の製造方法に関する。[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more specifically,
The present invention relates to a method for manufacturing a semiconductor device in which electron gas serving as a carrier is moved in a one-dimensional direction.
ｎ型アルミニウム・ガリウム砒素／ガリウム砒素（ｎ−
ＡＩＧａＡｓ ／ＧａＡｓ）等のようなヘテロ接合界面
に発生する２次元電子は高移動度を有しており、この性
質を利用した装置として、高移動度トランジスタ（｝Ｔ
ＥＭＴ）が提案されている。n-type aluminum gallium arsenide/gallium arsenide (n-
Two-dimensional electrons generated at heterojunction interfaces such as AIGaAs/GaAs) have high mobility, and high-mobility transistors (}T
EMT) has been proposed.
しかし、２次元電子の移動の際には結晶による弾性散乱
を伴うので、更に高速化を図るために、ｎ−ＡＩＧａＡ
ｓ／ＧａＡｓの幅を数＋１の細線状に形成し、この中に
電子を閉じ込めて電子の量子効果によって高速化を図る
技術が提案されている。However, since the movement of two-dimensional electrons involves elastic scattering by crystals, in order to further speed up the movement, n-AIGaA
A technique has been proposed in which the width of s/GaAs is formed into a thin line shape with a width of several +1, and electrons are confined within the line to increase the speed due to the quantum effect of the electrons.
このような装置として、例えば第６図に示すように、Ｇ
ａＡｓ基板５１の上に８ｎｍ幅を有するＡＩＡｓ膜５２
及びＧａＡｓ膜５３をストライプ状に交互に形成すると
ともに、その上にｎ型のＡＩＧａＡｓ層５４を積層し、
さらに、ＧａＡｓ膜５３の長手方向にソース電極５５、
ゲート電極５６及びドレイン電極５７を形成した半導体
装置が提案されており、この装置によれば、細線状のＧ
ａＡｓ膜５３に発生する電子ガスをＧａＡｓ膜５３の長
手方向、即ち１次元方向に移動させることが可能になる
。As such a device, for example, as shown in FIG.
AIAs film 52 having a width of 8 nm on an aAs substrate 51
and GaAs films 53 are alternately formed in a stripe pattern, and an n-type AIGaAs layer 54 is laminated thereon.
Further, a source electrode 55 is provided in the longitudinal direction of the GaAs film 53,
A semiconductor device in which a gate electrode 56 and a drain electrode 57 are formed has been proposed, and according to this device, a thin line-shaped G
It becomes possible to move the electron gas generated in the aAs film 53 in the longitudinal direction of the GaAs film 53, that is, in the one-dimensional direction.
この装置を形戒する方法としては、第７図に示すように
、例えばＧａｐｓ基板５ｌの上面となる（００ｆ）面か
ら１〜３゜傾けてＧａＡｓ基板５１を切り出すことによ
りその表面を階段状に形成し、その段差ｄを原子１個の
大きさにする。As shown in FIG. 7, a method for shaping this device is to cut out the GaAs substrate 51 at an angle of 1 to 3 degrees from the (00f) plane, which is the upper surface of the Gaps substrate 5l, so that the surface of the GaAs substrate 51 is shaped like a step. The step d is the size of one atom.
そして、このＧ ａ Ａ ｓ Ｍ仮５ｌを図示しないＭ
ＯＣＶ Ｄ （ｍｅｔａｌ ｏｒｇａｎｉｃ ｃｈｅｍ
ｉｃａｌ ｖａｐｏｒ ｄｅｐｏｓｉｔｉｏｎ）装置の
反応室に入れ、まず、ＧａＡｓ基板５１を７ｏＯ゜Ｃに
加熱し、その表面にアルシン、水素及びＴＭＡ（トリメ
チルアルごニウム）ガスを流し、ＧａＡｓ基仮５１上に
形成された段の垂直面にＡＩＡｓを付着し、このＡＩＡ
ｓを段のステップ面Ｓの奥行きの半分に達する位置まで
或長させる（第７図（ａ））。And, this G a A s M tentative 5l is M
OCV D (metal organic chem
First, the GaAs substrate 51 is heated to 70°C, and arsine, hydrogen, and TMA (trimethylalgonium) gases are flowed over the surface of the GaAs substrate 51 to form a GaAs group on the temporary 51. AIAs was attached to the vertical surface of the stepped step, and this AIA
s is lengthened to a certain extent until it reaches half the depth of the step surface S of the step (FIG. 7(a)).
次に、ＴＭＡガスをＴＭＧ （｝リメチルガリウム）ガ
スに切り換え、段のステンブ面Ｓ上の残り半分の領域に
ＧａＡｓを成長させる（第７Ｖ！Ｊ（ｂ））。Next, the TMA gas is switched to TMG (}limethylgallium) gas, and GaAs is grown in the remaining half region on the stent surface S of the stage (7th V!J(b)).
これにより、各段のステンプ面Ｓ上に原子１個分の厚さ
を有するＡＩＡｓ層５ ２とＧａＡｓ層５ ３とが形成
されるために、ＧａＡｓ基板５１の表面には複数のＡＩ
Ａｓ［５２とＧａＡｓ層５３とが面方向に交互に形成さ
れ、しかも、これらの層５２．５３によって形成される
面は階段状となる。As a result, an AIAs layer 52 and a GaAs layer 53 having a thickness of one atom are formed on the stamped surface S of each step, so that a plurality of AIAs layers are formed on the surface of the GaAs substrate 51.
As [52 and GaAs layers 53 are formed alternately in the plane direction, and the plane formed by these layers 52 and 53 has a step-like shape.
したがって、このような膜の戒長を交互に複数回行うこ
とにより、ＧａＡｓ基板５１の表面に膜厚１０００人程
度のＡＩＡｓ層５２及びＧａＡｓ層５３を交互に形成す
ることが可能になる（第７図（Ｃ））。Therefore, by alternately performing such film lengthening a plurality of times, it becomes possible to alternately form the AIAs layer 52 and the GaAs layer 53 with a film thickness of about 1000 layers on the surface of the GaAs substrate 51 (7th Figure (C)).
［発明が解決しようとする課題］
ところで、ＭＯＣＶＤ法によりＡ１＾Ｓ層５２及びＧａ
ＡｓＪｉ ５ ３をストライプ状に形成する場合には、
ＧａＡｓ基板５１を入れる反応室を７ ０ ０ ’Ｃに
ＪＪｎ熱しながら行い、その中にＴＭＡガスとＴ Ｍ
Ｇガスを一定時間交互に切り換えて流すようにしている
。[Problems to be Solved by the Invention] By the way, the A1^S layer 52 and the Ga
When forming AsJi 5 3 in stripes,
The reaction chamber containing the GaAs substrate 51 was heated to 700'C, and TMA gas and TM
The G gas is alternately switched for a certain period of time.
しかし、ガスの切り換えを行った直後においては、ＴＭ
ＡとＴＭＧが混合した状態となるため、段のステップ面
Ｓ上に堆積されるＡＩＡｓ層５２とＧａＡｓ層５３とを
均一の幅に戒長させることが難しくなり、これらの膜５
２．５３の境界の断面が第７図（ｃ）及び第８図に示す
ように凹凸になるため、ＧａＡｓ膜５３の長手方向に沿
って一次元的に移動する電子が散乱し易くなり、高移動
度の性質が十分に発揮されないといった問題がある。However, immediately after switching the gas, TM
Since A and TMG are in a mixed state, it becomes difficult to make the AIAs layer 52 and the GaAs layer 53 deposited on the step surface S of the step uniform in width.
Since the cross section of the boundary at 2.53 is uneven as shown in FIGS. 7(c) and 8, electrons moving one-dimensionally along the longitudinal direction of the GaAs film 53 are easily scattered, resulting in high There is a problem that the property of mobility is not fully exhibited.
本発明は、このような問題に鑑みてなされたものであっ
て、ストライプ状に交互に形成される＾ＩＡｓのような
障壁層と、ＧａＡｓのような導電層との境界の断面を直
線状に形成することができる半導体装置の製造方法を提
供することを目的とする。The present invention was made in view of these problems, and it is possible to make the cross section of the boundary between barrier layers such as IAs and conductive layers such as GaAs, which are alternately formed in stripes, into a straight line. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be formed.
上記した課題は、基板の表面に第一の反応ガスを｛Ｊｔ
給すると同時に、前記基板の温度を反応温度に上げ、こ
の状態を所望時間保持することにより、前記基板上に障
壁層を形成し、この後に、前記第一の反応ガスの供給を
停止すると同時に、前記基板の温度を低下させて前記基
板表面の膜の成長を停止し、ついで第一の反応ガスを除
去する第１の工程と、前記基板の表面に第二の反応ガス
を供袷すると同時に、前記基板の温度を反応温度に設定
し、この状態を所望時間保持することにより、前記基板
上に導電層を形戊し、この後に、前記第二の反応ガスの
供給を停止すると同時に、前記基板温度を低下させて前
記基板表筒の膜の成長を停止し、ついで、第二の反応ガ
スを除去する第２の工程とを有するとともに、前記第１
の工程と前記第２の工程とを順に所望回数繰り返すこと
によって障壁層と導電層とを前記基板上に交互に形成す
ることを特徴とする半導体装置の製造方法により解決す
る。The above-mentioned problem is solved by applying the first reaction gas to the surface of the substrate {Jt
At the same time as supplying the first reaction gas, the temperature of the substrate is raised to the reaction temperature and this state is maintained for a desired time to form a barrier layer on the substrate, and then, at the same time, the supply of the first reaction gas is stopped. A first step of lowering the temperature of the substrate to stop the growth of a film on the surface of the substrate, and then removing the first reaction gas, and simultaneously supplying a second reaction gas to the surface of the substrate, A conductive layer is formed on the substrate by setting the temperature of the substrate to the reaction temperature and maintaining this state for a desired time, and then, at the same time as stopping the supply of the second reaction gas, a second step of lowering the temperature to stop the growth of the film on the substrate surface cylinder, and then removing the second reaction gas;
The present invention is solved by a method for manufacturing a semiconductor device, characterized in that a barrier layer and a conductive layer are alternately formed on the substrate by repeating the step and the second step a desired number of times.
（作 用〕
本発明によれば、基板表面に第一の反応ガスを一定時間
供給するとともに、これに同朋させて反応ガスの反応温
度となるように基板を加熱することにより、基板表面の
一部領域に障壁層を形成し、この後に、加熱ランプを消
すと同時に第一の反応ガスの供給を停止して膜の戒長を
止め、ついで、第一の反応ガスを除去する。(Function) According to the present invention, the first reaction gas is supplied to the substrate surface for a certain period of time, and the substrate is simultaneously heated to the reaction temperature of the reaction gas, whereby a portion of the substrate surface is heated. After forming a barrier layer in the area, the heat lamp is turned off and at the same time the supply of the first reactant gas is stopped to stop the lengthening of the film, and then the first reactant gas is removed.
さらに、加熱ランプによる基板の加熱と、第二の反応ガ
スの供給とを一定時間同時に行うことにより、障壁層に
隣接する領域に導電層を形成し、この後に、加熱ランプ
の消灯とＴＭＡガスの供給停止とを同時に行って膜の戒
長を止めてから、第二の反応ガスを排気する。Furthermore, a conductive layer is formed in the region adjacent to the barrier layer by simultaneously heating the substrate with the heating lamp and supplying the second reaction gas for a certain period of time, and then turning off the heating lamp and supplying the TMA gas. After the supply is stopped at the same time and the membrane length is stopped, the second reaction gas is exhausted.
このような障壁層と導電層との形成を複数回繰り返し行
うと、膜厚を増やすことができ、しかも、障壁層と導電
層との境界がほぼ直線状に形成される。By repeating the formation of the barrier layer and the conductive layer a plurality of times, the film thickness can be increased, and the boundary between the barrier layer and the conductive layer can be formed in a substantially straight line.
なお、基板表面を階段状に形戒すると、第３図（ｅ）及
び第５図に例示するように、各段のステノブ面には障壁
層と導電層が隣接してストライプ状に形成されることに
なる。Note that when the substrate surface is shaped like steps, a barrier layer and a conductive layer are formed adjacent to each other in stripes on the steno knob surface of each step, as illustrated in FIGS. 3(e) and 5. It turns out.
以上のような方法により形成された障壁層と導電層との
境界は直線状になるため、導電層の長手方向、即ち一次
元方向に移動する電子の散乱は抑制され、高速移動を妨
げる要因を少なくすることができる。Since the boundary between the barrier layer and the conductive layer formed by the above method is linear, the scattering of electrons moving in the longitudinal direction of the conductive layer, that is, in one dimension, is suppressed, and the factors that impede high-speed movement are suppressed. It can be reduced.
そこで、以下に本発明の実施例を図面に基づいて説明す
る。Therefore, embodiments of the present invention will be described below based on the drawings.
第１図は、本発明の実施に使用するＭＯＣＶＤ装置の一
例を示す構或図であって、図中符号ｌは石英よりなる反
応室で、その一端にはガス供給口２が設けられ、他端に
はガス排気口３が形成され、また、反応室内１の底部に
は基板載置台４が取付けられ、さらに、反応室１の外部
には、基板載置台４上の基板１１表面を加熱する加熱ラ
ンプ５が取付けられており、ガス供給口２から供給され
た反応ガスの性質に応じた膜を基板１１の表面に形成す
るように構或されている。FIG. 1 is a configuration diagram showing an example of an MOCVD apparatus used for carrying out the present invention, in which reference numeral l represents a reaction chamber made of quartz, one end of which is provided with a gas supply port 2, the other end of which is a reaction chamber made of quartz. A gas exhaust port 3 is formed at the end, a substrate mounting table 4 is attached to the bottom of the reaction chamber 1, and a substrate 11 on the substrate mounting table 4 is heated on the outside of the reaction chamber 1. A heating lamp 5 is attached and is configured to form a film on the surface of the substrate 11 according to the properties of the reaction gas supplied from the gas supply port 2.
６は、２つのガス人口６ａ，６ｂと２つのガス出口６ｃ
，６ｄを有する第一の切換弁で、一方のガス人口６ａに
はＴＭＡ（｝リメチルアルミニウム）ガスが一定流量で
供給され、他方のガス人口６ｂには水素（Ｈ２）ガスが
一定流量で供給され、また、一方のガス出口６ｃには、
反応室１のガス供給口２に接続された第一のガス管７が
取付けられ、他方のガス出口６ｄにはガス放出用のガス
管１５が接続されている。6 has two gas populations 6a, 6b and two gas outlets 6c.
, 6d, one gas population 6a is supplied with TMA (}remethylaluminum) gas at a constant flow rate, and the other gas population 6b is supplied with hydrogen (H2) gas at a constant flow rate. In addition, one gas outlet 6c has
A first gas pipe 7 connected to the gas supply port 2 of the reaction chamber 1 is attached, and a gas discharge gas pipe 15 is connected to the other gas outlet 6d.
８は、２つのガス人口８ａ，８ｂと２つのガス出口８ｃ
，８ｄを備えた第二の切換弁で、一方のガス人口８ａに
はＴＭＧ （｝リメチルガリウム）ガスが一定流量で供
給され、他方のガス人口８ｂには水素（Ｈア）ガスが一
定流量で供給され、また、一方のガス出口８ｃには、反
応室ｌのガス供給口２に接続された第二のガス管９が取
付けられ、さらに、他方のガス出口８ｄにはガス放出用
のガス管１６が接続されている。8 has two gas populations 8a, 8b and two gas outlets 8c.
, 8d, one gas population 8a is supplied with TMG (}limethylgallium) gas at a constant flow rate, and the other gas population 8b is supplied with hydrogen (HA) gas at a constant flow rate. A second gas pipe 9 connected to the gas supply port 2 of the reaction chamber l is attached to one gas outlet 8c, and a gas for gas release is connected to the other gas outlet 8d. A tube 16 is connected.
ＩＯは、反応室１のガス供給口２に接続された第３のガ
ス管で、反応室１に常時供給するキャリアガスや反応ガ
スを一定量で流すように構成されている。IO is a third gas pipe connected to the gas supply port 2 of the reaction chamber 1, and is configured to flow a constant amount of carrier gas and reaction gas that are constantly supplied to the reaction chamber 1.
１１は、ガリウム砒素（ＧａＡｓ）基板で、このＧａＡ
ｓ基板の上面となる（００１）結晶面は、第３図（ａ）
に示すように階段状に形戊され、その段差ｄが原子１個
の大きさを有するとともに、その奥行きＷが１６ｎｍと
なるステップ面Ｓを有するように構或されている。11 is a gallium arsenide (GaAs) substrate;
The (001) crystal plane, which is the upper surface of the s-substrate, is shown in Figure 3(a).
As shown in the figure, it is shaped like a step, and has a step surface S in which the step d has the size of one atom and the depth W is 16 nm.
なお、図中符号１２は、第一及び第二の切換弁６，８の
切り換え、及び加熱ランプのＯＮ，ＯＦＦを制御する制
御回路を示している。Note that the reference numeral 12 in the figure indicates a control circuit that controls switching of the first and second switching valves 6 and 8 and turning on and off the heating lamp.
次に、本発明の一実施例を第１〜３図に基づいて説明す
る。Next, one embodiment of the present invention will be described based on FIGS. 1 to 3.
まず、第２図（ａ）に示すように、反応ガスとなるアル
シン（Ａｓｌｈ）と、キャリアガスとなる水素（Ｈ２）
ガスを流量１ ２ ｊ２／ｍｔｎで第３のガス管１０を
通して反応室１に供給するとともに、反応室ｌ内部の圧
力を減圧して７ ６ Ｔｏｒｒにする。First, as shown in Figure 2(a), arsine (Aslh) becomes a reaction gas and hydrogen (H2) becomes a carrier gas.
Gas is supplied to the reaction chamber 1 through the third gas pipe 10 at a flow rate of 1 2 j2/mtn, and the pressure inside the reaction chamber 1 is reduced to 7 6 Torr.
また、第二の切換弁８を切換えて、その第二の入口８ｂ
に入る水素ガスを第二のガス管９を通して反応室１内に
供給する一方、第一の入口８ａを通るＴＭＧガスを外部
に放出する。Also, the second switching valve 8 is switched to the second inlet 8b.
The entering hydrogen gas is supplied into the reaction chamber 1 through the second gas pipe 9, while the TMG gas passing through the first inlet 8a is discharged to the outside.
この状態において、第一の切換弁６を切換え、第一のガ
ス管７を通してＴＭＡガスを２．５ ｃｃ／ｍｉｎの流
量で反応室１に供給するとともに、この切換弁６の入口
６ｂに入った水素ガスを外方に放出する。In this state, the first switching valve 6 was switched, and TMA gas was supplied to the reaction chamber 1 at a flow rate of 2.5 cc/min through the first gas pipe 7, and the TMA gas entered the inlet 6b of this switching valve 6. Release hydrogen gas outward.
このＴＭＡガスの供給は３秒行い、この間に、加熱用ラ
ンブ５を点灯させて反応室ｌ内を７００“Ｃに保持する
。これにより、ＧａＡｓ基板１１上に形成された段の垂
直面Ｈとステップ面Ｓとの交差領域にＡＩＡｓが付着し
て戒長し、奥行きが８ｎｍとなる領域に第一の旧＾Ｓ層
２ｏが形成される（第３図（ａ））。The TMA gas is supplied for 3 seconds, and during this time the heating lamp 5 is turned on to maintain the inside of the reaction chamber 1 at 700"C. As a result, the vertical surface H of the step formed on the GaAs substrate 11 AIAs adheres and lengthens in the region intersecting with the step surface S, and a first old S layer 2o is formed in a region having a depth of 8 nm (FIG. 3(a)).
次に、この３秒が経過した時点で、第２図（ｂ）に示す
ように加熱用ランプ５を消灯させて反応室１内の温度を
ＴＭＡガスの反応温度以下にし、これと同時に第一の切
換弁６を切換えることにより、ＴＭＡガスを外部に放出
させるとともにキャリアガス（Ｈ２）を反応室ｌ内に供
給する。Next, when these 3 seconds have elapsed, the heating lamp 5 is turned off to bring the temperature inside the reaction chamber 1 below the reaction temperature of the TMA gas, as shown in FIG. By switching the switching valve 6, the TMA gas is released to the outside and the carrier gas (H2) is supplied into the reaction chamber 1.
したがって、反応室１内のＴＭＡガスは、低温下で水素
ガス等によって排気口３から放出され、約１分後には殆
ど除去されるので、この間、ＧａＡｓ基板１１上には膜
が戒長しないことになる。Therefore, the TMA gas in the reaction chamber 1 is released from the exhaust port 3 by hydrogen gas or the like at low temperature, and is almost removed after about 1 minute, so that no film is formed on the GaAs substrate 11 during this time. become.
この後に、第２図（ｃ）に示すように、第二の切換弁８
を切り換え、第二のガス管９を通してＴＭＧガスを２．
５ｃｃ／ＩＩＩｉｎの流量で反応室１に供給するととも
に、この切換弁８を通る水素ガスを外方に放出する。After this, as shown in FIG. 2(c), the second switching valve 8
2. Switch the TMG gas through the second gas pipe 9.
Hydrogen gas is supplied to the reaction chamber 1 at a flow rate of 5 cc/IIIin, and the hydrogen gas that passes through this switching valve 8 is discharged to the outside.
このＴＭＣガスの供給は３秒行い、これに同期させて加
熱用ランブ５を点灯し、反応室内を７００゜Ｃに保持す
る。これにより、ＧａＡｓ基仮１１上に形成された第一
のＡＩＡｓ層２０の垂直面Ｈと段のステップ面Ｓとの交
差領域にＧａＡｓが付着し始め、ステップ面Ｓの残りの
領域に第一のＧａＡｓ層２ｌが形成されることになる（
第３図（ｂ））．ついで、この３秒経過と同時に加熱用
ランブ５を消灯してＴＭＧガスの化学反応を停止した上
、第二の切換弁８を切換えてＴＭＧガスを外部に放出さ
せるとともに、キャリアガス（Ｈ２）を反応室１内に供
給すると、反応室１内のＴＭＧガスＬよキャリアガスに
よって排気口３から放出され、約１分後には殆ど除去さ
れるので、ＧａＡｓ基仮１１上には膜がそれ以上戒長し
ないことになる（第２図（ｂ〉）。This TMC gas is supplied for 3 seconds, and in synchronization with this, the heating lamp 5 is turned on to maintain the inside of the reaction chamber at 700°C. As a result, GaAs begins to adhere to the intersection area between the vertical surface H of the first AIAs layer 20 formed on the GaAs base layer 11 and the step surface S of the step, and the first AIAs layer 20 forms on the remaining region of the step surface S. A GaAs layer 2l will be formed (
Figure 3(b)). Then, at the same time as these 3 seconds have elapsed, the heating lamp 5 is turned off to stop the chemical reaction of the TMG gas, and the second switching valve 8 is switched to release the TMG gas to the outside, and at the same time, the carrier gas (H2) is turned off. When supplied into the reaction chamber 1, the TMG gas L in the reaction chamber 1 is discharged from the exhaust port 3 by the carrier gas, and most of it is removed after about 1 minute, so that no further film is deposited on the GaAs base 11. (Figure 2 (b)).
この工程を終えると、ＧａＡｓ基板１１表面の各ステン
プ面Ｓには、ＡＩＡｓｌｉ ２ ０とＧａＡｓｌｉ ２
１が隣接して形成されることになり、各ステンプ面Ｓ
に形成されたこれらの層２０．２１によって表面に新た
な階段面が形成される。After completing this step, each stamp surface S on the surface of the GaAs substrate 11 has AIAsli 2 0 and GaAsli 2
1 are formed adjacent to each other, and each stamp surface S
These layers 20,21 formed on the surface form a new step surface on the surface.
次に、加熱ランブ５を点灯させて、反応室１内を３秒間
７ ０ ０ ’Ｃにするとともに、これに同期させて第
一の切換弁６を切り換えることにより反応室１内にＴＭ
Ａガスを供給し、第一のＡＩＡｓ層２０のステンブ面と
第一のＧａＡｓＪ！ ２ １の垂直面との交差領域にＡ
ＩＡｓを付着させ、第一のＡＩＡｓ層２０上面と同一奥
行きとなる第二のＡＩＡｓ層２２を長させる（第２図（
ａ），第３図（Ｃ））。Next, the heating lamp 5 is turned on to bring the temperature inside the reaction chamber 1 to 700'C for 3 seconds, and in synchronization with this, the first switching valve 6 is switched so that the TM inside the reaction chamber 1 is turned on.
A gas is supplied, and the stencil surface of the first AIAs layer 20 and the first GaAsJ! 2 A in the area of intersection with the vertical plane of 1
IAs is deposited and the second AIAs layer 22 is lengthened to have the same depth as the top surface of the first AIAs layer 20 (see Fig. 2).
a), Figure 3 (C)).
この後に、加熱ランプ５の消灯と第一の切換弁の切換え
を同時に行い、ＧａＡｓ基板ｌ１上の膜の成長を停止さ
せる（第２図（ｂ））．
ついで、加熱ランブ５によって反応室ｌｌ内を３秒間７
００゜Ｃに上げると同時に、第二の切換弁８を切り換え
てＴＭＧガスを反応室１に供給し、第一のＧａＡｓ層２
１上に第二のＧａＡｓ層２３を形成する（第２図（Ｃ）
．第３図（ｄ））。After this, the heating lamp 5 is turned off and the first switching valve is switched on at the same time to stop the growth of the film on the GaAs substrate l1 (FIG. 2(b)). Then, the inside of the reaction chamber 11 is heated by heating lamp 5 for 3 seconds.
At the same time, the second switching valve 8 is switched to supply TMG gas to the reaction chamber 1, and the first GaAs layer 2 is heated to 00°C.
A second GaAs layer 23 is formed on 1 (FIG. 2(C)
．． Figure 3(d)).
以上のような加熱ランプ５のＯＮ−ＯＦＦと切換弁６，
８の切換えとを交互に行う（第４図）。ON/OFF of the heating lamp 5 and the switching valve 6 as described above,
8 switching is performed alternately (Fig. 4).
即ち、加熱ランブ５によりＧａＡｓ基板ｌ１を３秒間７
００゜Ｃに加熱するとともに、これに同期させてＧａＡ
ｓ基板１１表面にＴＭＡガスを供給することにより、Ｇ
ａＡｓ基＋７ｉ１１表面の段のステップ面Ｓの奥行き方
向の半分にＡＩＡｓ層を形成し、この後に、加熱ランブ
５を消すと同時にＴＭＡガスの供給を停止してＧａＡｓ
基板１１表面の膜の戒長を止め、ついで、ＴＭＡガスを
除去する。That is, the heating lamp 5 heats the GaAs substrate l1 for 3 seconds.
At the same time as heating to 00°C, GaA
By supplying TMA gas to the surface of the s-substrate 11, G
An AIAs layer is formed on the half of the step surface S of the step surface of the aAs group +7i11 surface in the depth direction, and then the heating lamp 5 is turned off and at the same time the supply of TMA gas is stopped to form a GaAs layer.
The growth of the film on the surface of the substrate 11 is stopped, and then the TMA gas is removed.
さらに、加熱ランブ５によるＧａＡｓ基板の７００゜Ｃ
の加熱と、ＴＭＧガスの供給とを３秒間同時に行うこと
により、段のステップ面Ｓの残り半分の領域にＧａＡｓ
層を形成し、この後に、加熱ランプの消灯とＴＭＡガス
の供給停止とを同時に行ってＧａＡｓ基板１表面の膜の
成長を止めてから、ＴＭＧガスを排気する。Furthermore, the heating lamp 5 heated the GaAs substrate to 700°C.
By simultaneously heating and supplying TMG gas for 3 seconds, GaAs is deposited on the remaining half region of the step surface S of the step.
After forming a layer, the heating lamp is turned off and the supply of TMA gas is stopped at the same time to stop the growth of the film on the surface of the GaAs substrate 1, and then the TMG gas is exhausted.
このようなＡＩＡｓ層とＧａＡｓ層との形戒を複数回繰
り返し行い、それぞれの膜厚を１０００入に形成した結
果、第３図（ｅ）及び第５図に示すように、ＡＩＡｓ層
３０とＧａＡｓ層３１との境界がほぼ直線状に形成され
た。As a result of repeating the formation of the AIAs layer 30 and the GaAs layer several times and forming each layer to a thickness of 1000, as shown in FIGS. 3(e) and 5, the AIAs layer 30 and the GaAs layer 30 The boundary with layer 31 was formed in a substantially straight line.
以上のような工程を経た後、第６図に示すように、ＡＩ
Ａｓ層３０及びＧａＡｓｌｌ ３ １め上にシリコンを
混入したＡＩＧａＡｓ層１３をエピタキシャル成長し、
その上にソース電極１４、ゲート電極１５、ドレイン電
極ｌ６の各電極を形成することになる。After going through the above steps, as shown in Figure 6, the AI
An AIGaAs layer 13 mixed with silicon is epitaxially grown on the As layer 30 and GaAsll 3 1st.
The source electrode 14, the gate electrode 15, and the drain electrode l6 are formed thereon.
この装置において、上記したＡ］ＡｓＪｉ ３ ０は障
壁層となるため、導電層となるＧａＡｓ層３１に発生す
る電子ガスは、ステップ面Ｓの奥行き方向への移動を妨
げられるために、ソース電極ｌ４からドレイン電極１６
方向、即ち、ＧａＡｓ層３１の長手方向に沿って１次元
方向に移動することになる。In this device, since the above-mentioned A]AsJi 3 0 serves as a barrier layer, the electron gas generated in the GaAs layer 31, which serves as a conductive layer, is prevented from moving in the depth direction of the step surface S. from the drain electrode 16
In other words, it moves in a one-dimensional direction along the longitudinal direction of the GaAs layer 31.
この場合、ＧａＡｓｌｌ３１とＡＩＡｓ層３０との境界
が直線状に形成されているため、その境界に沿って一次
元方向に進行する電子の散乱が抑制され、高速移動の妨
げる要因を少なくすることができる。In this case, since the boundary between the GaAsll 31 and the AIAs layer 30 is formed in a straight line, scattering of electrons traveling in a one-dimensional direction along the boundary is suppressed, and factors that hinder high-speed movement can be reduced. .
なお、上記した実施例は、ＧａＡ．Ｊ！：板１１に形成
した段のステップ面ＳにＡ１＾Ｓ層３ｏとＧａＡｓ層３
１とを形成する場合について述べたが、図示しないシリ
コン基板上に段を形成し、そのステップ面に障壁層とな
るシリコン層、導電層となるシリコンゲルマニウム層を
形成する場合にも、基板表面に供給する反応ガスを切り
換える際に、基板周囲の反応ガスの除去と基板加熱温度
の低下という新たな工程を加えることにより、障壁層と
導電層との境界の断面をほぼ直線状に形成することがで
きる．この場合、シリコン層を形成するための反応ガス
としてＳｉＨｎを使用し、シリコンゲルマニウム層を形
成するための反応ガスとしてＳ ｔ Ｈ４にＧｅＣｌｔ
を加えたガスをイ史用する。Note that the above-mentioned embodiments are based on GaA. J! :A1^S layer 3o and GaAs layer 3 on the step surface S of the step formed on the plate 11.
1 has been described, however, when forming steps on a silicon substrate (not shown) and forming a silicon layer to serve as a barrier layer and a silicon germanium layer to serve as a conductive layer on the step surface, it is also possible to form steps on the substrate surface. By adding a new process of removing the reactive gas around the substrate and lowering the substrate heating temperature when switching the reactive gas to be supplied, it is possible to form the cross section of the boundary between the barrier layer and the conductive layer into a nearly straight line. can. In this case, SiHn is used as a reactive gas to form a silicon layer, and GeClt is used in S t H4 as a reactive gas to form a silicon germanium layer.
The gas with which is added is then used.
また、ガリウムを含むＩｎ−Ｖ層化合物半導体を導電層
となし、これよりもバンドギャ・ンブの大きな材料によ
り障壁層を形成する場合にも、反応ガスの切り換えの際
に、一時的に基板温度を低くするとともに、基板上の反
応ガスを除去する工程を加え、各層の境界面を揃えるこ
ともできる。Furthermore, when using an In-V layer compound semiconductor containing gallium as a conductive layer and forming a barrier layer using a material with a larger band gap than this, the substrate temperature may be temporarily lowered when switching the reaction gas. In addition to lowering the thickness, it is also possible to add a step of removing the reactive gas on the substrate to align the boundary surfaces of each layer.
［発明の効果］
以上述べたように本発明によれば、基板表面に供給する
反応ガスを切り換える際に、基板周囲の反応ガスの除去
と基板加熱温度の低下という新たな工程を加えたので、
反応ガスの切り換えによってストライプ状に形戒される
障壁層と導電層との境界の断面がほぼ直線状に形成され
ることになり、導電層の長平方向、即ち一次元方向に移
動する電子の散乱は抑制され、高速移動を妨げる要因を
少なくすることが可能になる。[Effects of the Invention] As described above, according to the present invention, when switching the reactive gas supplied to the substrate surface, a new process of removing the reactive gas around the substrate and lowering the substrate heating temperature is added.
By switching the reactant gas, the cross section of the boundary between the striped barrier layer and the conductive layer is formed into a nearly straight line, and the scattering of electrons moving in the longitudinal direction of the conductive layer, that is, in one dimension. is suppressed, making it possible to reduce factors that hinder high-speed movement.
第１図は、本発明の一実施例に使用する装置の構或図、
第２図は、本発明の一実施例の動作説明図、第３図は、
本発明による膜の形戊過程を示す断面図、
第４図は、本発明に使用するガスの流景と基板温度の一
例を示すタイミングチャート、第５図は、本発明によっ
て形成したＡＩＡｓ層とＧａＡｓ層との境界の位置を示
す分布図、
第６図は、量子細線構造の半導体装置の一例を示す斜視
図、
第７図は、従来方法による膜の形成過程を示す断面図、
第８図は、従来方法によって形成したＡＩＡｓ層とＧａ
Ａｓ層との境界の位置を示す分布図である。
［符号の説明］
ｌ・・・反応室、
２・・・ガス供給口、
３・・・ガス排気口、
４・・・基板載置台、
５・・・加熱ランプ、
６・・・第一の切換弁、
８・・・第二の切換弁、
７．９．１０・・・ガス管、
１１・・・基板、
１２・・・制御回路、
２ ０． ２ ２． ３ ０−ＡｌＡＳ層、２ １
， ２ ３． ３ １＝ＧａＡｓ層。FIG. 1 is a diagram showing the configuration of an apparatus used in an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of an embodiment of the present invention, and FIG.
FIG. 4 is a cross-sectional view showing the process of forming the film according to the present invention. FIG. 4 is a timing chart showing an example of the gas flow and substrate temperature used in the present invention. FIG. A distribution diagram showing the position of the boundary with the GaAs layer, FIG. 6 is a perspective view showing an example of a semiconductor device with a quantum wire structure, FIG. 7 is a cross-sectional view showing the process of forming a film by a conventional method, and FIG. 8 is an AIAs layer formed by a conventional method and a Ga layer.
FIG. 3 is a distribution diagram showing the position of the boundary with the As layer. [Explanation of symbols] 1...Reaction chamber, 2...Gas supply port, 3...Gas exhaust port, 4...Substrate mounting table, 5...Heating lamp, 6...First Switching valve, 8... Second switching valve, 7.9.10... Gas pipe, 11... Board, 12... Control circuit, 2 0. 2 2. 3 0-AlAS layer, 2 1
, 2 3. 3 1=GaAs layer.
Claims (2)
、前記基板の温度を反応温度に上げ、この状態を所望時
間保持することにより、前記基板上に障壁層を形成し、
この後に、前記第一の反応ガスの供給を停止すると同時
に、前記基板の温度を低下させて前記基板表面の膜の成
長を停止し、ついで第一の反応ガスを除去する第１の工
程と、前記基板の表面に第二の反応ガスを供給すると同
時に、前記基板の温度を反応温度に設定し、この状態を
所望時間保持することにより、前記基板上に導電層を形
成し、この後に、前記第二の反応ガスの供給を停止する
と同時に、前記基板温度を低下させて前記基板表面の膜
の成長を停止し、ついで、第二の反応ガスを除去する第
２の工程とを有するとともに、 前記第１の工程と前記第２の工程とを順に所望回数繰り
返すことによって障壁層と導電層とを前記基板上に交互
に形成することを特徴とする半導体装置の製造方法。(1) Forming a barrier layer on the substrate by simultaneously supplying a first reaction gas to the surface of the substrate, raising the temperature of the substrate to the reaction temperature, and maintaining this state for a desired time;
After this, a first step of stopping the supply of the first reaction gas, simultaneously lowering the temperature of the substrate to stop the growth of the film on the surface of the substrate, and then removing the first reaction gas; At the same time as supplying the second reaction gas to the surface of the substrate, the temperature of the substrate is set to the reaction temperature and this state is maintained for a desired time to form a conductive layer on the substrate. a second step of stopping the supply of the second reaction gas, simultaneously lowering the substrate temperature to stop the growth of the film on the substrate surface, and then removing the second reaction gas; A method for manufacturing a semiconductor device, characterized in that barrier layers and conductive layers are alternately formed on the substrate by repeating the first step and the second step a desired number of times.
層と導電層とがストライプ状に構成された量子細線構造
をもって成長することを特徴とする請求項（１）記載の
半導体装置の製造方法。(2) The semiconductor device according to claim 1, wherein the surface of the substrate is formed in a stepwise manner, and the barrier layer and the conductive layer are grown to have a quantum wire structure configured in a stripe shape. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24407989A JPH03105915A (en) | 1989-09-19 | 1989-09-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24407989A JPH03105915A (en) | 1989-09-19 | 1989-09-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03105915A true JPH03105915A (en) | 1991-05-02 |
Family
ID=17113425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24407989A Pending JPH03105915A (en) | 1989-09-19 | 1989-09-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03105915A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05275678A (en) * | 1992-03-27 | 1993-10-22 | Daido Hoxan Inc | Semiconductor device |
| JPH05275679A (en) * | 1992-03-27 | 1993-10-22 | Daido Hoxan Inc | Manufacture of semiconductor device |
| US5296390A (en) * | 1990-04-09 | 1994-03-22 | Fujitsu Limited | Method for fabricating a semiconductor device having a vertical channel of carriers |
-
1989
- 1989-09-19 JP JP24407989A patent/JPH03105915A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5296390A (en) * | 1990-04-09 | 1994-03-22 | Fujitsu Limited | Method for fabricating a semiconductor device having a vertical channel of carriers |
| JPH05275678A (en) * | 1992-03-27 | 1993-10-22 | Daido Hoxan Inc | Semiconductor device |
| JPH05275679A (en) * | 1992-03-27 | 1993-10-22 | Daido Hoxan Inc | Manufacture of semiconductor device |
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