JPH03104559A - Method and jig for sticking semiconductor wafer to polishing block - Google Patents
Method and jig for sticking semiconductor wafer to polishing blockInfo
- Publication number
- JPH03104559A JPH03104559A JP1241916A JP24191689A JPH03104559A JP H03104559 A JPH03104559 A JP H03104559A JP 1241916 A JP1241916 A JP 1241916A JP 24191689 A JP24191689 A JP 24191689A JP H03104559 A JPH03104559 A JP H03104559A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- jig
- polishing block
- attaching
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005498 polishing Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims description 32
- 238000000034 method Methods 0.000 title claims description 16
- 239000000853 adhesive Substances 0.000 claims abstract description 10
- 230000001070 adhesive effect Effects 0.000 claims abstract description 10
- 235000012431 wafers Nutrition 0.000 claims description 51
- 238000001179 sorption measurement Methods 0.000 abstract 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000004744 fabric Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 235000009827 Prunus armeniaca Nutrition 0.000 description 1
- 244000018633 Prunus armeniaca Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- ORFSSYGWXNGVFB-UHFFFAOYSA-N sodium 4-amino-6-[[4-[4-[(8-amino-1-hydroxy-5,7-disulfonaphthalen-2-yl)diazenyl]-3-methoxyphenyl]-2-methoxyphenyl]diazenyl]-5-hydroxynaphthalene-1,3-disulfonic acid Chemical compound COC1=C(C=CC(=C1)C2=CC(=C(C=C2)N=NC3=C(C4=C(C=C3)C(=CC(=C4N)S(=O)(=O)O)S(=O)(=O)O)O)OC)N=NC5=C(C6=C(C=C5)C(=CC(=C6N)S(=O)(=O)O)S(=O)(=O)O)O.[Na+] ORFSSYGWXNGVFB-UHFFFAOYSA-N 0.000 description 1
- 238000010186 staining Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、研磨加工用のブロックに半導体ウェハを貼付
ける方法及び貼付けるための治只に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for attaching a semiconductor wafer to a polishing block and a jig for attaching the semiconductor wafer.
（従来の技術）
’Ｆ導体ウェハは、研磨用ブロックに貼付け、研磨砥粒
を用いて研磨テーブルの研磨クロスと摺動させることに
より、半導体ウェハ表面を平而状に研磨する。研磨用ブ
ロックに半導体ウェハを貼付ける方法には、真空吸着や
摩擦力などにより保持するワックスレス方法があり、こ
の方法は貼付け作業性、研磨後の洗浄の容易性、生産性
などの点で有利であるが、ウェハの平面度、ウェハ裏而
への研磨液の回り込みによる高部的なエッチングやステ
インの発生などの鏡面ウェハの品質面で問題があり、現
在はワックス等の接着剤で貼付ける方法が採用されてい
る。(Prior Art) A 'F conductor wafer is attached to a polishing block and is slid against a polishing cloth on a polishing table using polishing abrasive grains to flatten the surface of the semiconductor wafer. There is a waxless method for attaching a semiconductor wafer to a polishing block, which uses vacuum suction or frictional force to hold it, and this method is advantageous in terms of workability of attachment, ease of cleaning after polishing, and productivity. However, there are problems with the quality of the mirror wafer, such as the flatness of the wafer and the generation of etching and staining in high areas due to the polishing liquid getting around to the wafer's backside, so currently, wafers are pasted with adhesive such as wax. method has been adopted.
接着剤による貼付方法においても、研磨後のウェハ而内
の厚みバラツキが問題であり、これを低減するために、
研磨用ブロノクの貼付而及びウェハ表面を共に数ミクロ
ンオーダで仕上げ、塗布するワックスの厚さを可能な限
り均一にする工夫がなされてきた。例えば、ワックスの
厚さをできるだけ薄くしたり、ワックスの固化時に荷重
を加える方法が採られてきた。Even with adhesive attachment methods, variations in the thickness of the wafer after polishing are a problem, and in order to reduce this,
Efforts have been made to finish both the polishing pad and the wafer surface to the order of several microns, and to make the thickness of the applied wax as uniform as possible. For example, methods have been adopted to make the wax as thin as possible or to apply a load when the wax solidifies.
また、半導体ウェハは、その上にエビタキ７ヤル層を形
成させ、その表而のモフォロジーを整えたり、エビタキ
シャル層の厚さを制御することが要請されるため、エビ
タキシャル成長後の最表面を均一に研磨する必要性が生
じた。In addition, it is necessary to form an epitaxial layer on a semiconductor wafer, adjust the morphology of the surface, and control the thickness of the epitaxial layer. A need arose for uniform polishing.
しかし、エビタキシャル層かへテロ接合である場合には
、基板とエビタヰシャル層の結品格子定数や膨張率が丸
なるために大きなそりを示したり、厚さが不均一になる
ため、研磨用ブロックの貼付面に対して半導体ウエノ＼
の研磨而を平行に貼付保持することが難しく、エビタキ
シャル居の表面からの１磨される量が而内で不均一にな
るという問題があった。However, if the epitaxial layer is a heterojunction, the lattice constant and expansion coefficient of the substrate and the epitaxial layer become rounded, resulting in large warpage or non-uniform thickness. Semiconductor Ueno＼
There was a problem in that it was difficult to attach and hold the polished parts parallel to each other, and the amount of polishing from the surface of the epitaxial layer was uneven within the surface.
（発明が解決しようとする課題）
本発明は、」一記の問題を解消し、研磨用ブロックの貼
付面に対して半導体ウエノ＼の彼研磨而を平行に接着固
定する方法及び該方法を容易にする貼付用治具を提供し
ようとするものである。(Problems to be Solved by the Invention) The present invention solves the problems mentioned above, and provides a method for adhesively fixing a polishing block of a semiconductor wafer in parallel to the attachment surface of a polishing block, and a method that facilitates the method. The purpose of the present invention is to provide a pasting jig that can be used in various ways.
（課題を解決するための手段）
本発明は、（１）半導体ウェハを研磨用プロ・ノクに貼
付ける方法において、半導体ウエノ＼の披研磨而を貼付
け用治具の下而に真空吸青により固定し、半導体ウェハ
の′ｉ′テ面と研磨用ブロックとの間に接着剤を介在さ
せ、−１二記彼研磨而と研磨用ブロックの貼付面とを平
行に保持して該接着剤を硬化することを特徴とする半導
体ウェハの貼付け方法、及び、（２）’Ｆ導体ウェハを
研磨用ブロックに貼付けるための治１１において、該治
具は半導体ウェハを収容する四部と、その周囲に研磨用
ブロックの貼付而と接する凸部を有し、該凸部は上記四
部の゛１′導体ウェハと接する平面に対して該貼付面を
１Ｌ行に保持する形状を備え、かつ、」；記凹部には真
空排気系に連通ずる多数の開口を備えて半導体ウェハを
真空吸着可能としたことを特徴とする半導体ウェハの貼
付け用治具である。(Means for Solving the Problems) The present invention provides (1) a method for attaching a semiconductor wafer to a polishing professional, in which the polishing material of the semiconductor wafer is placed under the attachment jig by vacuum blue absorption. Fix the semiconductor wafer and place an adhesive between the surface of the semiconductor wafer and the polishing block. A method for attaching a semiconductor wafer characterized by curing, and (2) a jig 11 for attaching a 'F conductor wafer to a polishing block, the jig includes four parts that accommodate the semiconductor wafer and a surrounding part of the jig. It has a convex portion that comes into contact with the attachment surface of the polishing block, and the convex portion has a shape that holds the attachment surface in line 1L with respect to the plane that contacts the four ``1'' conductor wafers, and''; This jig for attaching semiconductor wafers is characterized in that the concave portion has a large number of openings communicating with a vacuum evacuation system so that semiconductor wafers can be vacuum-adsorbed.
（作用）
第１図は、本発明の貼付用治Ｉの１つの具体例を示した
概念図である。同図（ａ）は該治１１の側断面図であり
、（ｂ）は平面図である。(Function) FIG. 1 is a conceptual diagram showing one specific example of the adhesive patch I of the present invention. 3(a) is a side sectional view of the jig 11, and FIG. 2(b) is a plan view.
この治只は、半導体ウェハを収容する叩部へとその周囲
に研磨用ブロックの貼付而と接する凸部Ｂを有し、四部
Ａには多数の開「１１を有し、該開［−Ｊ ｌは真空排
気系２と連通している。第２図は、第１図の治具を用い
て半導体ウェハを６）■磨用ブロックに貼付ける手舶を
示した説明図である。図には、゛１′−導体基板の表面
にエビタキシャル成長を行い、ヘテロ接合を形！戊した
ウェハを例にして示した。このウェハは、エビタキシャ
ル屑側にそったもので、同図（ａ）は、貼付用治只の１
川部の接触而に対してエビタキンヤル屑を対向させて（
ｆｉ ｉｉ！５せしめた状態を示したものであり、（；
））は、該接触而に沿ってエビタキシャル表面を密行さ
せるように、”Ｉ’ ”；’体ウェハを貞空吸青させた
状態を示したものであり、（ｃ）は、該治巳の周囲の１
１１部を研磨用ブロソクの貼付而に接触させ、十４体ウ
ェハのエビタキシャル表而と研磨用ブロソクの貼付而と
を・１２行に保持し、：１′．Ｊｑ体ウェハの背面と研
磨用ブロ／クの間にワ，クスを介７Ｆ−．させ、この関
係を保持して固定する状鳴を示したものであり、（（Ｉ
）は、接？１後に±゛｛窄吸杏を解き、詠冶已を取り除
いた状鳴を小し７たものである。This jig has a convex part B that contacts the polishing block attached to the tapping part that accommodates the semiconductor wafer, and has a large number of openings 11 in the fourth part A, and the openings [-J 1 is in communication with the vacuum exhaust system 2. Fig. 2 is an explanatory diagram showing a device for attaching a semiconductor wafer to a polishing block using the jig shown in Fig. 1. This example shows a wafer in which a heterojunction is formed by epitaxial growth on the surface of a conductor substrate.This wafer is along the epitaxial waste side, and is ) is 1 of the adhesive for pasting.
With Kawabe's contact, Eita Kinyaru was facing him (
fiii! This shows the state in which the figure has reached 5.
)) shows the state in which the "I" body wafer is subjected to pure blue absorption so that the epitaxial surface closely follows the contact surface, and (c) shows the state where the "I"; 1 around
Part 11 is brought into contact with the attachment point of the polishing cloth, and the epitaxial surface of the 14-body wafer and the attachment point of the polishing cloth are held in line 12, and: 1'. 7F-. Put wax between the back of the Jq body wafer and the polishing block. and maintains and fixes this relationship, ((I
) is the connection? After 1, ±゛{constricted apricot is loosened and eiji 已 is removed, resulting in a smaller 7.
このように、本発明の貼付用冶貝を用いることにより、
半導体ウェハのエビタキシャル表而を該治具の凹部平而
に密着保持し、該エビタキシャル表面と貼付面を下行に
保持した状態で接着することができ、このまま研磨加ヱ
を施すときには、半導体ウェハの厚みのバラツキやそり
等にかかわらず、エビタキンヤル表面から均一に研磨す
ることができる。特に、＾ｌＧａＡｓ／ＧａＡｓ， Ｇ
ａＡｓ／ＧａＡｓ， ＧａＡｓ／Ｇｅ， ＧａＡｓ／Ｓ
ｉ等の、基板に対するエビタキシャル層の格子定数や膨
張率の異なるウェハの貼付けに有効である。In this way, by using the adhesive shell of the present invention,
The epitaxial surface of the semiconductor wafer can be held in close contact with the concave portion of the jig, and the epitaxial surface and the attachment surface can be bonded with the attachment surface held downward, and when polishing is performed as it is, the semiconductor wafer Regardless of variations in thickness or warpage, it is possible to uniformly polish the surface of the Evita spindle. In particular, ^lGaAs/GaAs, G
aAs/GaAs, GaAs/Ge, GaAs/S
This method is effective for attaching wafers with different lattice constants and expansion coefficients of epitaxial layers to substrates, such as wafers such as i.
（実施例）
内径５２ｍｍの四部を有する第１図の貼付用治貝を貼変
形の少ないアルミナセラミックで作製した。被研磨材料
としては、厚さ３００μｍのＧａＡｓ基板１二にエビタ
キシャル層厚さ２００μ箇の＾ＩＧａＡｓのエビタキシ
ャル層を成長させたものであり、ウェハのそりは約５０
０μ■、而内の厚みバラ゛ン半はｌＯμ一のものを用い
た。(Example) The pasting shell shown in FIG. 1 having four parts with an inner diameter of 52 mm was made of alumina ceramic, which causes little deformation of the pasting. The material to be polished was a GaAs substrate 12 with a thickness of 300 μm, on which an epitaxial layer of 200 μm of IGaAs was grown, and the warpage of the wafer was approximately 50 μm.
0μ■, while the inner thickness variation was 1Oμ.
−Ｌ記の貼付用治具に」二記ウェハを真空吸着し、１１
゜〔径２６５Ｉの研磨用ブロックの貼付而に８枚のウェ
ハをステンキワックス（日化１３ Ｉ 製）で目０’Ｃ
で順次貼付け、自然冷却で２５℃まで冷却してから、真
空を解いて貼付用治具を取り外した。- Vacuum adsorb the wafer described in "L" on the pasting jig, and
[8 wafers were attached to a polishing block with a diameter of 265I using stainless steel wax (manufactured by Nikka 13I) at 0'C.
The samples were sequentially pasted, and after cooling to 25° C. by natural cooling, the vacuum was released and the pasting jig was removed.
この状態で８枚のウェハについて、それぞれ面内５点づ
つ測定点を定めて研磨用ブロックの貼付而からの高さを
計測したところ、５３０μ■±５μ−の範囲に納めるこ
とができた。In this state, for each of the eight wafers, five measurement points were set on each surface and the height from the point where the polishing block was attached was measured, and the height was within the range of 530μ±5μ−.
この研磨用ブロノクをｆＡ＃３０ＱＱ（不二見研磨材］
二業製）の研磨剤で約ＩＯμ園ラッピングしてから、コ
ロイダルシリカ系の研磨剤と研磨布を用いて鏡面加工を
施した。研磨屋は、ラップと会わせて３０μｍ１５４ｍ
の範囲に仕−１二げることができた。This polishing bronok fA#30QQ (Fujimi Abrasives)
After lapping with an abrasive (manufactured by Nikyo Co., Ltd.) of about 10 μm, a mirror finish was applied using a colloidal silica abrasive and an abrasive cloth. The polisher is 30μm 154m including the lap
I was able to get within the range of -1-2.
（発明の効果）
本発明は、」一記の構成を採用することにより、研磨月
１ブロックの貼付而に対して半導体ウェハの被研磨而を
平行に接着固定することを可能にし、その結果、半導体
ウェハの形状に左石されることなく、ウェハ表面を任意
のｉｔだけ均一に研磨することを可能にした。(Effects of the Invention) The present invention makes it possible to adhesively fix the semiconductor wafer to be polished in parallel to the attachment of one polishing block by adopting the configuration described in section 1, and as a result, This makes it possible to uniformly polish the wafer surface by any desired distance without depending on the shape of the semiconductor wafer.
第１図は、本発明の貼付用治具の１つの只体例を示した
概念園である。同図（ａ）は該冶几の側断面図であり、
（ｂ）は平面図である。
第２図（ａ）〜（ｄ）は、第１図の貼付用治具を用いて
研磨用ブロックに半導体ウェハを貼付ける手順を示した
説明図である。FIG. 1 is a conceptual diagram showing one example of the pasting jig of the present invention. Figure (a) is a side cross-sectional view of the jig,
(b) is a plan view. FIGS. 2(a) to 2(d) are explanatory diagrams showing a procedure for attaching a semiconductor wafer to a polishing block using the attaching jig shown in FIG. 1.
Claims (2)
おいて、半導体ウェハの被研磨面を貼付け用治具の平面
に真空吸着により固定し、半導体ウェハの背面と研磨用
ブロックとの間に接着剤を介在させ、上記平面と研磨用
ブロックの貼付面とを平行に保持して該接着剤を硬化さ
せることにより、該被研磨面を該貼付面に平行に貼り付
けることを特徴とする半導体ウェハの貼付け方法。(1) In the method of attaching a semiconductor wafer to a polishing block, the surface to be polished of the semiconductor wafer is fixed to the flat surface of the attachment jig by vacuum suction, and an adhesive is applied between the back surface of the semiconductor wafer and the polishing block. Attaching a semiconductor wafer, characterized in that the surface to be polished is attached parallel to the attaching surface by holding the plane and the attaching surface of the polishing block parallel to each other and curing the adhesive. Method.
治具において、該治具は半導体ウェハを収容する凹部と
、その周囲に研磨用ブロックの貼付面と接する凸部を有
し、該凸部は上記凹部の半導体ウェハと接する平面に対
して該貼付面を平行に保持する形状を備え、かつ、上記
凹部には真空排気系に連通する多数の開口を備えて半導
体ウェハを真空吸着可能としたことを特徴とする半導体
ウェハの貼付け用治具。(2) A jig for attaching a semiconductor wafer to a polishing block, the jig having a recess for accommodating the semiconductor wafer and a protrusion around the recess that contacts the attachment surface of the polishing block; The recess has a shape that holds the attachment surface parallel to the plane in contact with the semiconductor wafer, and the recess has a large number of openings communicating with a vacuum exhaust system so that the semiconductor wafer can be vacuum-adsorbed. A jig for attaching semiconductor wafers, which is characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1241916A JPH03104559A (en) | 1989-09-20 | 1989-09-20 | Method and jig for sticking semiconductor wafer to polishing block |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1241916A JPH03104559A (en) | 1989-09-20 | 1989-09-20 | Method and jig for sticking semiconductor wafer to polishing block |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03104559A true JPH03104559A (en) | 1991-05-01 |
Family
ID=17081460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1241916A Pending JPH03104559A (en) | 1989-09-20 | 1989-09-20 | Method and jig for sticking semiconductor wafer to polishing block |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03104559A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100670762B1 (en) * | 2005-10-27 | 2007-01-17 | 삼성전자주식회사 | Apparatus and method for wafer back lap and tape mount |
| KR100914983B1 (en) * | 2008-01-10 | 2009-09-02 | 주식회사 하이닉스반도체 | Equipment for attaching bar-code label |
| US7682936B2 (en) | 2006-09-20 | 2010-03-23 | International Business Machines Corporation | Reduction in thickness of semiconductor component on substrate |
| US8165913B2 (en) | 2006-08-31 | 2012-04-24 | International Business Machines Corporation | System, method, program for assigning virtual attribute to product, and system, method, and program for tracing cause of phenomenon occurring in product |
-
1989
- 1989-09-20 JP JP1241916A patent/JPH03104559A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100670762B1 (en) * | 2005-10-27 | 2007-01-17 | 삼성전자주식회사 | Apparatus and method for wafer back lap and tape mount |
| US8165913B2 (en) | 2006-08-31 | 2012-04-24 | International Business Machines Corporation | System, method, program for assigning virtual attribute to product, and system, method, and program for tracing cause of phenomenon occurring in product |
| US7682936B2 (en) | 2006-09-20 | 2010-03-23 | International Business Machines Corporation | Reduction in thickness of semiconductor component on substrate |
| KR100914983B1 (en) * | 2008-01-10 | 2009-09-02 | 주식회사 하이닉스반도체 | Equipment for attaching bar-code label |
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