JPH03102908A - Channel selection device - Google Patents
Channel selection deviceInfo
- Publication number
- JPH03102908A JPH03102908A JP23993189A JP23993189A JPH03102908A JP H03102908 A JPH03102908 A JP H03102908A JP 23993189 A JP23993189 A JP 23993189A JP 23993189 A JP23993189 A JP 23993189A JP H03102908 A JPH03102908 A JP H03102908A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- point
- shaped output
- circuit
- afc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims description 7
- 230000010355 oscillation Effects 0.000 claims description 4
- 238000001514 detection method Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、テレビ受ｇＩ慎等に使用される選局装置に関
し、特にｐＬＬ周波数シンセサイザ方式を用いた選局装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a channel selection device used for television reception, etc., and particularly relates to a channel selection device using a pLL frequency synthesizer method.
従来の装置は、脣公昭５６ − ４５５２４号公報に記
載のように、同期信号等の信号及びＡＦＣ出力が適切か
否かにより判断し、適切な場合のみ正規同調点と見たす
方式を採るのが一般的であった。Conventional devices, as described in Japanese Publication No. 56-45524, employ a method in which a judgment is made based on whether or not signals such as a synchronization signal and AFC output are appropriate, and only when appropriate, the point is regarded as a normal tuning point. was common.
上記従来技術は、衛星放送による高ｖＩＩＩＭＪｉ度放
逸有料放送及びデータ放送、又はケーブル放送による有
料放送等の同期信号が容易に検出できない放送の場合，
正常に正規Ｐｌ調点に引込めない欠点があった。峙に衛
星放送の場合、屋外のコンバータユニットで一度中間周
波数に変換する方式では、厳しい環境変化による周波数
のドリ７トを無視できなく、また、ケープル放送では，
多チャンネル信号の伝送に伴なう妨害を軽減するために
送信周波数をオフセットしており、これらの放送に対応
不可能であった。本発明の目的は、かかる従来技術の欠
点を除外し、受信周波数の変化に対して安定に受イ１で
きる選局装置を提倶することにある。In the case of broadcasting in which synchronization signals cannot be easily detected, such as high-vIIIMJi-degree pay broadcasting and data broadcasting by satellite broadcasting, or pay broadcasting by cable broadcasting,
There was a drawback that the normal Pl adjustment point could not be drawn normally. In the case of satellite broadcasting, the method of converting the frequency once to an intermediate frequency using an outdoor converter unit cannot ignore frequency fluctuations caused by severe environmental changes, and in the case of cable broadcasting,
The transmission frequency was offset to reduce interference associated with multi-channel signal transmission, and it was not possible to support these broadcasts. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art and to provide a channel selection device that can stably respond to changes in reception frequency.
上記目的違戒のため、本発明では、同期信号が存在しか
つＡＦＣ出力が規定レベル範囲内にある場合のみ正規Ｐ
Ｉ調点とみなす第１の手段と、同期信号が存在し々くと
もＡＦＣ出力が規定レベル範囲内にある場合に正規同調
点とみなす第２の手段を傭えた。To avoid the above-mentioned purpose, in the present invention, the normal P
A first means for determining the I tuning point and a second means for determining the normal tuning point when the AFC output is within a specified level range even if a synchronizing signal is present.
第１の手段で、通常の同ＩＡｇｌ号が存在する放送信号
に対して正規同調点を探がし、正規同調点が見つかれば
その点で停止し、もし、同期信号が存在しなげれば、＠
２０手段で正規同調点を探がし正規同調点が見つかれば
その点で停止する。第１の手段及び褐２の手段を順次実
行すれば、通常の放送に対してはすばやく同調でき，有
料放送等の放送に対しても同調可能となる。In the first method, a normal tuning point is searched for the broadcast signal where the normal IAgl signal exists, and if the normal tuning point is found, it stops at that point, and if there is no synchronizing signal, @
The normal tuning point is searched by 20 means, and if the normal tuning point is found, the process stops at that point. If the first means and the second means are executed in sequence, it is possible to quickly tune in to normal broadcasts, and it is also possible to tune in to broadcasts such as paid broadcasts.
以下、第１図に例示した実施例により、本発明を具体的
に説明する。第１図において、１は選局用キーボード、
２は例えば２桁のチャンネル表示装置、３はコントロー
ラ、４はチ異一ナ、５はＡＦＣ回路、６はチューナ４の
局部発振出力を分周する固定分周器、７は固定分周器６
により分周された局部発振出力をさらに分゜周し、コン
トローラ５からの出力により分局比を変えることができ
る可変分周器、８は固定分周器６．可変分局器７で分周
された周波数と基準周波数とを比較し、この周波数が同
じにねるように誤差電圧を出力する位相比較器、９は位
相比較器８の誤差電圧から直流成分を取り出す低域フィ
ルタ、１０は基準発振器１１の出力を分局する固定分周
器、１２は前記ＡＦＣ回路の出力を判別するための第１
及びｍ２のスレツシ島ホールド電圧を有するＡＦＣ判別
助路である。Hereinafter, the present invention will be specifically explained using an example illustrated in FIG. In Figure 1, 1 is a keyboard for selecting channels;
2 is, for example, a two-digit channel display device, 3 is a controller, 4 is a channel converter, 5 is an AFC circuit, 6 is a fixed frequency divider that divides the local oscillation output of the tuner 4, and 7 is a fixed frequency divider 6.
A variable frequency divider which further divides the frequency of the local oscillation output frequency-divided by , and whose division ratio can be changed according to the output from the controller 5; 8 is a fixed frequency divider 6. A phase comparator compares the frequency divided by the variable divider 7 with a reference frequency and outputs an error voltage so that the frequencies are the same. 10 is a fixed frequency divider for dividing the output of the reference oscillator 11; 12 is a first frequency divider for determining the output of the AFC circuit;
and an AFC discrimination aid path having a threshold island hold voltage of m2.
１５は同期信号と水平パルスとの論理積１′Ｉｉ号を出
力する同期信号検出回路、ｉ４ ． １５はそれぞれ同
期信号入力端子および水平パルス入力端子である。15 is a synchronization signal detection circuit which outputs the logical product 1'Ii of the synchronization signal and the horizontal pulse; i4 . 15 are a synchronization signal input terminal and a horizontal pulse input terminal, respectively.
今、選局キーボード１よりあるチャンネル査号を入力す
ると，そのチャンネルに相当するデータがコントａ−ラ
３から可変分周器７に入力される。Now, when a certain channel code is inputted from the channel selection keyboard 1, data corresponding to that channel is inputted from the controller 3 to the variable frequency divider 7.
これによって可変分局器７に遜局されたチャンネルに対
応した分局比が設定される。次いで、固定分ＡＩ器６、
可変分周器７、位相比較器８、低域フィルタ９からなる
位相同期ループによるフィードバックにより、チューナ
４０局部発振周波数は希皇チャンネルに相当する周波数
に設定される。As a result, a division ratio corresponding to the channel that has been downtuned to the variable division divider 7 is set. Next, a fixed amount AI device 6,
Feedback from a phase-locked loop consisting of a variable frequency divider 7, a phase comparator 8, and a low-pass filter 9 sets the local oscillation frequency of the tuner 40 to a frequency corresponding to the rare channel.
このようにして設定された正規周改数に対して、受Ｃｍ
チャンネルの周波数がずれている場合について説明する
。For the normal cycle change number set in this way, the received Cm
A case where the channel frequencies are shifted will be explained.
第２図一》及び弟３図（α》は、第１図におげるＡＦＣ
回路５の周波数に対する出力電圧特性を示すグラフであ
り、検軸は受偵周波数，縦軸は出力電圧を示している。Figure 2 1》 and younger brother 3 (α》) are the AFCs listed in Figure 1.
It is a graph showing the output voltage characteristics with respect to the frequency of the circuit 5, where the axis of detection shows the detected frequency and the vertical axis shows the output voltage.
論２ １ＷＩｂ） ， ｋ＋及び第３図Ｉｌｌ） ＃
（ＣＩは、弟１図におげるＡＦＣ判別回路１２の周波数
に対する検出出力値号の特性を示すグラフであり、（旬
はＡＦＣＨレベル判定回路からの検出出力特性、（Ｃｌ
はＡＦＣＬレベル判定回路からの検出出力特性を示して
いる。Theory 2 1WIb), k+ and Figure 3 Ill) #
(CI is a graph showing the characteristics of the detection output value number with respect to the frequency of the AFC discrimination circuit 12 shown in Fig.
shows the detection output characteristics from the AFCL level determination circuit.
第２図（ｄｉ及び第３図＠）は、第１図における同期信
号検出回路１５の周波数に対する同期信号検出出力の件
性を示すグラフであり、Ｈレベルが同期無、Ｌレベルが
同期有を示す。FIG. 2 (di and FIG. 3 @) is a graph showing the characteristics of the synchronization signal detection output with respect to the frequency of the synchronization signal detection circuit 15 in FIG. 1, where H level indicates no synchronization and L level indicates synchronization. show.
第２図｛−１及び第５図（一》は，横軸に受信周波数、
縦軸に時間を示したものである。In Figure 2 {-1 and Figure 5 (1)}, the horizontal axis represents the receiving frequency;
The vertical axis shows time.
以下に、本実施例の動作についてさらに説明する。The operation of this embodiment will be further explained below.
弟２図（ｍｌにおいて、回図α点は、厳初に設定された
周波数を示し、ｂ点は次の設定周波数を示す。In the younger brother figure 2 (ml), the rotation point α indicates the frequency set exactly at the beginning, and the b point indicates the next set frequency.
α点〜α′点及び２点〜一′点の時間は位相同期ループ
、ＡＦＣ出力及び同期信号が安定するのを待つ時間であ
り、１点及びｂ′点でＡＦＣ出力及び同期信号の判別が
行々われる。α′点では回期は見つからずｂ′点で回期
が見つかるため、このｂ′点におげるＡＦＣ回路５の出
力電圧は第２のスレツシ島ホールド電圧より低くなるた
め受値周波数をダウンしようとする要求がコントローラ
５へ与えられる。The time from point α to α' and from point 2 to point 1' is the time to wait for the phase locked loop, AFC output and synchronization signal to become stable, and the AFC output and synchronization signal can be determined at point 1 and b'. It is carried out. Since a cycle is not found at point α' but a cycle is found at point b', the output voltage of the AFC circuit 5 at point b' becomes lower than the second threshold island hold voltage, so the received value frequency is lowered. A request to do so is given to the controller 5.
次にコントａ−ラ５は、可変分局器７の分周比を１だげ
ダウンさせる。このような手順をくり返し、ＡＦＣ出力
電圧が第１及び第２のスレツシ阜ホールド竃圧Ｖｒｌ＠
ａ ＶＴＩ＠の閲になると可変分局器７の分周比の変
化を停止させＣ点を最適同一点とする。一ＦＩＬｃ点を
受信すると、このＣ点を基準とし一定範囲内におげるＡ
Ｆ０１ｇ圧の変化に応答し常に最適ＩＷｌ一点を保つこ
とができる。Next, the controller 5 lowers the frequency division ratio of the variable divider 7 by one. By repeating these steps, the AFC output voltage reaches the first and second threshold hold voltage Vrl@
a When the VTI @ is reached, the change in the frequency division ratio of the variable divider 7 is stopped and the C point is made the optimum same point. When one FILc point is received, raise A within a certain range using this C point as a reference.
It is possible to always maintain a single optimum IWl point in response to changes in F01g pressure.
次に，ＡＦＣ出力が存在するが、同期が存在しない例を
示したものが第５図である。第５図（一》において、α
′点及びｂ′点でも同期便号が見つからないため探局範
ｄ内では同期信号が見つからないと判断し、受１６周波
数を探局範囲の上＠Ｏ点に設定する。この点から、可変
分局器７０分周比をＮだげダウンさせ、このような手順
をくり返してＡＦｃｗ力電圧が、弟１のスレツシ島ホー
ルド電圧ＶＴＩｇより低く、次のステップで弟２のスレ
ツシ一ホールド電圧より高くなった場合にＡＦＣ出力が
存在したと判断し（同図ｄ点），この点が見つかると、
この点では受僅周波数をアップしようとする費ボがコン
トＱ−ラ５へ与えられる．次に、可変分周器７の分周比
を１ずつアップさせ、ＡＦＣ出力電圧が第１及び第２の
スレツシエホールド電圧〆ｒｚｌｓ Ｖｒｌｇの間にな
ると可変分局器７の分局比の変化を停止させε点を最適
同調点とする。以降第２図による説明と同様の動作を行
なう。Next, FIG. 5 shows an example in which there is an AFC output but no synchronization. In Figure 5 (1), α
Since no synchronous flight number is found at points '' and b', it is determined that no synchronous signal is found within the search range d, and the receiving 16 frequency is set at the top of the search range @ point O. From this point, the frequency division ratio of the variable divider 70 is decreased by N, and this procedure is repeated until the AFcw voltage is lower than the threshold island hold voltage VTIg of the younger brother 1, and in the next step, the threshold island hold voltage of the younger brother 2 is lowered. If it becomes higher than the hold voltage, it is determined that the AFC output exists (point d in the figure), and when this point is found,
At this point, the burden of trying to raise the received frequency is given to controller Q-5. Next, the frequency division ratio of the variable frequency divider 7 is increased by 1, and when the AFC output voltage is between the first and second threshold voltages 〆rzlsVrlg, the change in the division ratio of the variable frequency divider 7 is increased. Stop and set the ε point as the optimum tuning point. Thereafter, operations similar to those described with reference to FIG. 2 are performed.
以上述べたように、本発明の選局装置によれば、受信チ
ャンネル周波数があらかじめ定められた分周比により決
定された周波数からずれており、かつ同期信号が存在す
る放送信号、または同期信号が存在しないか、存在する
がその検出が困難な放送信号に対して安定に自動微調機
能を働かせることができる。As described above, according to the channel selection device of the present invention, a broadcast signal in which the received channel frequency deviates from a frequency determined by a predetermined frequency division ratio and a synchronization signal is present, or a synchronization signal is detected. The automatic fine adjustment function can be operated stably for broadcast signals that do not exist or exist but are difficult to detect.
第１図は、本発明の一実施例を示すブロック図、納２図
はその動作態様の一例を示す動作波形図，第５図はその
動作態様の他の例を示す動作波形図、である。
１・・・選局用キーボード ５・・・コントローラ４・
・・チューナ ５・・・ＡＦｃ回路７・・・可
変分周器 ８・・・位相比較器１２・一ＡＦＣ判
別回路 １５・一同期信号検出回路代私弁理士小川勝
男
雨
図
雨２図
■
１時間Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is an operation waveform diagram showing an example of its operation mode, and Fig. 5 is an operation waveform diagram showing another example of its operation mode. . 1...Keyboard for tuning 5...Controller 4.
... Tuner 5 ... AFc circuit 7 ... Variable frequency divider 8 ... Phase comparator 12 - AFC discrimination circuit 15 - Synchronous signal detection circuit Private patent attorney Katsuo Ogawa Rain Diagram 2 Diagram ■ 1 time
Claims (1)
発振器（１１）からの出力と周波数および位相を位相比
較器（８）で比較し、チューナ（４）の同調電圧を制御
するＰＬＬ周波数シンセサイザ方式を用いた選局装置に
おいて、コントローラ（３）、該コントローラ（３）に
より分周比が制御される可変分周期（７）、前記チュー
ナ（４）に接続されたＡＦＣ回路（５）、前記ＡＦＣ回
路のＳ字出力を判別するＡＦＣ判別回路（１２）、およ
び受信した信号の同期を判別する信号判別回路（１３）
を具備するほか、第１の手段として、規定周波数を含む
一つ以上の受信周波数のポイントで前記信号判別回路（
１３）により同期が存在するかどうか調らべ、同期が存
在するポイントが見つかれば、少なくとも、前記ＡＦＣ
回路（５）のＳ字出力を検出できる周波数ステップで受
信周波数を可変し、同期信号が存在しかつ前記ＡＦＣ回
路（５）のＳ字出力が規定レベル範囲内にあった時に正
規同調点と見なし受信周波数の変化を停止させる前記コ
ントローラ（３）と、前記第１の手段で、いずれのポイ
ントでも同期が存在しない場合、第２の手段として、一
定の周波数範囲を上限から下限または下限から上限に向
かって、少なくとも前記ＡＦＣ回路（５）のＳ字出力を
検出できる周波数ステップで受信周波数を可変し、前記
Ｓ字出力が規定レベル範囲内にあった点を正規同調点と
見なし受信周波数の変化を停止させる前記コントローラ
（３）とを具備したことを特徴とする選局装置。 ２、請求項１に記載の選局装置において、正規同調点に
一度停止した後前記ＡＦＣ回路（５）のＳ字出力が規定
レベル範囲外になった場合、前記第１段階又は第２段階
で停止した受信周波数を基準としてある一定範囲内で、
前記Ｓ字出力が規定レベル範囲内になるように受信周波
数を変化させる前記コントローラ（３）を具備したこと
を特徴とする選局装置。[Claims] 1. The local oscillation frequency of the tuner (4) is divided, and the frequency and phase are compared with the output from the reference oscillator (11) using a phase comparator (8). In a tuning device using a PLL frequency synthesizer method for controlling a tuning voltage, a controller (3), a variable frequency divider (7) whose frequency division ratio is controlled by the controller (3), and a variable frequency divider (7) connected to the tuner (4) are connected to the tuner (4). an AFC circuit (5), an AFC discrimination circuit (12) that discriminates the S-shaped output of the AFC circuit, and a signal discrimination circuit (13) that discriminates the synchronization of the received signal.
In addition, as a first means, the signal discrimination circuit (
13) to check whether synchronization exists, and if a point where synchronization exists is found, at least the above AFC
The reception frequency is varied in frequency steps that can detect the S-shaped output of the circuit (5), and when a synchronization signal is present and the S-shaped output of the AFC circuit (5) is within a specified level range, it is regarded as a normal tuning point. If synchronization does not exist at any point in the first means, the controller (3) stops the change in the reception frequency; and the second means changes the fixed frequency range from the upper limit to the lower limit or from the lower limit to the upper limit. Then, the receiving frequency is varied in frequency steps at which the S-shaped output of the AFC circuit (5) can be detected, and the point where the S-shaped output is within a specified level range is regarded as a normal tuning point, and the change in the receiving frequency is detected. A channel selection device comprising: the controller (3) for stopping the channel. 2. In the tuning device according to claim 1, if the S-shaped output of the AFC circuit (5) falls outside the specified level range after once stopping at the regular tuning point, the first step or the second step is performed. Within a certain range based on the stopped receiving frequency,
A channel selection device comprising the controller (3) that changes the receiving frequency so that the S-shaped output falls within a specified level range.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1239931A JP2728517B2 (en) | 1989-09-18 | 1989-09-18 | Tuning device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1239931A JP2728517B2 (en) | 1989-09-18 | 1989-09-18 | Tuning device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03102908A true JPH03102908A (en) | 1991-04-30 |
| JP2728517B2 JP2728517B2 (en) | 1998-03-18 |
Family
ID=17051962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1239931A Expired - Lifetime JP2728517B2 (en) | 1989-09-18 | 1989-09-18 | Tuning device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2728517B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59152717A (en) * | 1983-02-18 | 1984-08-31 | Sony Corp | Channel selecting circuit of pll frequency synthesizer system |
| JPS59178013A (en) * | 1983-03-29 | 1984-10-09 | Pioneer Electronic Corp | Method for selecting channel of receiver |
-
1989
- 1989-09-18 JP JP1239931A patent/JP2728517B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59152717A (en) * | 1983-02-18 | 1984-08-31 | Sony Corp | Channel selecting circuit of pll frequency synthesizer system |
| JPS59178013A (en) * | 1983-03-29 | 1984-10-09 | Pioneer Electronic Corp | Method for selecting channel of receiver |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2728517B2 (en) | 1998-03-18 |
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