JPH029190A - Manufacture of ceramic circuit board with resistor - Google Patents
Manufacture of ceramic circuit board with resistorInfo
- Publication number
- JPH029190A JPH029190A JP63159822A JP15982288A JPH029190A JP H029190 A JPH029190 A JP H029190A JP 63159822 A JP63159822 A JP 63159822A JP 15982288 A JP15982288 A JP 15982288A JP H029190 A JPH029190 A JP H029190A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- layer
- ceramic substrate
- resistor layer
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 87
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000010410 layer Substances 0.000 claims abstract description 127
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 239000002184 metal Substances 0.000 claims abstract description 55
- 239000004020 conductor Substances 0.000 claims abstract description 40
- 239000011241 protective layer Substances 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 67
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 239000010949 copper Substances 0.000 claims description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 238000007747 plating Methods 0.000 abstract description 14
- 239000000126 substance Substances 0.000 abstract description 14
- 239000011521 glass Substances 0.000 abstract description 11
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 8
- 238000007650 screen-printing Methods 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000007740 vapor deposition Methods 0.000 abstract description 2
- 239000000853 adhesive Substances 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 238000007733 ion plating Methods 0.000 abstract 1
- 238000007788 roughening Methods 0.000 description 19
- 239000000463 material Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 238000010304 firing Methods 0.000 description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- 238000001035 drying Methods 0.000 description 8
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 6
- 238000009966 trimming Methods 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 239000002253 acid Substances 0.000 description 4
- 230000002411 adverse Effects 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- 239000012298 atmosphere Substances 0.000 description 4
- 238000013508 migration Methods 0.000 description 4
- 230000005012 migration Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 239000012808 vapor phase Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000010953 base metal Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- KRVSOGSZCMJSLX-UHFFFAOYSA-L chromic acid Substances O[Cr](O)(=O)=O KRVSOGSZCMJSLX-UHFFFAOYSA-L 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- AWJWCTOOIBYHON-UHFFFAOYSA-N furo[3,4-b]pyrazine-5,7-dione Chemical compound C1=CN=C2C(=O)OC(=O)C2=N1 AWJWCTOOIBYHON-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 229910000570 Cupronickel Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 description 1
- 229910052878 cordierite Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- JSKIRARMQDRGJZ-UHFFFAOYSA-N dimagnesium dioxido-bis[(1-oxido-3-oxo-2,4,6,8,9-pentaoxa-1,3-disila-5,7-dialuminabicyclo[3.3.1]nonan-7-yl)oxy]silane Chemical compound [Mg++].[Mg++].[O-][Si]([O-])(O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2)O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2 JSKIRARMQDRGJZ-UHFFFAOYSA-N 0.000 description 1
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052839 forsterite Inorganic materials 0.000 description 1
- HCWCAKKEBCNQJP-UHFFFAOYSA-N magnesium orthosilicate Chemical compound [Mg+2].[Mg+2].[O-][Si]([O-])([O-])[O-] HCWCAKKEBCNQJP-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052863 mullite Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- -1 steatite Chemical compound 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910052845 zircon Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、抵抗体付セラミ・７り回路板の製造方法に
関し、通常の配線用導体回路とともに抵抗体が形成され
たセラミック回路板を製造する方法に関するものである
。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a ceramic circuit board with a resistor, and a method for manufacturing a ceramic circuit board on which a resistor is formed along with a normal wiring conductor circuit. It's about how to do it.
抵抗体を含むセラミック回路板を製造する方法としては
、従来、焼結されたセラミック基板上に導体回路となる
Ａｇ／Ｐｄ等を主成分とする貴金属ペーストをスクリー
ン印刷等によって印刷するとともに、Ｒｕｂ、を主成分
とするフリット入りの抵抗体ペーストをスクリーン印刷
等によって印刷し、酸化雰囲気中において焼成すること
によって、導体回路と抵抗体を同時に形成する方法が一
般的であった。Conventionally, as a method for manufacturing a ceramic circuit board including a resistor, a noble metal paste mainly composed of Ag/Pd, etc., which becomes a conductive circuit, is printed on a sintered ceramic substrate by screen printing, etc., and Rub, A common method has been to print a resistor paste containing frits containing resistor paste as a main component by screen printing or the like, and then to bake it in an oxidizing atmosphere to form a conductive circuit and a resistor at the same time.
しかし、上記方法では、マイグレーションが発生し易く
、また配線抵抗も１０〜３０ｍΩ／口と高い。そこで、
最近、上記方法を改良して、マイグレージョンの防止や
配線抵抗の低減化とともにペースト材料の低コスト化を
図れる方法として、Ｃｕ等を主成分とする卑金属ペース
トとＬａＢ４、ＳｎＯ□等を主成分とするフリット入り
の抵抗体ペーストを組み合わせ、両者を窒素雰囲気中で
焼成して、導体回路と抵抗体を同時に形成する方法が盛
んになっている。However, in the above method, migration is likely to occur, and the wiring resistance is as high as 10 to 30 mΩ/hole. Therefore,
Recently, the above method has been improved to prevent migration, reduce wiring resistance, and reduce the cost of paste materials. A method of forming a conductive circuit and a resistor at the same time by combining resistor paste containing frits and firing both in a nitrogen atmosphere is becoming popular.
しかし、上記方法でも、導体金属ペーストをスクリーン
印刷しているため１００ｎ以下の微細配線の形成が困難
であるとともに、ペースト中にガラス質を含むためにハ
ンダ付着性が劣り、不良品が出やすく、使用時に故障を
起こし易いという問題がある。また、抵抗体ペーストを
窒素雰囲気中で焼成する必要があり、ペースト材料の完
成度が低いこともあって、従来の空気焼成用抵抗体ペー
ストに比べて、性能的に全ての面で充分に匹敵するとは
言えない。However, even with the above method, since the conductive metal paste is screen printed, it is difficult to form fine wiring of 100 nm or less, and since the paste contains glass, solder adhesion is poor, and defective products are likely to occur. There is a problem in that it is easy to break down during use. In addition, the resistor paste needs to be fired in a nitrogen atmosphere, and the paste material is less complete, so it is fully comparable in performance to conventional air-fired resistor pastes in all aspects. I can't say that I will.
一方、微細配線回路を形成する方法として、メタライジ
ング法によって、セラミック基板の表面に、ガラス質を
含まない導体金Ｅ、Ｎを形成し、写真製版技術等を用い
て回路を形成する方法が提案されている。しかし、この
方法は、抵抗体ペーストを焼成する際の高温で導体金属
層が酸化されるのを防止するために、不活性あるいは還
元性雰囲気で焼成しなければならないといった制約があ
るそこで、Ｒｕｂ、を主成分とする空気焼成用抵抗体ペ
ーストを印刷・焼成して抵抗体層を形成した後、抵抗体
層の上に保護層を形成し、セラミック基板の表面および
抵抗体層の露出部分全体を、強酸によって同時に粗化し
、ついで触媒・活性化処理を行った後、化学めっきまた
は化学めっきと電気めっきを施して導体金ｎＲを形成し
、この導体金属層をパターンエツチングして導体回路を
形成する方法が提案されており、特開昭６１−１８５９
９５号公報に開示されている。On the other hand, as a method for forming fine wiring circuits, a method has been proposed in which glass-free conductive gold E and N are formed on the surface of a ceramic substrate using a metallizing method, and a circuit is formed using photolithography technology. has been done. However, this method has limitations in that it must be fired in an inert or reducing atmosphere in order to prevent the conductive metal layer from being oxidized at the high temperatures used when firing the resistor paste. After forming a resistor layer by printing and firing an air-firing resistor paste containing as the main component, a protective layer is formed on the resistor layer, and the surface of the ceramic substrate and the entire exposed part of the resistor layer are coated. , simultaneously roughened with a strong acid, then subjected to catalyst/activation treatment, and then subjected to chemical plating or chemical plating and electroplating to form a conductive gold nR, and pattern etched this conductive metal layer to form a conductive circuit. A method has been proposed, published in Japanese Patent Application Laid-Open No. 61-1859.
It is disclosed in Publication No. 95.
また、前記したような各従来技術は、特開昭６１−２７
０８８５号公報、特開昭６１−１９４７９４号公報等に
開示されており、本願出願人は同様の技術について、特
願昭６１−３５７６７号および特願昭６３−６２３４７
号にて特許出願している。In addition, each of the above-mentioned conventional techniques is
0885, Japanese Patent Application Laid-Open No. 61-194794, etc., and the applicant of the present application has disclosed similar techniques in Japanese Patent Application No. 61-35767 and Japanese Patent Application No. 63-62347.
A patent application has been filed under No.
ところが、上記した特開昭６１−１８５９９５号公報に
開示の先行技術では、セラミック基板と導体回路あるい
は抵抗体層と導体回路との密着力を高めるために、セラ
ミック基板および抵抗体層の露出部分を強酸で粗化して
いるために、この粗化処理によって抵抗体層が侵され、
抵抗体層の性能品質に悪影ツを与えるという問題があっ
た。このような問題を起こさないためには、粗化処理を
、抵抗体層の性能品質に影響がない程度に抑えればよい
が、そうすると導体回路とセラミック基板および抵抗体
層との密着力が劣るものとなってしまう。However, in the prior art disclosed in JP-A-61-185995 mentioned above, in order to increase the adhesion between the ceramic substrate and the conductor circuit or between the resistor layer and the conductor circuit, the exposed portions of the ceramic substrate and the resistor layer are removed. Because it is roughened with strong acid, the resistor layer is attacked by this roughening treatment.
There is a problem in that it adversely affects the performance quality of the resistor layer. In order to prevent such problems from occurring, the roughening treatment should be kept to a level that does not affect the performance quality of the resistor layer, but this will result in poor adhesion between the conductor circuit, the ceramic substrate, and the resistor layer. It becomes a thing.
そこで、この発明の課題は、上記従来技術において、抵
抗体層の性能品質に悪影響を与えることなく、導体回路
とセラミック基板および抵抗体）昏との密着力を高める
ことのできる抵抗体付セラミック回路板の製造方法を提
供することにある。Therefore, an object of the present invention is to provide a ceramic circuit with a resistor that can improve the adhesion between the conductor circuit, the ceramic substrate, and the resistor without adversely affecting the performance quality of the resistor layer. The object of the present invention is to provide a method for manufacturing a board.
上記課題を解決する、この発明のうち、請求項１記載の
発明は、製造過程において以下の工程ｆｌ）〜（３）を
含むようにしている。Among the present inventions that solve the above problems, the invention according to claim 1 includes the following steps fl) to (3) in the manufacturing process.
（１） セラミック基板に抵抗体層を形成し、抵抗体
層の上に保護層を形成する工程。(1) A process of forming a resistor layer on a ceramic substrate and forming a protective layer on the resistor layer.
（２） セラミック基板表面および抵抗体層の露出部
分に対して、所定の回路パターンに対応する導体金属層
を形成する工程。(2) A step of forming a conductive metal layer corresponding to a predetermined circuit pattern on the surface of the ceramic substrate and the exposed portion of the resistor layer.
（３）導体回路が形成されたセラミック基板を加熱処理
する工程。(3) A step of heat treating the ceramic substrate on which the conductor circuit is formed.
請求項２記載の発明は、請求項１記載の発明の実施に際
し、加熱処理工程における加熱処理温度を、２００〜８
００℃で行うようにしている。The invention according to claim 2 is characterized in that when carrying out the invention according to claim 1, the heat treatment temperature in the heat treatment step is set to 200 to 8
I try to do it at 00℃.
請求項３記載の発明は、請求項１記載の発明の実施に際
し、導体回路を構成する金属として、銅ニッケル、金の
うちの何れかを使用するようにしている。According to the third aspect of the present invention, when implementing the first aspect of the present invention, either copper nickel or gold is used as the metal constituting the conductor circuit.
請求項１記載の発明によれば、導体回路が形成されたセ
ラミック基板を加熱処理することによって、導体回路と
セラミック基板および抵抗体層との密着力を高めること
ができる。According to the first aspect of the invention, by heat-treating the ceramic substrate on which the conductor circuit is formed, it is possible to increase the adhesion between the conductor circuit, the ceramic substrate, and the resistor layer.
請求項２記載の発明によれば、加熱処理温度を２００〜
８００℃に限定することによって、請求項１記載の発明
の作用を、より効果的に発揮させることができる。According to the invention described in claim 2, the heat treatment temperature is 200-
By limiting the temperature to 800°C, the effect of the invention described in claim 1 can be more effectively exerted.
請求項３記載の発明によれば、導体回路を銅。According to the third aspect of the invention, the conductor circuit is made of copper.
ニッケル、金で構成することによって、導体回路の性能
向上を図ることができる。By using nickel and gold, the performance of the conductor circuit can be improved.
第１図は、この発明にかかる抵抗体付セラミック回路板
の製造方法の１例を工程流れ図によって示しており、こ
れにしたがって順次説明を加える。また、第２図には、
製造された抵抗体付セラミック回路板の断面構造を示し
ている。FIG. 1 shows an example of a method for manufacturing a ceramic circuit board with a resistor according to the present invention in the form of a process flowchart, and explanations will be added sequentially according to the process flowchart. Also, in Figure 2,
The cross-sectional structure of the manufactured ceramic circuit board with a resistor is shown.
焼結されたセラミック基板１を用窓する。セラミック基
板１の材質は、アルミナ、フォステライト、ステアタイ
ト、ジルコニア、ムライト、コージライト ジルコン、
チタニア等の酸化物系セラミック材料を主に用いるが、
炭化物系あるいは窒化物系等、任意のセラミック材料を
使用することができる。The sintered ceramic substrate 1 is used. The materials of the ceramic substrate 1 are alumina, forsterite, steatite, zirconia, mullite, cordierite, zircon,
Oxide-based ceramic materials such as titania are mainly used, but
Any ceramic material can be used, such as carbide or nitride.
必要に応じて、セラミック基板１の表面を粗化する。こ
の粗化処理によって、後工程で形成される導体金属層２
と基板表面との密着力（いわゆるアンカー効果）を向上
させることができる。導体金ＫＮ２を気相法によって形
成する場合には、この粗化処理を行わなくてもよいが、
導体金属厄２を化学めっき法によって形成する場合には
、この粗化処理を行うことが好ましい。粗化処理の方法
は、セラミック基板ｌを、例えば、熱リン酸、溶融アル
カ、ワ、ＨＦ等の溶液中に浸漬する方法、あるいは研磨
やサンドブラスト等によって物理的に粗化する方法等が
あるが、その他の粗化処理方法も採用できる。If necessary, the surface of the ceramic substrate 1 is roughened. Through this roughening treatment, the conductive metal layer 2 formed in a later process is
It is possible to improve the adhesion between the substrate and the surface of the substrate (so-called anchor effect). When forming conductive gold KN2 by a vapor phase method, this roughening treatment is not necessary, but
When forming the conductive metal layer 2 by chemical plating, it is preferable to carry out this roughening treatment. Methods for roughening treatment include, for example, immersing the ceramic substrate l in a solution such as hot phosphoric acid, molten alkali, wax, HF, etc., or physically roughening it by polishing, sandblasting, etc. , other roughening treatment methods can also be employed.
セラミック基板１の所定の位置に、抵抗体ペーストをス
クリーン印刷等の手段で、所定のパターンになるように
塗布乾燥させる。その後、セラミック基板１とともに抵
抗体ペーストを焼成して、抵抗体層３を形成する。A resistor paste is applied to a predetermined position on the ceramic substrate 1 by means such as screen printing so as to form a predetermined pattern and dried. Thereafter, the resistor paste is fired together with the ceramic substrate 1 to form the resistor layer 3.
抵抗体ペーストは、Ｐｄ○／Ｐｄ／Ａｇ系もしくはＲｕ
ｂ、系等の抵抗成分を、Ｓｉ、Ｃａ、ＡＩ等の酸化物を
含むガラスや有機系ビヒクル等と混合してペースト化し
たもの等、通常の抵抗体形成用の材料が使用される。抵
抗体ペーストの使用にあたっては、セラミック基板の材
料と適合するものを選択して使用するのが好ましいが、
通常、最も安定した特性を有するＲ ｕ ＯＺ系のもの
が好適である。The resistor paste is Pd○/Pd/Ag type or Ru.
A conventional material for forming a resistor is used, such as a paste obtained by mixing a resistive component such as B and B with a glass containing an oxide such as Si, Ca, or AI, or an organic vehicle. When using a resistor paste, it is preferable to select one that is compatible with the material of the ceramic substrate.
Generally, R u OZ-based materials having the most stable properties are preferred.
抵抗体ペーストを乾燥および焼成する方法は、通常の抵
抗体形成方法と同様の方法で行われるが、例えば、つぎ
のような条件が一般的である。すなわち、スクリーン印
刷等によってセラミック基板１上に印刷された抵抗体ペ
ーストを、５０〜２００℃で乾燥させた後、成分中のガ
ラスフリットが熔融接合する温度、好ましくは５００〜
１１００℃、より好ましくは６００〜９５０℃の範囲で
焼成する。The method of drying and firing the resistor paste is carried out in the same manner as the usual method of forming a resistor, and for example, the following conditions are generally used. That is, after drying the resistor paste printed on the ceramic substrate 1 by screen printing or the like at 50 to 200°C, the temperature at which the glass frit in the components is melted and bonded is preferably 500 to 200°C.
Firing is performed at 1100°C, more preferably in the range of 600 to 950°C.
抵抗体層３の一部を覆って保護層４を形成する。この保
護層４は、抵抗体層３の耐熱性、耐湿性、耐薬品性等を
向上させ、抵抗値のドリフトを減少させるために形成す
る。保護層４は、後工程で抵抗体層３と導体金属層２と
を接続するための部分を除いて、抵抗体層３の全体を覆
うようにする。保護層４としては、従来の製造方法でも
用いられている、通常のオーバーコートガラスを用いる
ことができるが、このオーバーコートガラスの代わりに
、感光性ポリイミド、ポリイミド、エポキシ樹脂、トリ
アジン系材料等から形成された有機系あるいは無機系物
質で、後工程における粗化処理で使用される酸等に対し
て耐性のあるものからなる保護層４を用いるごともでき
る。A protective layer 4 is formed covering a portion of the resistor layer 3. This protective layer 4 is formed to improve the heat resistance, moisture resistance, chemical resistance, etc. of the resistor layer 3, and to reduce drift in resistance value. The protective layer 4 is designed to cover the entire resistor layer 3 except for a portion for connecting the resistor layer 3 and the conductive metal layer 2 in a later process. As the protective layer 4, normal overcoat glass that is also used in conventional manufacturing methods can be used, but instead of this overcoat glass, it is possible to use photosensitive polyimide, polyimide, epoxy resin, triazine-based materials, etc. It is also possible to use a protective layer 4 made of a formed organic or inorganic substance that is resistant to acids and the like used in the roughening treatment in the subsequent process.
保護層４の形成方法は、通常の方法で実施できるが、例
えば、つぎのような条件が一般的である。すなわち、ス
クリーン印刷法を用いて、前記抵抗体層３の一部を除く
全体を覆って、オーバーコート用ガラスペーストを印刷
形成した後、３００〜８００°Ｃでガラスペーストを焼
成することによって、保護層４を形成する。The protective layer 4 can be formed by a conventional method, but the following conditions are generally used, for example. That is, a glass paste for overcoat is printed to cover the entire resistor layer 3 except for a part using a screen printing method, and then the glass paste is baked at 300 to 800°C to provide protection. Form layer 4.
必要に応じて、抵抗体層３のうち、保護層４で覆われて
いない露出部分を粗化処理する。こうして粗化処理され
た抵抗体層３の露出部分の上に導体金属層２を形成すれ
ば、いわゆるアンカー効果によって、抵抗体層３と導体
金属層２との接続部分の密着性が向上する。粗化処理す
る方法は、前記したセラミック基板１の粗化処理で説明
した熱リン酸のような強い粗化作用を有する処理方法を
用いる必要はなく、比較的弱い粗化方法であっても、抵
抗体層３を粗化処理することができる。具体的な処理方
法としては、例えば、リン酸、フッ酸、クロム酸、硫酸
等の酸、あるいはＮａＯＨ等のアルカリ溶液を用いる方
法が通用できる。この粗化処理によって、抵抗体層３の
露出部分と同時に、保護層４やセラミック基板１の表面
がある程度粗化されても構わないが、保護層４による抵
抗体層３の保護効果や抵抗体層３の性能に悪影電！を与
えない程度の粗化処理方法を適用する。If necessary, exposed portions of the resistor layer 3 that are not covered with the protective layer 4 are roughened. If the conductive metal layer 2 is formed on the exposed portion of the resistor layer 3 that has been roughened in this way, the adhesion of the connection portion between the resistor layer 3 and the conductive metal layer 2 will be improved due to the so-called anchor effect. As for the roughening treatment method, it is not necessary to use a treatment method having a strong roughening effect such as the hot phosphoric acid described in the roughening treatment of the ceramic substrate 1 described above, and even if it is a relatively weak roughening method, The resistor layer 3 can be roughened. As a specific treatment method, for example, a method using an acid such as phosphoric acid, hydrofluoric acid, chromic acid, or sulfuric acid, or an alkaline solution such as NaOH can be used. Through this roughening treatment, the surface of the protective layer 4 and the ceramic substrate 1 may be roughened to some extent at the same time as the exposed portion of the resistor layer 3; Bad effects on layer 3 performance! Apply a roughening treatment method that does not cause
〔工程■〕
セラミック基板１の表面および抵抗体層３の露出部分全
体に導体金属層２を形成する。導体金属層２としては、
通常の導体回路の材料として用いられている各種の全屈
材料が用いられ、化学めっき、蒸着、スパッタリング、
イオンブレーティング等の、通常の薄膜形成手段のなか
から選ばれた任意の方法が通用できる。[Step (2)] A conductive metal layer 2 is formed on the surface of the ceramic substrate 1 and the entire exposed portion of the resistor layer 3. As the conductor metal layer 2,
Various full-flex materials used as materials for ordinary conductor circuits are used, including chemical plating, vapor deposition, sputtering,
Any method selected from ordinary thin film forming means, such as ion blating, can be used.
化学めっきの場合には、通常のセンシタイジングーアク
チベーション法を用いて、セラミック基板１表面に金属
パラジウムを析出させて表面を活性化させる。その後、
化学銅めっき浴あるいは化学ニッケルめっき浴等に、前
記活性化されたセラミック基板１を浸漬し、銅あるいは
ニッケル等の導体金属層２を形成させる。In the case of chemical plating, metal palladium is deposited on the surface of the ceramic substrate 1 to activate the surface using a normal sensitizing-activation method. after that,
The activated ceramic substrate 1 is immersed in a chemical copper plating bath or a chemical nickel plating bath to form a conductive metal layer 2 of copper, nickel, or the like.
蒸着、スパッタリング、イオンブレーティング等の気相
法、あるいはＣＶＤ法を用いて導体金属層２を形成する
こともできる。気相法を用いる場合、第１工程でＣｒま
たはＴｉの金Ｅ’Ｋｘを形成し、その上に第２工程とし
て銅またはニッケル等の金属層を形成させる方法や、４
００℃程度に加熱された粗面化済みのセラミック基板ｌ
に、上記同様のＣｒまたはＴｉの金属層および銅または
ニッケル等の金属層を順次形成する方法を採用すること
によって、セラミック基板ｌと薄＋１Ａ金属Ｗ１２との
密着力が増大する。The conductive metal layer 2 can also be formed using a vapor phase method such as evaporation, sputtering, or ion blasting, or a CVD method. When using a vapor phase method, there is a method in which gold E'Kx of Cr or Ti is formed in the first step, and a metal layer such as copper or nickel is formed thereon in the second step;
Roughened ceramic substrate heated to around 00℃
In addition, by employing a method of sequentially forming a metal layer of Cr or Ti and a metal layer of copper or nickel as described above, the adhesion between the ceramic substrate 1 and the thin +1A metal W12 is increased.
〔工程■］ 必要に応じて、導体金属層２の上に電解めっきを行う。[Process ■] Electrolytic plating is performed on the conductive metal layer 2, if necessary.
前記工程の化学めっき法や気相法等では、１〜数μｌの
薄い金属層しか形成出来ないので、導体回路として必要
な導体金属層２の厚みを分厚くするには、金ＨＥの厚付
けを行える電解めっき法を併用することが好ましい。In the chemical plating method, vapor phase method, etc. of the above process, only a thin metal layer of 1 to several μl can be formed, so in order to increase the thickness of the conductive metal layer 2 necessary for the conductive circuit, it is necessary to thicken the gold HE. It is preferable to use an electrolytic plating method that can be used in combination.
セラミック基板１および抵抗体層３の露出部分全体に形
成された導体金属層２を、エツチングによって、所定の
回路パターンに形成する。工・ノチングによる回路形成
の詳細については、通常の印刷回路板の製造方法と同様
に行われるので、具体的な工程の説明は省略する。この
ような、エツチングによる回路形成を行うと、配線抵抗
の小さな銅等の卑金属導体を使用して、線幅、線間３０
μ層という微細パターンを形成することが可能になるな
お、導体回路の形成手段としては、上記のように、セラ
ミック基板１の全体に形成された導体金属層２をエツチ
ングする方法のほか、予め回路パターンに対応するパタ
ーンを有するめっきレジスト層を形成しておき、回路パ
ターンに相当する部分のみに、めっき法で導体金属層２
を形成する方法等、エツチングを行わずに直接導体回路
を形成することもできる。その他、導体回路の形成手段
としては、通常の印刷回路板の製造方法で用いられる各
種の導体回路形成手段を適用することができる。The conductive metal layer 2 formed on the entire exposed portions of the ceramic substrate 1 and the resistor layer 3 is formed into a predetermined circuit pattern by etching. The details of circuit formation by notching and notching are carried out in the same manner as in the manufacturing method of a normal printed circuit board, so a detailed explanation of the steps will be omitted. When forming a circuit by etching, a base metal conductor such as copper, which has low wiring resistance, is used to increase the line width and line spacing by 30 mm.
It is possible to form a fine pattern called a μ layer.In addition to the method of etching the conductive metal layer 2 formed on the entire ceramic substrate 1 as described above, methods for forming the conductor circuit include the method of etching the conductive metal layer 2 formed on the entire ceramic substrate 1, as well as the method of etching the conductive metal layer 2 formed on the entire ceramic substrate 1 as described above. A plating resist layer having a pattern corresponding to the pattern is formed, and a conductive metal layer 2 is applied by plating only to the portion corresponding to the circuit pattern.
It is also possible to directly form a conductor circuit without etching, such as by forming a conductive circuit. In addition, various types of conductor circuit forming means used in ordinary printed circuit board manufacturing methods can be used as the conductor circuit forming means.
つぎに、導体金属層２が形成されたセラミック基板１を
、窒素雰囲気中で加熱処理する。処理温度は、２００〜
８００℃の範囲で行うのが好ましく、より好ましくは４
００〜７００℃の範囲内で実施する。この加熱処理によ
って、導体回路２と抵抗体層３およびセラミック基板１
が強固に密着する。特に、抵抗体層３と導体回路２との
接続個所における密着力が顕著に向上する。Next, the ceramic substrate 1 on which the conductive metal layer 2 is formed is heat-treated in a nitrogen atmosphere. The processing temperature is 200~
It is preferably carried out at a temperature of 800°C, more preferably 4
It is carried out within the range of 00 to 700°C. By this heat treatment, the conductor circuit 2, the resistor layer 3 and the ceramic substrate 1 are
adheres firmly. In particular, the adhesion strength at the connection points between the resistor layer 3 and the conductor circuit 2 is significantly improved.
処理時間は適宜に設定されるが、例えば１〜１００分程
度行われる。加熱雰囲気は、例えば窒素雰囲気中で行わ
れる。なお、必要であれば、上記加熱雰囲気中に、２〜
２００ｐｐｍ程度の微量の酸素を含んでいてもよい。但
し、上記加熱処理では、セラミック基板１の表面に形成
された抵抗体層３、導体金属層２．保護層４等の性能に
悪影グを及ぼさないように実施するのが好ましい。Although the processing time is set appropriately, it is performed for about 1 to 100 minutes, for example. The heating atmosphere is, for example, a nitrogen atmosphere. In addition, if necessary, in the above heating atmosphere, 2~
It may contain a trace amount of oxygen of about 200 ppm. However, in the above heat treatment, the resistor layer 3, the conductive metal layer 2. It is preferable to carry out the process so as not to adversely affect the performance of the protective layer 4 and the like.
〔工程０〕
必要に応じて、抵抗体層３のトリミングを行い、所望の
抵抗値に調整する。トリミングの方法は通常の抵抗体付
回路板と同様の方法が用いられ、例えば、アブレッジブ
トリミング、レーザートリミング等の方法がある。その
中でも、高速処理が行え、高性能なレーザートリミング
が、この発明の実施にとって、最も好ましいものである
。[Step 0] If necessary, the resistor layer 3 is trimmed to adjust to a desired resistance value. The trimming method is the same as that used for ordinary circuit boards with resistors, and examples thereof include abrasive trimming, laser trimming, and the like. Among these, laser trimming, which can perform high-speed processing and has high performance, is the most preferable for implementing the present invention.
以上のような各工程を経て、第２図に示すような、抵抗
体付セラミック回路板が製造される。Through the above steps, a ceramic circuit board with a resistor as shown in FIG. 2 is manufactured.
上記実施例において、薄膜金属層２０および導体金属層
２からなる導体回路を構成する全屈として、配線抵抗が
小さく安価な銅、ニッケル等の卑金属導体を使用するこ
とによって、線幅、線間３０μ層という微細パターンの
導体回路を安価に形成することができる。また、金を使
用すれば、マイグレーションの心配がなく、はんだ付は
性等が良好になる。In the above embodiment, by using base metal conductors such as copper and nickel, which have low wiring resistance and are inexpensive, as the total conductors constituting the conductor circuit consisting of the thin film metal layer 20 and the conductor metal layer 2, the line width and line spacing are 30 μm. Conductor circuits with fine patterns called layers can be formed at low cost. Furthermore, if gold is used, there is no worry of migration and the soldering properties are good.
ＲｕＯ□系等の空気焼成用抵抗体ペーストを使用すれば
、窒素焼成用抵抗体ペーストに比べて、高精度で高信頼
性の抵抗体層３を形成することができ、例えば、回路定
数に対する抵抗特性が±２％以内という、極めて高精度
な抵抗体Ｆｉ３を備えたセラミック回路板を製造するこ
とができる。By using an air-fired resistor paste such as RuO□, it is possible to form a resistor layer 3 with higher precision and reliability than with a nitrogen-fired resistor paste. It is possible to manufacture a ceramic circuit board equipped with an extremely highly accurate resistor Fi3 whose characteristics are within ±2%.
つぎに、この発明にかかる抵抗体付セラミ・７り回路板
の製造方法を実際に適用した具体的実施例について説明
する。Next, a specific example in which the method for manufacturing a ceramic circuit board with a resistor according to the present invention is actually applied will be described.
実施例１−
焼結セラミック基板１として、９６％アルミナ基板（４
”Ｘ４“Ｘ ０．６３５ｍｍ）を用い、この基板１を熱
リン酸に浸漬して、基板表面を均一に粗化した。粗化に
よって、表面粗さが最大粗さ２〜３μ園になった。粗化
処理の後、充分に洗浄して乾燥させた。乾燥後、セラミ
ック基板１の上にＲｕＯ２系の抵抗体ペース１−をスク
リーン印刷し、乾燥後、空気中８５０℃で焼成して抵抗
体層３を形成した。このあと、抵抗体層３のうち、導体
金属層２との接続部分となる一部を除いて全体を覆うよ
うに、オーバーコート用ガラスペーストをスクリーン印
刷し、乾燥させた後、空気中６００ ”Ｃの条件で焼成
して保護層４を形成した。抵抗体層３の露出部分に対し
て、５％のフン酸溶液を用いて粗化処理を行い、その後
充分に水洗および乾燥させた。Example 1 - As the sintered ceramic substrate 1, a 96% alumina substrate (4
The substrate 1 was immersed in hot phosphoric acid to uniformly roughen the surface of the substrate. As a result of roughening, the surface roughness reached a maximum roughness of 2 to 3 μm. After the roughening treatment, it was thoroughly washed and dried. After drying, a RuO2-based resistor paste 1- was screen printed on the ceramic substrate 1, and after drying, it was fired in air at 850°C to form a resistor layer 3. After that, an overcoat glass paste was screen printed to cover the entire resistor layer 3 except for a part that would be connected to the conductive metal layer 2, and after drying, it was exposed to air for 600 minutes. The protective layer 4 was formed by firing under the conditions of C. The exposed portion of the resistor layer 3 was roughened using a 5% hydrofluoric acid solution, and then thoroughly washed with water and dried.
セラミック基板１に、化学めっき法によって銅層を形成
し、さらに電解めっき法によって金属鋼の厚付けを行い
、合わせて厚み１０μの導体金属層２を形成した。その
後、５０ｐｐｍの酸素を含む窒素雰囲気中６００℃で加
熱処理を行った。この状態で、抵抗体層３の露出部分と
導体金属層２とは強固に接着しているとともに、導体金
属層２とセラミック基板１との密着力は２．０〜３．０
ｋｇ／ｍｍ”と、極めて高い値を示した。A copper layer was formed on the ceramic substrate 1 by chemical plating, and a thick layer of metal steel was further applied by electrolytic plating to form a conductive metal layer 2 having a total thickness of 10 μm. Thereafter, heat treatment was performed at 600° C. in a nitrogen atmosphere containing 50 ppm of oxygen. In this state, the exposed portion of the resistor layer 3 and the conductive metal layer 2 are firmly adhered, and the adhesion between the conductive metal layer 2 and the ceramic substrate 1 is 2.0 to 3.0.
kg/mm”, an extremely high value.
つｙに、導体金属層２に対して、写真製版技術を用いて
パターンエツチングを施し、線幅、線間５０μｍの導体
回路を形成した。このようにして得られた抵抗体付セラ
ミック回路板について、抵抗体層３の回路定数に対する
抵抗特性を測定したところ、±２％以内で高精度な値を
示した。その後、抵抗体層３の抵抗値が所望の値になる
ように、レーザートリマーでトリミング８周整すること
によって、第２図に示すような、抵抗体付セラミック回
路板が製造できた。Next, pattern etching was performed on the conductive metal layer 2 using photolithography to form a conductive circuit with a line width and line spacing of 50 μm. When the resistance characteristics of the resistor-equipped ceramic circuit board thus obtained with respect to the circuit constant of the resistor layer 3 were measured, it showed highly accurate values within ±2%. Thereafter, the resistor layer 3 was trimmed eight times with a laser trimmer so that the resistance value of the resistor layer 3 became a desired value, thereby producing a ceramic circuit board with a resistor as shown in FIG. 2.
一実施例２゛−
焼結セラミック基板１として、９２％アルミナ基板を用
い、ＮａＯＨ熔融塩に浸漬することによって、表面を最
大粗さ２〜３μ鴎程度に粗化処理した後、充分に洗浄し
て乾燥させた。乾燥後、セラミック基板１の上に、Ｒｕ
０ｇ系の抵抗体ペーストをスクリーン印刷し、乾燥させ
た後、空気中９００℃の条件で焼成して抵抗体層３を形
成した。Example 2 - A 92% alumina substrate was used as the sintered ceramic substrate 1, and the surface was roughened to a maximum roughness of 2 to 3 μm by immersing it in molten NaOH, and then thoroughly cleaned. and dried. After drying, Ru is placed on the ceramic substrate 1.
A 0 g resistor paste was screen printed, dried, and then fired in air at 900° C. to form a resistor layer 3.
このあと、抵抗体層３の所定部分を覆うように、オーバ
ーコート用ガラスペーストをスクリーン印刷し、乾燥さ
せた後、空気中５８０℃の条件で焼成して保護層４を形
成した。さらに、抵抗体層３の露出部分を、１０％のク
ロム酸溶液を用いて粗化し、充分に水洗・乾燥した。Thereafter, a glass paste for overcoat was screen printed to cover a predetermined portion of the resistor layer 3, dried, and then fired in air at 580° C. to form a protective layer 4. Furthermore, the exposed portion of the resistor layer 3 was roughened using a 10% chromic acid solution, thoroughly washed with water, and dried.
セラミック基板１の表面および抵抗体層３の露出部分の
全体に、化学めっき法のみで、厚み５μ−の銅層からな
る導体金属層２を形成した。その後、窒素雰囲気中６５
０℃で加熱処理を行った。A conductive metal layer 2 made of a copper layer having a thickness of 5 μm was formed on the surface of the ceramic substrate 1 and the entire exposed portion of the resistor layer 3 by chemical plating alone. Afterwards, 65% in a nitrogen atmosphere.
Heat treatment was performed at 0°C.
この状態で、抵抗体層３の露出部分と導体金属層２とは
強固に接着しているとともに、導体金属層２とセラミッ
ク基板１との密着力は２．０〜３．０ｋｇ／ｍｍ”と、
極めて高い値を示した。In this state, the exposed portion of the resistor layer 3 and the conductive metal layer 2 are firmly adhered, and the adhesion between the conductive metal layer 2 and the ceramic substrate 1 is 2.0 to 3.0 kg/mm''. ,
It showed an extremely high value.
つぎに、導体金属層２に対して、写真製版技術を用いて
パターンエツチングを施し、線幅、線間５０μ朧の導体
回路を形成した。このようにして得られた抵抗体付セラ
ミック回路板について、抵抗体層３の回路定数に対する
抵抗特性を測定したところ、±２％以内で高精度な値を
示した。その後、抵抗体層３の抵抗値が所望の値になる
ように、レーザー１−リマーでトリミング調整した。Next, pattern etching was applied to the conductive metal layer 2 using photolithography to form a conductive circuit with a line width and line spacing of 50 μm. When the resistance characteristics of the resistor-equipped ceramic circuit board thus obtained with respect to the circuit constant of the resistor layer 3 were measured, it showed highly accurate values within ±2%. Thereafter, trimming adjustment was performed using a laser 1-rimer so that the resistance value of the resistor layer 3 became a desired value.
一実施例３−
焼結セラミック基板１として、９９％アルミナ基板を用
い、この基板の表面をフン酸を用いて、最大粗さ１〜２
μ穐に粗化処理した後、充分に洗浄して乾燥させた。乾
燥したセラミック基板Ｉの上にＲｕＯ□系の抵抗体ペー
ストをスクリーン印刷し、乾燥させた後、空気中８５０
℃で焼成して抵抗体ｒ５３を形成した。抵抗体層３０所
定部分をミうように、オーバーコート用ガラスペースト
をスクリーン印刷し、乾燥させた後、空気中６００ ’
Ｃで焼成して保護層４を形成した。Example 3 - A 99% alumina substrate is used as the sintered ceramic substrate 1, and the surface of this substrate is coated with hydrochloric acid to a maximum roughness of 1 to 2.
After the roughening treatment was carried out to give μ axes, they were thoroughly washed and dried. A RuO□-based resistor paste was screen printed on the dried ceramic substrate I, and after drying, it was
C. to form a resistor r53. A glass paste for overcoat was screen-printed so as to cover a predetermined portion of the resistor layer 30, and after drying, it was dried in air for 600'.
A protective layer 4 was formed by firing with C.
つぎに、抵抗体層３の露出部分を１０％の硫酸溶液を用
いて粗化し、充分に水洗・乾燥した後、スパッタリング
法によって！ＰＩ層を形成し、さらに電解めっき法によ
って金属銅の厚付けを行い、厚み１２ｎの導体金属層２
を形成した。その後、７０ ｐｐｍの酸素を含む窒素雰
囲気中において６００℃で加熱処理を行った。Next, the exposed portion of the resistor layer 3 is roughened using a 10% sulfuric acid solution, thoroughly washed with water, dried, and then sputtered! A PI layer is formed, and metal copper is further thickened by electrolytic plating to form a conductive metal layer 2 with a thickness of 12n.
was formed. Thereafter, heat treatment was performed at 600° C. in a nitrogen atmosphere containing 70 ppm of oxygen.
この状態で、抵抗体層３の露出部分と導体金属層２とは
強固に接着しているとともに、導体金属層２とセラミッ
ク基板１との密着力は２．０〜３．０ｋｇ／ｍｍ”と、
極めて高い値を示した。In this state, the exposed portion of the resistor layer 3 and the conductive metal layer 2 are firmly adhered, and the adhesion between the conductive metal layer 2 and the ceramic substrate 1 is 2.0 to 3.0 kg/mm''. ,
It showed an extremely high value.
つぎに、導体金属層２に対して、写真製版技術を用いて
パターンエツチングを施し、線幅、線間５０μの導体回
路を形成した。このようにして得られた抵抗体付セラミ
ック回路板について、抵抗体層３の回路定数に対する抵
抗特性を測定したところ、±２％以内で高精度な値を示
した。その後、抵抗体層３の抵抗値が所望の値になるよ
うに、レーザートリマーでトリミング調整した。Next, pattern etching was applied to the conductive metal layer 2 using photolithography to form a conductive circuit with a line width and a line spacing of 50 μm. When the resistance characteristics of the resistor-equipped ceramic circuit board thus obtained with respect to the circuit constant of the resistor layer 3 were measured, it showed highly accurate values within ±2%. Thereafter, trimming was performed using a laser trimmer so that the resistance value of the resistor layer 3 became a desired value.
一実施例４−
セラミンク基板ｌとして９６％アルミナ基板を用い、抵
抗体ペーストをセラミック基板１上に、所定の形状にな
るように直接描画した以外は、前記実施例２と同様の工
程で、抵抗体付セラミック回路板を製造した。その結果
、得られたセラミック回路板の抵抗体層３の抵抗値のバ
ラツキは、実施例２と同様の優れた特性を有するもので
あった一実施例５−
焼結セラミック基板として、９９％アルミナ基板を用い
、導体金属層２となる銅層を、電解めっきを行わず、化
学めっきのみで厚み８μｍになるように形成した以外は
、実施例１と同様の工程で、抵抗体付セラミック回路板
を製造した。その結果、得られたセラミック回路板の抵
抗体層３の抵抗値のバラツキは、実施例１と同様の優れ
た特性を有するものであった。Example 4 - A resistor was fabricated in the same process as in Example 2, except that a 96% alumina substrate was used as the ceramic substrate 1, and the resistor paste was directly drawn on the ceramic substrate 1 in a predetermined shape. A ceramic circuit board with a built-in body was manufactured. As a result, the variation in the resistance value of the resistor layer 3 of the obtained ceramic circuit board had the same excellent characteristics as in Example 2.Example 5 - As a sintered ceramic substrate, 99% alumina A ceramic circuit board with a resistor was produced using the same steps as in Example 1, except that the copper layer, which would become the conductive metal layer 2, was formed using a substrate to a thickness of 8 μm only by chemical plating without electrolytic plating. was manufactured. As a result, the variation in the resistance value of the resistor layer 3 of the obtained ceramic circuit board had the same excellent characteristics as in Example 1.
以上に述べた、この発明にかかる抵抗体付セラミック回
路板の製造方法のうち、請求項１記載の発明によれば、
抵抗体層および保護層が形成されたセラミンク基板の表
面および抵抗体層の露出部分に導体回路を形成した後、
加熱処理を行うことによって、導体回路と抵抗体層およ
びセラミック基板との密着力を大幅に高めることができ
た。この加熱処理では、従来の粗化処理のように、抵抗
体層に悪影響を与える心配がないため、高精度で高信頼
性の抵抗体層を有するセラミック回路板を製造すること
ができる。According to the invention described in claim 1 of the method for manufacturing a ceramic circuit board with a resistor according to the present invention described above,
After forming a conductor circuit on the surface of the ceramic substrate on which the resistor layer and protective layer are formed and on the exposed portion of the resistor layer,
By performing the heat treatment, it was possible to significantly increase the adhesion between the conductor circuit, the resistor layer, and the ceramic substrate. Unlike conventional roughening treatment, this heat treatment does not have a negative effect on the resistor layer, so it is possible to manufacture a ceramic circuit board having a resistor layer with high precision and reliability.
しかも、導体金属ペーストの焼成によって導体回路を製
造する方法等に比べ、微♀■回路が形成でき、低抵抗の
導体金属を用いることができるので配線抵抗が低くなり
、抵抗体層として高性能なものを使用できるので、より
高精度で高信頼性ををする抵抗体層を備えたセラミック
回路板を提供することができる。Moreover, compared to methods such as manufacturing conductor circuits by firing conductor metal paste, it is possible to form microcircuits and use low-resistance conductor metals, resulting in lower wiring resistance and higher performance as a resistor layer. Therefore, it is possible to provide a ceramic circuit board having a resistor layer with higher precision and reliability.
請求項２記載の発明によれば、請求項１記載の上記効果
に加え、加熱処理を２００〜８００°Ｃで行うことによ
って、前記密着力が特に向上するとともに、抵抗体層の
性能に悪影グを与える可能性がより少なくなる。According to the invention set forth in claim 2, in addition to the above-mentioned effects set forth in claim 1, by performing the heat treatment at 200 to 800°C, the adhesion strength is particularly improved, and the performance of the resistor layer is not adversely affected. less likely to cause problems.
請求項３記載の発明によれば、請求項１記載の上記効果
に加え、回路パターンを形成する導体金属として、銅ま
たはニッケルのような卑金属を用いることによって、材
料コストを削減できるとともに配線抵抗を低くでき、ま
た、金を用いることによって、マイグレーションの心配
がなくなるとともに、はんだ付は性等が良好になる。According to the invention set forth in claim 3, in addition to the above-mentioned effects set forth in claim 1, by using a base metal such as copper or nickel as the conductor metal forming the circuit pattern, it is possible to reduce material cost and reduce wiring resistance. Moreover, by using gold, there is no need to worry about migration, and the soldering properties are improved.
第１図はこの発明の実施例を示す工程流れ図、第２図は
製造された抵抗体付セラミック回路板の断面図である。
１・・・セラミック基板 ２・・・導体金属層 ３・・
・抵抗体層 ４・・・保護層
代理人 弁理士 松 本 武 彦
第１図
第２図
用り積りＶネ市正１茎Ｆ（口慣９
１．事件の表示
昭和６３年特霞甥１５９８２２号
２、発明の名称
抵抗体付セラミック回路板の製造方法
３、補正をする者
事件との関係 特許出願人
住 所 大阪府門真市大字門真１０４８番地
名 称（５８３）松下電工株式会社
代表者 （１１ｍ役 三 好 俊 夫４、代理人
な し
６、補正の対象
＋Ａ＋紙のとおり
６、補正の対象
明細書
７、補正の内容
■ 明細書第２３頁第１８行〜第２０行に「向上すると
ともに・・・・・・少なくなる。」とあるを、「向上す
る。」と訂正する。FIG. 1 is a process flow chart showing an embodiment of the present invention, and FIG. 2 is a sectional view of a manufactured ceramic circuit board with a resistor. 1...Ceramic substrate 2...Conductor metal layer 3...
・Resistance layer 4... Protective layer Agent Takehiko Matsumoto Figure 1 Figure 2 Stack V Ne Ichimasa 1 Stalk F (Common Practice 9 1. Incident Display 1985 Toku Kasumi Nephew 159822 No. 2, Name of the invention Method for manufacturing a ceramic circuit board with resistor 3, Relationship with the amended case Patent applicant address 1048 Kadoma, Kadoma City, Osaka Name (583) Representative of Matsushita Electric Works Co., Ltd. ( 11m role: Toshio Miyoshi 4, no agent 6, subject of amendment + A + as per paper 6, specification subject to amendment 7, contents of amendment Correct the sentence ``with the increase of...decreases.'' to ``improve.''
Claims (1)
れたセラミック回路板を製造する方法であって、以下の
工程（１）〜（３）を含むことを特徴とする抵抗体付セ
ラミック回路板の製造方法。 （１）セラミック基板に抵抗体層を形成し、抵抗体層の
上に保護層を形成する工程。 （２）セラミック基板表面および抵抗体層の露出部分に
対して、所定の回路パターンに対応する導体金属層を形
成する工程。 （３）導体回路が形成されたセラミック基板を加熱処理
する工程。 ２ 加熱処理工程における加熱処理温度が、２００〜８
００℃である請求項１記載の抵抗体付セラミック回路板
の製造方法。 ３ 導体回路を構成する金属が、銅，ニッケル，金のう
ちの何れかである請求項１記載の抵抗体付セラミック回
路板の製造方法。[Scope of Claims] 1. A method for manufacturing a ceramic circuit board in which a resistor is formed together with a conductor circuit on a ceramic substrate, which method includes the following steps (1) to (3). Method of manufacturing ceramic circuit boards. (1) Step of forming a resistor layer on a ceramic substrate and forming a protective layer on the resistor layer. (2) A step of forming a conductive metal layer corresponding to a predetermined circuit pattern on the surface of the ceramic substrate and the exposed portion of the resistor layer. (3) A step of heat treating the ceramic substrate on which the conductor circuit is formed. 2 The heat treatment temperature in the heat treatment step is 200 to 8
2. The method for manufacturing a ceramic circuit board with a resistor according to claim 1, wherein the temperature is 00°C. 3. The method of manufacturing a ceramic circuit board with a resistor according to claim 1, wherein the metal constituting the conductor circuit is one of copper, nickel, and gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63159822A JPH0632358B2 (en) | 1988-06-27 | 1988-06-27 | Method for manufacturing ceramic circuit board with resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63159822A JPH0632358B2 (en) | 1988-06-27 | 1988-06-27 | Method for manufacturing ceramic circuit board with resistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH029190A true JPH029190A (en) | 1990-01-12 |
| JPH0632358B2 JPH0632358B2 (en) | 1994-04-27 |
Family
ID=15702010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63159822A Expired - Lifetime JPH0632358B2 (en) | 1988-06-27 | 1988-06-27 | Method for manufacturing ceramic circuit board with resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0632358B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010225627A (en) * | 2009-03-19 | 2010-10-07 | Mitsuboshi Belting Ltd | Method of manufacturing resistor film, resistor film, and resistor |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101907685B1 (en) * | 2016-12-07 | 2018-10-12 | 현대오트론 주식회사 | Slippage prevention system and method for nh3 |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54113867A (en) * | 1978-02-27 | 1979-09-05 | Hitachi Ltd | Method of producing resistanceeequipped printed circuit board |
| JPS5595396A (en) * | 1979-01-16 | 1980-07-19 | Oki Electric Ind Co Ltd | Method of fabricating ceramic multilayer circuit board |
| JPS55123196A (en) * | 1979-03-15 | 1980-09-22 | Fujitsu Ltd | Method of manufacturing ceramic multilayer circuit substrate |
| JPS57207395A (en) * | 1981-06-15 | 1982-12-20 | Nissha Printing | Method of producing ceramic board with metal circuit |
| JPS61194794A (en) * | 1985-02-22 | 1986-08-29 | 三菱電機株式会社 | Manufacture of hybrid integrated circuit board |
| JPS61225047A (en) * | 1985-03-29 | 1986-10-06 | 株式会社東芝 | Manufacture of ceramics circuit substrate |
-
1988
- 1988-06-27 JP JP63159822A patent/JPH0632358B2/en not_active Expired - Lifetime
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54113867A (en) * | 1978-02-27 | 1979-09-05 | Hitachi Ltd | Method of producing resistanceeequipped printed circuit board |
| JPS5595396A (en) * | 1979-01-16 | 1980-07-19 | Oki Electric Ind Co Ltd | Method of fabricating ceramic multilayer circuit board |
| JPS55123196A (en) * | 1979-03-15 | 1980-09-22 | Fujitsu Ltd | Method of manufacturing ceramic multilayer circuit substrate |
| JPS57207395A (en) * | 1981-06-15 | 1982-12-20 | Nissha Printing | Method of producing ceramic board with metal circuit |
| JPS61194794A (en) * | 1985-02-22 | 1986-08-29 | 三菱電機株式会社 | Manufacture of hybrid integrated circuit board |
| JPS61225047A (en) * | 1985-03-29 | 1986-10-06 | 株式会社東芝 | Manufacture of ceramics circuit substrate |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010225627A (en) * | 2009-03-19 | 2010-10-07 | Mitsuboshi Belting Ltd | Method of manufacturing resistor film, resistor film, and resistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0632358B2 (en) | 1994-04-27 |
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