JPH0287700A - High frequency circuit board - Google Patents
High frequency circuit boardInfo
- Publication number
- JPH0287700A JPH0287700A JP24195088A JP24195088A JPH0287700A JP H0287700 A JPH0287700 A JP H0287700A JP 24195088 A JP24195088 A JP 24195088A JP 24195088 A JP24195088 A JP 24195088A JP H0287700 A JPH0287700 A JP H0287700A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- land
- recess
- circuit board
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 abstract description 16
- 239000010410 layer Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 210000005069 ears Anatomy 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
通信機器における高周波回路基板に関し、半導体素子と
信号用配線パターンとの接続部での信号の漏話を防止す
ることを目的とし、半導体素子を搭載する多層回路基板
であって、該多層回路基板の表面全面にアース用配線パ
ターンを設け、中間に信号用配線パターンを設け、かつ
半導体素子を沈めるくぼみを穿設し、該くぼみの中央に
半導体素子の電極を密着接続するアース用ランドを配し
、その両側に入、出力信号用ランドとを配設するように
構成する。[Detailed Description of the Invention] [Summary] A multilayer circuit board on which a semiconductor element is mounted, for the purpose of preventing signal crosstalk at a connection between a semiconductor element and a signal wiring pattern, regarding a high frequency circuit board in communication equipment. A ground wiring pattern is provided on the entire surface of the multilayer circuit board, a signal wiring pattern is provided in the middle, and a recess into which the semiconductor element is sunk is formed, and the electrode of the semiconductor element is tightly attached to the center of the recess. A grounding land to be connected is arranged, and output signal lands are arranged on both sides of the grounding land.
本発明は高周波回路基板に関する。 The present invention relates to a high frequency circuit board.
通信機器に用いる高周波回路基板（以下、基板と略称す
る）においては、導体線路の構成にマイクロストリップ
線路を用いてインピーダンスの整合をとるのが一般的で
あるが、数ＧＨｚ〜数１０ＧＩＩｚの超高周波帯になる
と、このマイクロストリップ線路の構成ではアースによ
る遮蔽が不十分で信号の漏話を引き起こす場合がある。In high-frequency circuit boards (hereinafter referred to as "boards") used in communication equipment, it is common to use microstrip lines in the conductor line structure to match impedance. In the case of a microstrip line, this microstrip line configuration may not provide sufficient ground shielding and may cause signal crosstalk.
そのため、最近ではトリプレートストリップ線路が用い
られているが、半導体素子を基板に搭載する場合、なお
半導体素子と信号線路との接続部分での漏話が問題とな
っており、その漏話を防止することが要望されている。For this reason, triplate strip lines have recently been used, but when mounting semiconductor devices on a substrate, crosstalk at the connection between the semiconductor device and the signal line is still a problem, and it is necessary to prevent this crosstalk. is requested.
（従来の技術〕
従来は第３図の側断面図に小ずように、多層基板１１は
複数枚（図は２枚を示す）のガラスセラミックなどのグ
リーンシートを熱圧着し焼成・積層１、てなり、−ト、
下金表面をアース用配線パターン（表面層） ］、１ａ
−１で覆い、中間層として信号用配線パターン＋ｘｂ−
＋ を配して、いわゆるトリプレートストリップ
体素子１２を挿入する貫通花月Ｃを穿設し、その貫ｉｆ
ｆｌ孔１ １− ｃ．の側壁を内方に出（、７て信号用
配線パターンｉ１ｂ−１ を露出し半導体素子１２の電
極１２ａ とボンディングワイヤ１３で接続できるよう
にしている。(Prior Art) Conventionally, as shown in the cross-sectional side view of FIG. 3, the multilayer substrate 11 is made by thermally pressing a plurality of green sheets (the figure shows two sheets) such as glass ceramics, firing and laminating them. That's it, -to,
Wiring pattern for grounding the lower metal surface (surface layer) ], 1a
-1 and signal wiring pattern +xb- as an intermediate layer.
A through-hole C is bored through which a so-called tri-plate strip element 12 is inserted, and the through-hole if
fl hole 1 1- c. The side walls of the semiconductor element 12 are exposed inward (, 7) to expose the signal wiring pattern i1b-1 so that it can be connected to the electrode 12a of the semiconductor element 12 with the bonding wire 13.
この多層基板１１は、他の絶縁性基体１４上に固着され
、半導体素子１２は貫通孔１１（、内に挿入して絶縁性
基体１４」二に置きダイン（伏・ディユ２・グにより圧
着さね７ている。ぞｔ７で、半導体素子１２の電極１２
ａと信号用配線ベクへーンＩ１ｂ−］ とは、１５ン
デイングワイヤ１３により接続されている。This multilayer substrate 11 is fixed onto another insulating substrate 14, and the semiconductor element 12 is inserted into the through hole 11 and placed on the insulating substrate 14, and then crimped with a die. At t7, the electrode 12 of the semiconductor element 12
a and the signal wiring line I1b-] are connected by a 15-wire wire 13.
しかしながら、このような上記構成の基板によれば、、
半導体素ｆ−をトリブレートスト・リップ線路を有した
基板内に沈めても信号用配線パターンを露出させてポン
プイングリ・イヤにより接続すれば、高周波帯になる程
ホンディングワイヤ′および信号用配線バタ・−ンの僅
かな露出によっても１３号の漏話を引き起こｔ７、特性
に悪影響を及ぼすといった問題があった。However, according to the substrate with the above configuration,
Even if the semiconductor element f- is submerged in a substrate with a tributate strip line, if the signal wiring pattern is exposed and connected using pumping ears, the higher the frequency band, the more the honda wire and signal wiring will be connected. There was a problem in that even a slight exposure of the baton caused crosstalk in No. 13 and had an adverse effect on the t7 characteristics.
上記問題点に鑑み、本発明は半導体素子と信号用配線ベ
タ〜ンとの接続部での信号の漏話を防止するごとのでき
る高周波基板を提供することをＬ１的とする。In view of the above problems, an object of the present invention is to provide a high-frequency board that can prevent signal crosstalk at the connection between a semiconductor element and a signal wiring pattern.
上記目的を達成するために、本発明の基板においては、
基板の表面全面にアース用配線パターンを設け、中間に
信号用配線パターンを設け、かつ半導体素子を沈めるく
ぼみを穿設し、該くぼみの中央に半導体素子の電極を密
着接続するアース用ランドを配し、その両側に入、出力
信号用ランドとを配設するように構成する。In order to achieve the above object, in the substrate of the present invention,
A grounding wiring pattern is provided on the entire surface of the board, a signal wiring pattern is provided in the middle, a recess is made in which the semiconductor element is sunk, and a grounding land is placed in the center of the recess to closely connect the electrode of the semiconductor element. and an output signal land is arranged on both sides thereof.
基板に＜ １．ｆ７ｊ．と、その底面の）′− ス用ラ
ンドとべ、出力信号用ラン′ドとを段目、くぼみに沈め
た半導体素子の電極をそれぞれの・７・ンドに密着接続
することにより、接続長さを極小化して信号の漏話を少
な（するとともに、インピーダンスの整合を不必要とす
る。また、アース用ランドを入力信号用ラン［”と出力
信号用ランドとの間に配置することにより、入力線路側
から出力線路側への信号の僅かな漏話をア・−スに落と
し出力線路側に回り込まないようにすることができる。<1. f7j. The connection length can be reduced by closely connecting the electrodes of the semiconductor element sunk in the recesses to each of the 7- and 7-land. This minimizes signal crosstalk (and eliminates the need for impedance matching. Also, by placing the grounding land between the input signal run and the output signal land, the input line side It is possible to reduce the slight crosstalk of the signal from to the output line side to the ground and prevent it from going around to the output line side.
以ド図面Ｑご示した実施例に基づいて本発明の要旨を詳
細に説明する。The gist of the present invention will now be explained in detail based on the embodiment shown in Drawing Q.
第１図の分解斜視図および第２図のその積層後の側断面
図に示すよ・うに、多層基板１は上下全表面にアース用
配線パターン（表面層パターン） １ａ−１，１ａ−２
を設け、各中間層に信号用配線パターン（中間層パター
ン） ｉｂ−ｉ，ｉｂ−２を設けてトリブレートストリ
ップ線路を形成するとともに、、−力のアース用配線バ
ター・ン１ａ−２から半導体素子（ベア千ソゾ）２を沈
め得るくぼみ１ｃを穿設し、このくぼみｌ（中央に半導
体素子２の電極２ａと対応するアース用９７日ａ−２ａ
とその両側に入、出力信号用ランド１ｂ−２ａ， Ｉｂ
−２ｂとを配設する。As shown in the exploded perspective view in FIG. 1 and the side sectional view after lamination in FIG.
A signal wiring pattern (intermediate layer pattern) ib-i, ib-2 is provided in each intermediate layer to form a tribrate strip line, and a semiconductor is connected from the grounding wiring pattern 1a-2 to the tributary strip line. A recess 1c into which the element 2 can be sunk is made, and a grounding hole 1c corresponding to the electrode 2a of the semiconductor element 2 is placed in the center of the recess 1c.
and on both sides of the output signal land 1b-2a, Ib.
-2b.
この多層基板１の製作方法について述べる。A method for manufacturing this multilayer substrate 1 will be described.
第１図の分解斜視図に示すように、多層基板１は複数枚
（図は３枚を示す）の各グリーンシート１−Ｌ Ｌ．２
． １−３に各層の配線パターン１ａ， Ｉｈ間を接続
するピアホール１ｄや図示しない位置決めビン孔および
くぼみ１ｃを形成する角孔１ｃ′ などをパンチング加
工により穿設する。As shown in the exploded perspective view of FIG. 1, the multilayer substrate 1 includes a plurality of (the figure shows three) green sheets 1-L L. 2
．． Pier holes 1d for connecting the wiring patterns 1a and Ih of each layer, square holes 1c' for forming positioning holes (not shown) and recesses 1c, etc. are formed in 1-3 by punching.
上下表面基板となるグリーンシート１−１．１，３には
片面全面にアース用配線パターン１ａ−Ｌ１ａ−２を、
中間基板となるグリーンシー１−１〜２には所定の信号
用配線パターン１ｂ−１を、くほみ底面となるグリーン
シート１−３の内面側には搭載される半導体素子２の電
極２ａと対応するアース用ランドＩａ−２ａと、信号用
配線バター・ン１ｈ７２、即ち入、出力信号用配線パタ
ーン１ｂ−２ａ、 １ｂ−２ｂと、この入、出力信号用
配線パターン１ｂ−２ａ、 １ｂ−２ｂを１点鎖線で示
す角孔と重なる範囲内に延長接続した入、出力信号用ラ
ンド１ｂ−２ａ、 １ｂ−２ｂとをそれぞれ形成する導
体ペースト （例えば、１間またはｔ艮−バラノユウム
）をスクＩＪ−ン印刷法によりパターン印判する。The green sheets 1-1.1 and 3, which serve as the upper and lower surface substrates, have a grounding wiring pattern 1a-L1a-2 on the entire surface of one side.
Predetermined signal wiring patterns 1b-1 are placed on the green sheets 1-1 and 1-2, which serve as intermediate substrates, and electrodes 2a of the semiconductor elements 2 to be mounted are placed on the inner surface of the green sheets 1-3, which serve as the bottom surface of the groove. Corresponding earth land Ia-2a, signal wiring pattern 1h72, that is, input and output signal wiring patterns 1b-2a, 1b-2b, and input and output signal wiring patterns 1b-2a, 1b-2b. Screw the conductive paste (for example, 1 or t-baranoyuum) to form the input and output signal lands 1b-2a and 1b-2b, which are extended and connected within the range overlapping with the square hole shown by the dashed-dotted line. - Print a pattern stamp using the printing method.
そして、更にグリーンシー目−３にはアース用ランド１
ａ−２ａと表面のアース用配線パターン１ａ−２とを接
続するピアホール１ｄ−１を開け、グリーンシー 、）
１−２には回路に応じてさらに他の信号用配線パター
ンＴｏ−１と接続するピアホールＩｄ〜２．１ｄ−３，
Ｉａ４を開ける。各ピアホール１ｄには導体ペーストを
充填するが、積層厚さが厚くなる場合は、積層前の各グ
リーンシート単体時に充填し、薄い場合は位置合わせ積
層後に充填してもよい。And furthermore, the grounding land 1 is on green sea number -3.
Open a pier hole 1d-1 to connect a-2a and the ground wiring pattern 1a-2 on the surface, and connect the green sea.)
1-2 has peer holes Id to 2.1d-3, which are connected to other signal wiring patterns To-1 depending on the circuit.
Open Ia4. Each pier hole 1d is filled with conductor paste. If the laminated thickness is thick, it may be filled when each green sheet is alone before lamination, or if it is thin, it may be filled after alignment and lamination.
つぎに、各グリーンシート１−１．． ｌ−２，ｌ−３
を図示しない位置決めビンにより互いに位置合わせして
積層し、銅ペーストの場合、温度が８５０’Ｃ〜９００
℃の還元性雰囲気中（銀−パラジュウムの場合、７５０
℃〜９００”Ｃ大気中）で熱圧着・焼成し多層基板１を
得る。なお、多層基板は通常、生産効率を上げるため多
面取りのマザー基板（図示略）とし、焼結後、分割切断
して一度に複数枚を製作する。Next, each green sheet 1-1. ．． l-2, l-3
are aligned with each other using positioning bins (not shown) and stacked, and in the case of copper paste, the temperature is 850'C to 900'C.
in a reducing atmosphere at ℃ (for silver-palladium, 750
The multilayer substrate 1 is obtained by thermocompression bonding and firing at ℃~900''C in the atmosphere).In order to increase production efficiency, the multilayer substrate is usually made into a multi-sided motherboard (not shown), and after sintering, it is cut into pieces. to produce multiple sheets at once.
つぎに、この多層基板１に半導体素子２を搭載するには
、フリップチップボンディング型の半導体素子２の電極
２ａに半田（Ｐｂ／Ｓｎ） （または共晶合金（Ａｕ／
Ｓｎ） ）でバンブ２ｂを形成しておき、この半導体素
子２を角孔１ｃ＋ で形成されるくぼみＩｃ （第２図
参照）に入れて対応するアース用および入、出力信号用
ランド１ａ−２，１ｂ−２ａ、 Ｉｂ−２ｂに載せ、約
２３０℃（またはＡｌｌ／’Ｓ１１のとき約４５０’ｃ
）の温度で熱圧着し密着接続する。Next, in order to mount the semiconductor element 2 on this multilayer substrate 1, solder (Pb/Sn) (or eutectic alloy (Au/
A bump 2b is formed with Sn)), and this semiconductor element 2 is placed in a recess Ic (see Fig. 2) formed by a square hole 1c+, and the corresponding lands 1a-2, 1a-2, 1a-2 for grounding, input and output signals, etc. 1b-2a, Ib-2b, approximately 230°C (or approximately 450°C for All/'S11)
) to make a tight connection by thermocompression bonding at a temperature of
なお、ここに使用する半導体素子２の電極２ａの配置は
、第１図に示したように電極面の中央にアース用電極２
ａ−１に配し、その両側に入、出力信号用電極２ａ−２
ａ、 ２ａ−２ｂを配してアース用電極２ａ−１が両者
を遮断するごとく配置・製作されている。Note that the arrangement of the electrode 2a of the semiconductor element 2 used here is as shown in FIG.
a-1, and enters both sides of the output signal electrode 2a-2.
A, 2a-2b are arranged and a grounding electrode 2a-1 is arranged and manufactured so as to cut off both.
このように本発明による多層基板はトリプレートストリ
ップ線路に形成されてくぼみを備え、このくぼみに半導
体素子を沈めてバンプ接合により密着接続し、その接続
部分の入、出力信号用ランド間をアース用ランドで遮断
するように形成されるご上により、半導体素子の電極と
配線パターンとの間の接続長さは従来きボンディングワ
イヤに比べて殆んど零となり、この部分での信号の漏話
を少なくするとともに、インピーダンスの整合を考慮す
る必要もなくなる。As described above, the multilayer board according to the present invention has a recess formed in the tri-plate strip line, and a semiconductor element is sunk into the recess and closely connected by bump bonding, and the input and output signal lands of the connection part are grounded. Because the bonding wire is formed in such a way that it is interrupted by a land, the connection length between the electrode of the semiconductor element and the wiring pattern is almost zero compared to conventional bonding wires, and the crosstalk of signals in this part is reduced. At the same time, there is no need to consider impedance matching.
また、アース用ランドを入、出力信号用ランド間に配置
するごとにより、入力線路側から出力線路側へ微小なり
とも漏話する信号が出力線路側に回り込まないようにア
ースに落とすことができる。Further, by arranging a grounding land between the input and output signal lands, it is possible to ground the signal to prevent crosstalk from the input line side to the output line side, even if it is minute, from going around to the output line side.
〔発明の効果］
以上、詳述したように本発明によれば、トリプレートス
トリップ線路を有する多層基板にくぼみを設け、くぼみ
底面の中間層にアース用ランドの両側に入、出力信号用
ランドをそれぞれ設けることにより、半導体素子をその
電極を密着接続可能にし、その接続部分における信号の
漏話を殆んどな（すとともにインピーダンスの整合をと
る必要がなくなり、出力信号の特性を良好な高周波回路
基板を提供できるといった実用上極めて有用な効果を発
揮する。[Effects of the Invention] As detailed above, according to the present invention, a recess is provided in a multilayer board having a tri-plate strip line, and an output signal land is provided on both sides of a grounding land in the intermediate layer at the bottom of the recess. By providing these, it is possible to closely connect the electrodes of semiconductor elements, almost eliminate signal crosstalk at the connection part (and eliminate the need for impedance matching), and improve the characteristics of the output signal by using a high-frequency circuit board. It exhibits extremely useful effects in practical terms, such as being able to provide the following.
第１図は本発明による一実施例の分解斜視図、第２図は
第１図の積層後の側断面図、
第３図は従来技術による側断面図である。
図において、
■は基板く多層回路基板）、
１−１．１−２．１−３はグリーンシート、１ａ、 Ｉ
ａ−Ｌ １ａ−２はアース用配線パターン、１ａ−２ａ
はアース用ランド、
１ｂは信号用配線パターン、
１ｂ−１，１ｂ−２は入、出力信号用配線パターン、１
ｂ
２ａ、Ｉｂ
２ｂは入、
出力信号用ランド、
１ｃはくぼみ、
２は半導体素子、FIG. 1 is an exploded perspective view of an embodiment of the present invention, FIG. 2 is a side sectional view after lamination of FIG. 1, and FIG. 3 is a side sectional view of a conventional technique. In the figure, ■ is the board (multilayer circuit board), 1-1.1-2.1-3 is the green sheet, 1a, I
a-L 1a-2 is the ground wiring pattern, 1a-2a
is the ground land, 1b is the signal wiring pattern, 1b-1 and 1b-2 are the input and output signal wiring patterns, 1
b 2a, Ib 2b are lands for input and output signals, 1c is a recess, 2 is a semiconductor element,
Claims (1)
って、該多層回路基板（１）の表面全面にアース用配線
パターン（１ａ）を設け、中間に信号用配線パターン（
１ｂ）を設け、かつ前記半導体素子（２）を沈めるくぼ
み（１ｃ）を穿設し、該くぼみ（１ｃ）の中央に半導体
素子（２）の電極（２ａ）を密着接続するアース用ラン
ド（１ａ−２ａ）を配し、その両側に入、出力信号用ラ
ンド（１ｂ−２ａ，１ｂ−２ｂ）とを配設したことを特
徴とする高周波回路基板。A multilayer circuit board (1) on which a semiconductor element (2) is mounted, a ground wiring pattern (1a) is provided on the entire surface of the multilayer circuit board (1), and a signal wiring pattern (1a) is provided in the middle.
1b), and a recess (1c) into which the semiconductor element (2) is sunk, and a grounding land (1a) to closely connect the electrode (2a) of the semiconductor element (2) to the center of the recess (1c) -2a), and output signal lands (1b-2a, 1b-2b) are arranged on both sides of the high-frequency circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24195088A JPH0287700A (en) | 1988-09-26 | 1988-09-26 | High frequency circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24195088A JPH0287700A (en) | 1988-09-26 | 1988-09-26 | High frequency circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0287700A true JPH0287700A (en) | 1990-03-28 |
Family
ID=17081981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24195088A Pending JPH0287700A (en) | 1988-09-26 | 1988-09-26 | High frequency circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0287700A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006321306A (en) * | 2005-05-18 | 2006-11-30 | Universal Shipbuilding Corp | Ship with bow fin |
-
1988
- 1988-09-26 JP JP24195088A patent/JPH0287700A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006321306A (en) * | 2005-05-18 | 2006-11-30 | Universal Shipbuilding Corp | Ship with bow fin |
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