JPH0286135A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0286135A JPH0286135A JP23835688A JP23835688A JPH0286135A JP H0286135 A JPH0286135 A JP H0286135A JP 23835688 A JP23835688 A JP 23835688A JP 23835688 A JP23835688 A JP 23835688A JP H0286135 A JPH0286135 A JP H0286135A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- deposited
- layer
- polycrystalline
- silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 10
- 229910021332 silicide Inorganic materials 0.000 abstract description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 5
- 229910000765 intermetallic Inorganic materials 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 230000001131 transforming effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 21
- 238000009792 diffusion process Methods 0.000 description 4
- KGNDCEVUMONOKF-UGPLYTSKSA-N benzyl n-[(2r)-1-[(2s,4r)-2-[[(2s)-6-amino-1-(1,3-benzoxazol-2-yl)-1,1-dihydroxyhexan-2-yl]carbamoyl]-4-[(4-methylphenyl)methoxy]pyrrolidin-1-yl]-1-oxo-4-phenylbutan-2-yl]carbamate Chemical compound C1=CC(C)=CC=C1CO[C@H]1CN(C(=O)[C@@H](CCC=2C=CC=CC=2)NC(=O)OCC=2C=CC=CC=2)[C@H](C(=O)N[C@@H](CCCCN)C(O)(O)C=2OC3=CC=CC=C3N=2)C1 KGNDCEVUMONOKF-UGPLYTSKSA-N 0.000 description 3
- 229940125833 compound 23 Drugs 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005299 abrasion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、配線層が半導体基板に直接に接続されている
半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device in which a wiring layer is directly connected to a semiconductor substrate.
本発明は、上記の様な半導体装置の製造方法において、
半導体基板のうちで配線層を接続すべき領域を自己整合
的に金属間化合物化させてから配線層を形成することに
よって、信頼性の高い半導体装置を製造することができ
る様にしたものである。The present invention provides a method for manufacturing a semiconductor device as described above.
A highly reliable semiconductor device can be manufactured by forming an intermetallic compound in a self-aligned manner in the region of the semiconductor substrate where the wiring layer is to be connected, and then forming the wiring layer. .
配線層を半導体基板に直接に接続する手法、例えば、Ｍ
Ｏ３−３ＲＡＭにおいて多結晶Ｓｉから成るゲート電極
をソース・ドレイン拡散層に直接に接続する埋め込みコ
ンタクトは、セルサイズの縮小等に有効な手法である（
例えば、特開昭６２−３７９６７号公報）。A method of directly connecting a wiring layer to a semiconductor substrate, for example, M
In O3-3RAM, a buried contact that directly connects the gate electrode made of polycrystalline Si to the source/drain diffusion layer is an effective method for reducing the cell size (
For example, Japanese Patent Application Laid-Open No. 62-37967).
第３図は、この様な埋め込みコンタクトを有するＭＯＳ
−Ｓ ＲＡＭの製造方法の一従来例を示している。こ
の−従来例では、まず、第３Ａ図に示す様に、Ｓｉ基板
１１の素子分離領域にＬＯＧＯ５酸化膜１２を形成し、
更にゲート酸化膜１３を形成する。Figure 3 shows a MOS with such a buried contact.
-S A conventional example of a RAM manufacturing method is shown. In this conventional example, first, as shown in FIG. 3A, a LOGO5 oxide film 12 is formed in the element isolation region of the Si substrate 11,
Furthermore, a gate oxide film 13 is formed.
次に、第３Ｂ図に示す様に、レジスト（図示せず）をマ
スクにして埋め込みコンタクト部のゲート酸化膜１３を
フッ酸で除去し、更に、第３Ｃ図に示す様に、ゲート電
極を形成するための多結晶５ｉＦ１４をＣＶＤによって
堆積させる。Next, as shown in FIG. 3B, using a resist (not shown) as a mask, the gate oxide film 13 in the buried contact area is removed with hydrofluoric acid, and then, as shown in FIG. 3C, a gate electrode is formed. Polycrystalline 5iF14 is deposited by CVD.
次に、第３Ｄ図に示す様に、多結晶Ｓｉ層１４をエツチ
ングによってパターニングして、埋め込みコンタクト部
に接続されているゲート電極１５を形成する。なお、Ｓ
ｉ基板ＩＩが多結晶Ｓｉ層１４に対してエツチング選択
性を持たないので、多結晶Ｓｉ層１４のパターニング時
にＳｉ基板１１もエツチングされて、Ｓｉｌ板１１に凹
部１６が形成されてしまう。Next, as shown in FIG. 3D, the polycrystalline Si layer 14 is patterned by etching to form a gate electrode 15 connected to the buried contact portion. In addition, S
Since the i-substrate II has no etching selectivity with respect to the polycrystalline Si layer 14, the Si substrate 11 is also etched during patterning of the polycrystalline Si layer 14, and a recess 16 is formed in the Sil plate 11.
その後、第３Ｅ図に示す様に、不純物のイオン１７をＳ
ｉ基板１１中へ注入して、ソース・ドレイン拡散層１８
を形成する。Then, as shown in FIG. 3E, the impurity ions 17 are
The source/drain diffusion layer 18 is implanted into the i-substrate 11.
form.
ところが以上の様な一従来例では、Ｓｉ基板１１に凹部
１６が形成されてしまうので、ソース・ドレイン拡散層
１８のうちで凹部１６に対応する部分が実効的に深くな
り、微細化されたデバイスではこの様な部分がパンチス
ルー等の不良原因になり易い。However, in one conventional example as described above, since the recess 16 is formed in the Si substrate 11, the portion of the source/drain diffusion layer 18 corresponding to the recess 16 becomes effectively deeper, resulting in a miniaturized device. Such parts are likely to cause defects such as punch-through.
また、凹部１６に対応してできる激しい段差（図示せず
）が平坦化され切れず、Ａｌ配′！ＦｆＡ（図示せず）
の段切れの原因になる。In addition, the severe step (not shown) formed corresponding to the recess 16 cannot be completely flattened, and the Al arrangement ′! FfA (not shown)
This may cause a break in the steps.
従って、上述の様な一従来例では、必ずしも信頼性の高
い半導体装置を製造することができない。Therefore, in the conventional example as described above, it is not necessarily possible to manufacture a highly reliable semiconductor device.
本発明による半導体装置の製造方法は、配線層１５を接
続すべき領域を半導体基板１１の表面に露出させる様に
前記半導体基板１１上に絶縁膜１２．１３を選択的に形
成する工程と、露出した前記領域を自己整合的に金属間
化合物２３化させる工程と、金属間化合物２３化した前
記領域に接続させる様に前記配線層１５を形成する工程
とを夫夫具備している。The method of manufacturing a semiconductor device according to the present invention includes the steps of selectively forming an insulating film 12.13 on the semiconductor substrate 11 so as to expose a region to which the wiring layer 15 is to be connected on the surface of the semiconductor substrate 11; The method includes a step of converting the region formed into an intermetallic compound 23 in a self-aligned manner, and a step of forming the wiring layer 15 so as to be connected to the region formed into the intermetallic compound 23.
本発明による半導体装置の製造方法では、半導体基板１
１のうちで配線層１５を接続すべき領域を自己整合的に
金属間化合物２３化させてから配線層１５を形成してい
るので、この配線層１５を半導体で形成する場合でも、
配線層１５を接続すべき領域と配線Ｎ１５との材質が相
違している。In the method for manufacturing a semiconductor device according to the present invention, a semiconductor substrate 1
Since the wiring layer 15 is formed after forming the intermetallic compound 23 in the region to which the wiring layer 15 is to be connected in a self-aligned manner, even when the wiring layer 15 is formed of a semiconductor,
The region to which the wiring layer 15 is to be connected and the wiring N15 are made of different materials.
従って、配線層１５を接続すべき領域に対して配線Ｊｉ
ｉ１５の材料１４を選択的に処理することができ、半導
体基板１１に損傷を与えることなく配線］’ｉ１５を形
成することができる。Therefore, the wiring Ji for the area to which the wiring layer 15 is to be connected
The material 14 of i15 can be selectively processed, and the wiring]'i15 can be formed without damaging the semiconductor substrate 11.
以下、ＭＯＳ−３ＲＡＭの製造に適用した本発明の第１
及び第２実施例を、第１図及び第２図を参照しながら説
明する。Hereinafter, the first embodiment of the present invention applied to the manufacture of MOS-3RAM will be described.
A second embodiment will be described with reference to FIGS. 1 and 2.
第１図が、第１実施例を示している。この第１実施例で
は、ＬＯＧＯＳ酸化膜１２及びゲート酸化膜１３の形成
までは上述の一従来例と同様に行い、更に、第１Ａ図に
示す様に、これらの酸化膜１２．１３上にＳｉＮ膜２１
を堆積させる。FIG. 1 shows a first embodiment. In this first embodiment, the steps up to the formation of the LOGOS oxide film 12 and the gate oxide film 13 are performed in the same manner as in the above-mentioned conventional example, and furthermore, as shown in FIG. 1A, SiN is deposited on these oxide films 12 and 13. Membrane 21
deposit.
次に、第１Ｂ図に示す様に、レジスト（図示せず）をマ
スクにしてＳｉＮ膜２１及びゲート酸化膜１３をエツチ
ングして、Ｓｉ基板１１のうちの埋め込みコンタクト部
を露出させる。Next, as shown in FIG. 1B, the SiN film 21 and gate oxide film 13 are etched using a resist (not shown) as a mask to expose the buried contact portion of the Si substrate 11.
次に、第１Ｃ図に示す様に、Ｓｉ基板１１上の全面にＴ
ｉ２２を堆積させ、更に適度の熱処理を行う。Next, as shown in FIG. 1C, T is applied to the entire surface of the Si substrate 11.
i22 is deposited and further moderate heat treatment is performed.
すると、Ｓｉ基板１１の露出部つまり埋め込みコンタク
ト部が自己整合的にシリサイド２３となる。Then, the exposed portion of the Si substrate 11, that is, the buried contact portion becomes silicide 23 in a self-aligned manner.
つまり、埋め込みコンタクト部がサリサイド化する。In other words, the buried contact portion becomes salicided.
次に、第１Ｄ図に示す様に未反応のＴｉ２２及びＳｉＮ
膜２１を除去し、更に、第１Ｅ図に示す様に多結晶Ｓｉ
層１４をＣＶＤによって堆積させる。Next, as shown in Figure 1D, unreacted Ti22 and SiN
The film 21 is removed, and polycrystalline Si is further removed as shown in FIG. 1E.
Layer 14 is deposited by CVD.
その後、第１Ｆ図に示す様に、多結晶Ｓｉ層１４をエツ
チングによってパターニングして、埋め込みコンタクト
部つまりシリサイド２３に接続されているゲート電極１
５を形成する。これ以降のソ−ス・ドレイン拡散層１８
の形成等は、上述の一従来例と同様に行う。Thereafter, as shown in FIG. 1F, the polycrystalline Si layer 14 is patterned by etching to form a gate electrode 1 connected to the buried contact portion, that is, the silicide 23.
form 5. Source/drain diffusion layer 18 after this
The formation etc. are performed in the same manner as in the above-mentioned conventional example.
この様な第１実施例では、多結晶５ｉｉＪ１４のエツチ
ング時に、埋め込みコンタクト部がシリサイド２３化さ
れておりＳｉ基板１１が露出していない。In such a first embodiment, when the polycrystal 5iiJ14 is etched, the buried contact portion is made into silicide 23, so that the Si substrate 11 is not exposed.
従って、適当なエツチング条件を選べば、多結晶Ｓｉ層
１４のエツチング時にＳｉ基板１１がエツチングされな
い。このため、上述の一従来例の様に凹部１６は形成さ
れず、この凹部１６に起因する既述の様な信頼性の低下
がない。Therefore, if appropriate etching conditions are selected, the Si substrate 11 will not be etched when the polycrystalline Si layer 14 is etched. Therefore, unlike the above-mentioned conventional example, the recess 16 is not formed, and there is no reduction in reliability as described above due to the recess 16.
しかも、Ｔｉ２２等から成るシリサイド２３を形成する
と、Ｓｉ基板１１の表面における自然酸化膜（図示せず
）が破壊され、より安定なコンタクト砥抗値を得ること
ができる。Moreover, when the silicide 23 made of Ti22 or the like is formed, the natural oxide film (not shown) on the surface of the Si substrate 11 is destroyed, and a more stable contact abrasion value can be obtained.
第２図は、第２実施例を示している。この第２実施例は
、ＬＯＧＯＳ酸化膜１２及びゲート酸化膜１３の形成後
に多結晶ｓｉｌ膜２４を全面に形成し、この多結晶Ｓｉ
薄膜２４上にＳｉＮ膜２１を形成することを除いて、上
述の第１実施例と実質的に同様の工程を有している。FIG. 2 shows a second embodiment. In this second embodiment, after forming the LOGOS oxide film 12 and the gate oxide film 13, a polycrystalline sil film 24 is formed on the entire surface, and this polycrystalline silicon film 24 is formed on the entire surface.
This embodiment has substantially the same steps as the first embodiment described above, except for forming the SiN film 21 on the thin film 24.
この様な第２実施例では、多結晶Ｓｉ３膜２４が存在し
ているために、ＳｉＮ膜２１からの応力や薬品処理等か
らゲート酸化膜１３が保護され、より信頼性の高いＭＯ
３−３ＲＡＭを製造することができる。In the second embodiment, since the polycrystalline Si3 film 24 exists, the gate oxide film 13 is protected from stress from the SiN film 21, chemical treatment, etc., and a more reliable MO
3-3 RAM can be manufactured.
なお、以上の第１及び第２実施例の何れにおいてもシリ
サイド２３を形成するための金属としてＴｉ２２を用い
たが、Ｔｉ２２以外にＭＯ，、Ｗ 、Ｃｏ等を用いるこ
ともできる。Although Ti22 is used as the metal for forming the silicide 23 in both the first and second embodiments, MO, W2, Co, etc. can also be used in addition to Ti22.
本発明による半導体装置の製造方法では、半導体基板に
損傷を与えることなく配線層を形成することができるの
で、信頼性の高い半導体装置を製造することができる。In the method for manufacturing a semiconductor device according to the present invention, a wiring layer can be formed without damaging the semiconductor substrate, so a highly reliable semiconductor device can be manufactured.
第１図〜第３図は本発明の夫々第１実施例、第２実施例
及び−従来例を順次に示す側断面図である。
なお図面に用いた符号において、
１１−・−・−−一−−・−−−−−３ｉ基板１２−・
−・−−−−−ｍ−・−・−ＬＯＣＯ５酸化膜１３−−
−−−−・−−一一一一−−−−−・ゲート酸化膜１４
−・−−−−−一−−−−−〜−−−多結晶Ｓｉ層１５
−・−−ｍ−−・−・−・−・ゲート電極２３・−・−
・−・・・−・・・・シリサイドである。1 to 3 are side sectional views sequentially showing a first embodiment, a second embodiment, and a conventional example of the present invention, respectively. In addition, in the symbols used in the drawings, 11-・---1---3i substrate 12--
−・−−−−−m−・−・−LOCO5 oxide film 13−−
-----・--1111-----Gate oxide film 14
-------------Polycrystalline Si layer 15
−・−−m−−・−・−・−・Gate electrode 23・−・−
・－・・・－・・・・It is silicide.
Claims (1)
る様に前記半導体基板上に絶縁膜を選択的に形成する工
程と、 露出した前記領域を自己整合的に金属間化合物化させる
工程と、 金属間化合物化した前記領域に接続させる様に前記配線
層を形成する工程とを夫々具備する半導体装置の製造方
法。[Scope of Claims] A step of selectively forming an insulating film on the semiconductor substrate so as to expose a region to which a wiring layer is to be connected on the surface of the semiconductor substrate; A method for manufacturing a semiconductor device, comprising the steps of: forming a compound; and forming the wiring layer so as to be connected to the intermetallic region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23835688A JPH0286135A (en) | 1988-09-22 | 1988-09-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23835688A JPH0286135A (en) | 1988-09-22 | 1988-09-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0286135A true JPH0286135A (en) | 1990-03-27 |
Family
ID=17028975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23835688A Pending JPH0286135A (en) | 1988-09-22 | 1988-09-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0286135A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5587338A (en) * | 1995-04-27 | 1996-12-24 | Vanguard International Semiconductor Corporation | Polysilicon contact stud process |
| US6718604B1 (en) | 1999-06-22 | 2004-04-13 | Murata Manufacturing Co., Ltd. | Mounting method for electronic device elements |
-
1988
- 1988-09-22 JP JP23835688A patent/JPH0286135A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5587338A (en) * | 1995-04-27 | 1996-12-24 | Vanguard International Semiconductor Corporation | Polysilicon contact stud process |
| US6718604B1 (en) | 1999-06-22 | 2004-04-13 | Murata Manufacturing Co., Ltd. | Mounting method for electronic device elements |
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