JPH0281441A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0281441A JPH0281441A JP23291388A JP23291388A JPH0281441A JP H0281441 A JPH0281441 A JP H0281441A JP 23291388 A JP23291388 A JP 23291388A JP 23291388 A JP23291388 A JP 23291388A JP H0281441 A JPH0281441 A JP H0281441A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate
- covering layer
- covering
- photoresist layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000007772 electrode material Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 57
- 239000011247 coating layer Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 9
- 239000010409 thin film Substances 0.000 abstract description 4
- 230000005669 field effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
Ｃａ業上の利用分野〕
この発明は、半導体装置の製造方法に係り、特に電界効
果トランジスタ等のゲート電極の形成方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of Application in Ca Industry The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a gate electrode of a field effect transistor or the like.
第３図（ａ）〜（ｄ）は従来の電界効果トランジスタ等
のゲート電極の製造方法を説明するための工程断面図で
ある。まず、第３図（ａ）に示すように、半絶縁性Ｇａ
Ａｓ基板１とｎ型ＧａＡｓからなる動作層２を有する半
導体基板上にフォトレジスト層３を形成し、ゲートパタ
ーンニングがなされる。次に第３図（ｂ）に示すように
、動作層２にリセス領域４をウェットエツチング等によ
り形成し、次いで第３図（Ｃ）に示すように、ゲート電
極材料５′を蒸着等により形成する。次にフォトレジス
ト層３とともに、このフォトレジスト層３上にあるゲー
ト電極材料５′をリフトオフ等により除去することで第
３図（ｄ）に示すようなゲート電極５が完成する。FIGS. 3(a) to 3(d) are process cross-sectional views for explaining a conventional method of manufacturing a gate electrode of a field effect transistor or the like. First, as shown in FIG. 3(a), semi-insulating Ga
A photoresist layer 3 is formed on a semiconductor substrate having an As substrate 1 and an active layer 2 made of n-type GaAs, and gate patterning is performed. Next, as shown in FIG. 3(b), a recess region 4 is formed in the active layer 2 by wet etching or the like, and then, as shown in FIG. 3(C), a gate electrode material 5' is formed by vapor deposition or the like. do. Next, together with the photoresist layer 3, the gate electrode material 5' on the photoresist layer 3 is removed by lift-off or the like, thereby completing the gate electrode 5 as shown in FIG. 3(d).
（発明が解決しようとする課題〕
高周波用電界効果トランジスタの高性能化のために、ゲ
ート長（Ｌｇ）、ゲート抵抗の低減が求められている。(Problems to be Solved by the Invention) In order to improve the performance of high frequency field effect transistors, reductions in gate length (Lg) and gate resistance are required.
上記のような従来例では、ゲート長短縮のためゲートパ
ターンを細くしてゲート電極材料５′を蒸着等により形
成しているが、ゲート電極５の断面は先細りの台形状に
なり、ゲート電極断面積の減少によりケート抵抗の増加
を招く。つまり、ゲート抵抗の低減を図ると同時に、ゲ
ート長の短縮を図ることができないという問題点があっ
た。In the conventional example described above, in order to shorten the gate length, the gate pattern is made thinner and the gate electrode material 5' is formed by vapor deposition or the like. The decrease in area leads to an increase in gate resistance. In other words, there is a problem in that it is not possible to reduce the gate resistance and at the same time shorten the gate length.
この発明は、上記のような問題点を解消するためになさ
れたもので、ゲート抵抗の低減とゲート長の短縮を図っ
た半導体装置の製造方法を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that reduces gate resistance and shortens gate length.
この発明に係る半導体装置の製造方法は、半導体基板上
に下層から順に第１の被覆層、第２の被覆層、薄膜状の
フォトレジスト層が形成され、この薄膜状のフォトレジ
スト層をゲートパターンニングし、第２の被覆層をゲー
トパターニングより広くエツチング等で開窓した後、フ
ォトレジスト層をマスクに第１の被覆層にゲートパター
ニングし、その後、フォトレジスト層の開窓部をゲート
長より広く、かつ開窓された第２の被覆層に対してオー
バーハング状となる状態に後退させた後、ゲート電極金
属を蒸着し、Ｔ形状の断面を有するゲート電極を形成す
るものである。In the method for manufacturing a semiconductor device according to the present invention, a first covering layer, a second covering layer, and a thin film-like photoresist layer are formed in order from the bottom on a semiconductor substrate, and this thin-film photoresist layer is applied to a gate pattern. After etching and opening the second covering layer wider than the gate patterning, gate patterning is performed on the first covering layer using the photoresist layer as a mask. After receding to a state where it overhangs the second covering layer which has a wide opening, a gate electrode metal is deposited to form a gate electrode having a T-shaped cross section.
この発明における半導体装置の製造方法は、薄膜状のフ
ォトレジスト層を採用できるためゲート長の短縮が図れ
るのと同時に、Ｔ形状のゲート電極が得られゲート抵抗
が低減される。The method of manufacturing a semiconductor device according to the present invention can employ a thin photoresist layer, so that the gate length can be shortened, and at the same time, a T-shaped gate electrode can be obtained to reduce gate resistance.
以下、この発明の一実施例を図面について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図（ａ）〜（ｇ）はこの発明の半導体装置の製造方
法の一実施例を示す工程断面図で、この実施例はＧａＡ
ｓ ＭＥＳ ＦＥＴの製造工程を示すものである。FIGS. 1(a) to 1(g) are process cross-sectional views showing one embodiment of the method for manufacturing a semiconductor device of the present invention, and this embodiment is a GaA
s MES FET manufacturing process.
まず、第１図（ａ）に示すように、半導体基板、すなわ
ち半絶縁性ＧａＡｓ基板１上に形成されたｎ型ＧａＡｓ
からなる動作層２の表面に第１の被覆層１０を形成し、
この第１の被覆層１０上に第１の被覆層１０よりエツチ
ングレートの大きい第２の被覆層１１を形成する。さら
に、第２の被覆層１１上に薄膜状のフォトレジスト層１
２を形成し、このフォトレジスト層１２にゲートパター
ニングがなされるが、フォトレジスト層１２が薄膜状で
あるため微細バターニングが可能である。次に第１図（
ｂ）に示すように、第２の被覆層１１をウェットエツチ
ング等で任意の長さ、例えばＬｌだけエツチング除去す
る。この後、第１図（Ｃ）に示すように、フォトレジス
ト層１２をマスクとして、第１の被覆層１０をＲＩＥ等
によりゲートパターニングする。次に動作層２にリセス
領域１３を形成し、第１図（ｄ）に示す構造を得る。First, as shown in FIG. 1(a), an n-type GaAs film is formed on a semiconductor substrate, that is, a semi-insulating GaAs substrate 1.
Forming a first coating layer 10 on the surface of the operating layer 2 consisting of,
A second covering layer 11 having an etching rate higher than that of the first covering layer 10 is formed on the first covering layer 10 . Furthermore, a thin photoresist layer 1 is formed on the second coating layer 11.
Gate patterning is performed on this photoresist layer 12. Since the photoresist layer 12 is in the form of a thin film, fine patterning is possible. Next, Figure 1 (
As shown in b), the second covering layer 11 is etched away by wet etching or the like to an arbitrary length, for example, Ll. Thereafter, as shown in FIG. 1C, the first covering layer 10 is gate patterned by RIE or the like using the photoresist layer 12 as a mask. Next, a recess region 13 is formed in the active layer 2 to obtain the structure shown in FIG. 1(d).
次に、第１図（ｅ）に示すように、フォトレジスト層１
２を、ＲＩＢＥ等により長さＬ２ （ただし、Ｌ２＜
Ｌ、）だけ後退させ、フォトレジスト層１２が第２の被
覆層１１よりオーバーハングした形状にする。この後、
ゲート電極材料１４′を蒸着し、第１の被覆層１０．第
２の被覆層１１フォトレジスト層１２およびフォトレジ
スト層１２上の不要のケート電極材料１４′をリフトオ
フ等により除去することにより第１図（ｇ）に示すよう
に、リセス領域１３にＴ形断面図形状を有するゲート電
極１４を得る。Next, as shown in FIG. 1(e), a photoresist layer 1
2 to length L2 (however, L2<
L, ) so that the photoresist layer 12 overhangs the second covering layer 11. After this,
Depositing gate electrode material 14' and depositing first covering layer 10. By removing the second coating layer 11, the photoresist layer 12, and the unnecessary gate electrode material 14' on the photoresist layer 12 by lift-off or the like, a T-shaped cross section is formed in the recess area 13, as shown in FIG. 1(g). A gate electrode 14 having a figure shape is obtained.
なお、上記実施例では、ゲート１ｏｉｉ材料１４′の蒸
着後、第１の被覆層１０およびその上に積層された各層
を全て除去しているが、第２図に示すように第１の被覆
層１０を残すようにしてもよい。In the above embodiment, after the gate 1oii material 14' is deposited, the first covering layer 10 and all the layers stacked thereon are removed, but as shown in FIG. You may leave 10.
このように上記実施例では、第１の被覆層１０にケート
バターニング後、フォトレジスト層１２の開窓部（長ざ
Ｌｇ）を広げることにより、ゲート長（Ｌｇ）を確保し
たうえ、Ｔ形断面図形状のゲート電極１４が得られるた
め、ゲート抵抗が低減でき、高性能化が達成できる。In this way, in the above embodiment, after Kate buttering the first coating layer 10, the fenestration (length Lg) of the photoresist layer 12 is widened to ensure the gate length (Lg) and to form a T-shaped structure. Since the gate electrode 14 having a cross-sectional shape is obtained, gate resistance can be reduced and high performance can be achieved.
以上説明したようにこの発明は、薄膜状のフォトレジス
ト層を採用するため、微細ゲートパターニングが可能と
なり、ゲート長が短縮できる。また、第１の被覆層にゲ
ート長に相応する開窓部を設け、第１の被覆層の開窓部
より広い開窓部を持つ第２の被覆層を第１の被覆層上に
設け、第２の被覆層上にゲート長に相応した開窓部を有
する薄膜状のフォトレジスト層の開窓部を、ゲート長よ
り広く、かつ第２の被覆層の開窓部より狭い範囲内に広
げることによりゲート電極をＴ形断面形状にすることが
できる。したがって、ゲート長を短縮できる上、ゲート
抵抗が低減でき、高周波用電界効果トランジスタの高性
能化が計れる利点が得られる。As explained above, since the present invention employs a thin photoresist layer, fine gate patterning is possible and the gate length can be shortened. Further, a fenestration corresponding to the gate length is provided in the first covering layer, and a second covering layer having a fenestration wider than the fenestration in the first covering layer is provided on the first covering layer, The fenestration of a thin photoresist layer having an fenestration corresponding to the gate length on the second covering layer is expanded within a range wider than the gate length and narrower than the fenestration of the second covering layer. This allows the gate electrode to have a T-shaped cross section. Therefore, there are advantages in that the gate length can be shortened, gate resistance can be reduced, and the performance of the high frequency field effect transistor can be improved.
第１図はこの発明の半導体装置の製造方法の一実施例を
示す工程断面図、第２図はこの発明の他の実施例による
半導体装置の断面図、第３図は従来の半導体装置の製造
方法の工程断面図である。
図において、１は半絶縁性ＧａＡｓ基板、２はｎ型Ｇａ
Ａｓからなる動作層、１０は第１の被覆層、１１は第２
の被覆層、１２は薄膜状のフォトレジスト層、１３はリ
セス領域、１４はゲート電極である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第 １ 図
その１
第１図その２
Ｊソｔス硼壜
１４ ゲ′−トｆ、楊FIG. 1 is a process cross-sectional view showing one embodiment of the method for manufacturing a semiconductor device of the present invention, FIG. 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention, and FIG. 3 is a conventional manufacturing method of a semiconductor device. It is a process cross-sectional view of a method. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n-type GaAs substrate, and 2 is an n-type GaAs substrate.
An active layer made of As, 10 a first coating layer, 11 a second
12 is a thin film-like photoresist layer, 13 is a recess region, and 14 is a gate electrode. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 1 Figure 1 Figure 2 J Sots Bottle 14 Gate F, Yang
Claims (1)
りエッチングレートの大きい第２の被覆層、この第２の
被覆層上に薄膜状のフォトレジスト層を順次積層した後
、前記フォトレジスト層にゲートパターンニングする工
程、前記第２の被覆層を前記フォトレジスト層のゲート
パターニング幅より広く除去する工程、前記第１の被覆
層を前記フォトレジスト層をマスクとしてゲートパター
ニングする工程、前記第１の被覆層をマスクとして所定
幅で所定深さを有するリセス領域を形成する工程、前記
フォトレジスト層の開窓部を初期の幅より広く、かつ前
記第２の被覆層に対しオーバーハング状に後退させる工
程、ゲート電極材料を被着させた後、前記第１の被覆層
とともに、またはこの第１の被覆層を残して前記第２の
被覆層、フォトレジスト層および不要のゲート電極材料
を除去する工程からなることを特徴とする半導体装置の
製造方法。After sequentially laminating a first coating layer, a second coating layer having a higher etching rate than the first coating layer, and a thin photoresist layer on the second coating layer on the main surface of the semiconductor substrate, a step of gate patterning the photoresist layer; a step of removing the second covering layer wider than the gate patterning width of the photoresist layer; a step of gate patterning the first covering layer using the photoresist layer as a mask; forming a recess region having a predetermined width and a predetermined depth using the first covering layer as a mask; making the fenestration of the photoresist layer wider than the initial width and overhanging the second covering layer; After depositing the gate electrode material, the second covering layer, the photoresist layer and the unnecessary gate electrode material are removed together with the first covering layer or leaving the first covering layer. 1. A method for manufacturing a semiconductor device, comprising the step of removing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23291388A JPH0281441A (en) | 1988-09-17 | 1988-09-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23291388A JPH0281441A (en) | 1988-09-17 | 1988-09-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0281441A true JPH0281441A (en) | 1990-03-22 |
Family
ID=16946800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23291388A Pending JPH0281441A (en) | 1988-09-17 | 1988-09-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0281441A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5215939A (en) * | 1991-02-08 | 1993-06-01 | Alcatel N.V. | Method of manufacturing a planar buried heterojunction laser |
| US5288654A (en) * | 1990-12-26 | 1994-02-22 | Mitsubishi Denki Kabushiki Kaisha | Method of making a mushroom-shaped gate electrode of semiconductor device |
| US5583063A (en) * | 1993-11-30 | 1996-12-10 | Nec Corporation | Method of forming T-shaped, cross-sectional pattern using two layered masks |
| JP2009527749A (en) * | 2006-02-21 | 2009-07-30 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Pressure measuring device |
-
1988
- 1988-09-17 JP JP23291388A patent/JPH0281441A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5288654A (en) * | 1990-12-26 | 1994-02-22 | Mitsubishi Denki Kabushiki Kaisha | Method of making a mushroom-shaped gate electrode of semiconductor device |
| US5215939A (en) * | 1991-02-08 | 1993-06-01 | Alcatel N.V. | Method of manufacturing a planar buried heterojunction laser |
| US5583063A (en) * | 1993-11-30 | 1996-12-10 | Nec Corporation | Method of forming T-shaped, cross-sectional pattern using two layered masks |
| JP2009527749A (en) * | 2006-02-21 | 2009-07-30 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Pressure measuring device |
| US8250909B2 (en) | 2006-02-21 | 2012-08-28 | Robert Bosch Gmbh | Pressure measuring device |
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