JPH0268522A - Active matrix substrate - Google Patents

Active matrix substrate

Info

Publication number
JPH0268522A
JPH0268522A JP63220938A JP22093888A JPH0268522A JP H0268522 A JPH0268522 A JP H0268522A JP 63220938 A JP63220938 A JP 63220938A JP 22093888 A JP22093888 A JP 22093888A JP H0268522 A JPH0268522 A JP H0268522A
Authority
JP
Japan
Prior art keywords
signal line
signal lines
video signal
metal film
active matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63220938A
Other languages
Japanese (ja)
Inventor
Hitoshi Noda
均 野田
Hiroshi Takahara
博司 高原
Mamoru Takeda
守 竹田
Ichiro Yamashita
一郎 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63220938A priority Critical patent/JPH0268522A/en
Publication of JPH0268522A publication Critical patent/JPH0268522A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136204Arrangements to prevent high voltage or static electricity failures
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136254Checking; Testing

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)

Abstract

PURPOSE:To prevent an insulating film at the intersection part of a scanning signal line and a video signal line from breaking down electrostatically by connecting scanning signal lines and video signal lines alternately by metallic films at respective signal line ends, and connecting them to the pattern of a metallic film formed outside input terminals through the insulating film. CONSTITUTION:The scanning signal lines X1-Xm and video signal lines Y1-Yn of an active matrix substrate formed by arranging switching elements 1 on a glass substrate in matrix are connected alternately to the metallic film patterns 3 formed on the glass substrate, and further connected to an outside common electrode pattern 4 through the insulating film 5. Consequently, the switching elements and the insulating film at the intersection parts of the scanning signal lines and video signal lines are prevented from breaking down owing to static electricity charged in the substrate during its manufacture and the wire breaking defect inspection of the signal lines and short-circuit defect inspection between both signal line groups can be carried out.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、液晶表示パネルに用いられるアクティブマト
リックス基板に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an active matrix substrate used in a liquid crystal display panel.

従来の技術 近年、産業機器の小型化にともない従来からの表示装置
に代わる薄型平面表示装置が要望されている。種々ある
平面表示装置の中で液晶を用いた表示装置は、消費電力
が少なく、フルカラー表示が容易である点などから注目
されている。特に、表示画素の一つ一つにスイッチング
素子を設けたアクティブマトリンクス型液晶表示パネル
は表示画質が優れているため携帯用のテレビなどに応用
されている。
2. Description of the Related Art In recent years, with the miniaturization of industrial equipment, there has been a demand for thin flat display devices to replace conventional display devices. Among various flat display devices, display devices using liquid crystals are attracting attention because they consume less power and can easily display full color. In particular, active matrix liquid crystal display panels in which each display pixel is provided with a switching element have excellent display image quality, and are therefore used in portable televisions and the like.

第6図は従来のアクティブマトリックス基板の構成を示
す等価回路図である。第6図において、51は薄膜トラ
ンジスタ、52は信号線をショート欠陥にするための金
属膜パターン、X1〜Xmは走査信号線、Y1〜Ynは
映像信号線である。
FIG. 6 is an equivalent circuit diagram showing the structure of a conventional active matrix substrate. In FIG. 6, 51 is a thin film transistor, 52 is a metal film pattern for making a signal line short-circuited, X1 to Xm are scanning signal lines, and Y1 to Yn are video signal lines.

ところが、アクティブマトリックス基板では、基板の製
造行程中に基板に帯電する静電気によってスイッチング
素子や走査信号線と映像信号線の交差部分の11!!縁
膜が破壊され、ショート状態になってしまうという問題
点があった。この静電気による絶縁膜の破壊防止対策と
して、従来では第6図に示すようにアクティブマトリッ
クス基板の全ての端子を金属膜パターン52でショート
しておき、液晶パネルへの組立後この金属膜パターン5
2を切断するという方法が用いられていた。
However, in active matrix substrates, static electricity that builds up on the substrate during the manufacturing process causes damage to the switching elements and the intersections between the scanning signal lines and the video signal lines. ! There was a problem in that the membrane was destroyed, resulting in a short circuit. As a measure to prevent breakdown of the insulating film due to static electricity, conventionally all terminals of the active matrix substrate are short-circuited with a metal film pattern 52 as shown in FIG.
A method of cutting 2 was used.

発明が解決しようとする課題 しかしながら、第4図に示したような従来の静電気によ
る絶縁膜の破壊防止方法では、全ての端子がショートさ
れているためアクティブマトリックス基板の完成後、シ
ョート部分を切断するまで信号線の断線による断線欠陥
、隣合う走査信号線どうしや映像信号線どうしのショー
ト欠陥、走査信号線と映像信号線のショートといったシ
ョート欠陥を検査することはできなかった。
Problems to be Solved by the Invention However, in the conventional method for preventing breakdown of an insulating film due to static electricity as shown in Fig. 4, all terminals are short-circuited, so it is necessary to cut off the short-circuited parts after the active matrix substrate is completed. Until now, it was not possible to inspect short-circuit defects such as disconnection defects due to signal line disconnections, short-circuit defects between adjacent scanning signal lines or video signal lines, and short-circuits between scanning signal lines and video signal lines.

本発明はかかる点に鑑みてなされたもので、静電気によ
る絶縁膜の破壊を防止し、かつ、欠陥検査が行えるアク
ティブマトリックス基板を提供することを目的としてい
る。
The present invention has been made in view of the above problems, and an object of the present invention is to provide an active matrix substrate that prevents breakdown of an insulating film due to static electricity and allows defect inspection.

課題を解決するための手段 本発明は上記した課題を解決するために、アクティブマ
トリックス基板のスイッチング素子の走査信号線および
映像信号線を各信号線群毎に信号線端で1本おきにガラ
ス基板上に形成した金属膜で接続し、走査信号線と映像
信号線の入力端子の外側に形成した金属膜のパターンと
絶縁膜または半導体膜を介して接続するように構成した
ものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a glass substrate for scanning signal lines and video signal lines of switching elements of an active matrix substrate at every other signal line end of each signal line group. The connection is made through a metal film formed above, and connected to a metal film pattern formed outside the input terminals of the scanning signal line and the video signal line via an insulating film or a semiconductor film.

作用 本発明は上記した構成により、アクティブマトリックス
基板における静電気による絶縁膜の破壊を防止すると共
に、信号線の断線欠陥検査と走査信号線群と映像信号線
群間のショート欠陥検査を行うことを可能とする。
Effect: With the above-described configuration, the present invention prevents breakdown of the insulating film due to static electricity on the active matrix substrate, and also makes it possible to inspect signal line disconnections and short circuit defects between the scanning signal line group and the video signal line group. shall be.

実施例 以下、本発明の一実施例のアクティブマトリックス基板
について図面を参照しながら説明する。
EXAMPLE Hereinafter, an active matrix substrate according to an example of the present invention will be described with reference to the drawings.

第1図は本発明の第1の実施例におけるアクティブマト
リックス基板の構成図である。第1図において1は薄膜
トランジスタ、2は走査信号線および映像信号線の入力
端子、3は走査信号線および映像信号線をショートする
ための金属膜パターン、4は信号線の入力端子の外側に
共通電極として金属膜で形成した共通電極パターン、5
は信号線をショートさせた金属膜パターン3と共通電極
パターン4のあいだに形成した絶縁膜、Xt〜Xmは走
査信号線、Y1〜Ynは映像信号線である。本実施例で
は第1図に示すように走査信号線と映像信号線は1本お
きに金属膜パターン3に接続し、絶縁膜5を介して共通
電極パターン4に接続されている。
FIG. 1 is a configuration diagram of an active matrix substrate in a first embodiment of the present invention. In Figure 1, 1 is a thin film transistor, 2 is an input terminal for the scanning signal line and video signal line, 3 is a metal film pattern for shorting the scanning signal line and video signal line, and 4 is common to the outside of the input terminal for the signal line. Common electrode pattern formed of a metal film as an electrode, 5
denotes an insulating film formed between the metal film pattern 3 and the common electrode pattern 4 in which signal lines are short-circuited, Xt to Xm are scanning signal lines, and Y1 to Yn are video signal lines. In this embodiment, as shown in FIG. 1, every other scanning signal line and video signal line is connected to a metal film pattern 3 and connected to a common electrode pattern 4 via an insulating film 5.

第2図は金属膜パターン3と共通電極金属膜パターン4
の第1図のA部における構造図であり、第3図は第2図
のa−a’部における略断面図である。第2図、第3図
で本実施例の構造を説明する。信号線の入力端子2をガ
ラス基板10上に形成するときに同時に信号線をショー
トさせる金属膜パターン3も形成しておく。次にスイッ
チング素子を形成するときに同時に金属膜パターン3上
に絶縁M5を形成する。そして、最後に共通電極パター
ン4を信号線の補強膜とする金属膜11を形成するとき
に同時に形成する。このように構成することでフォトマ
スクの枚数を増やすことなく静電気による絶縁膜破壊の
防止対策を行うことができる。また、第2図のb部で示
す信号線と金属膜パターン3の接続部分は検査終了後切
断しやすいように補強金属膜11を形成していない。
Figure 2 shows metal film pattern 3 and common electrode metal film pattern 4.
1, and FIG. 3 is a schematic sectional view taken along the line a-a' in FIG. 2. FIG. The structure of this embodiment will be explained with reference to FIGS. 2 and 3. When forming the input terminal 2 of the signal line on the glass substrate 10, a metal film pattern 3 for shorting the signal line is also formed at the same time. Next, when forming the switching element, an insulation M5 is formed on the metal film pattern 3 at the same time. Finally, the common electrode pattern 4 is formed simultaneously with the formation of the metal film 11 that serves as a reinforcing film for the signal line. With this configuration, it is possible to take measures to prevent insulation film breakdown due to static electricity without increasing the number of photomasks. In addition, the reinforcing metal film 11 is not formed at the connection portion between the signal line and the metal film pattern 3 shown in part b in FIG. 2 so that it can be easily cut after the inspection is completed.

第4図に本発明の第2の実施例をしめす。第4図は前記
第1図のA部と同じ部分の構造図であり、第5図は第4
図のc−c’部における略断面図である。第4図、第5
図で第2の実施例の構造を説明する。信号線の入力端子
2をガラス基板10上に形成するときに同時に信号線を
ショートさせる金属膜パターン3も形成しておく。次に
スイッチング素子を形成するときに同時に金属膜パター
ン3上に半導体膜6を形成する。そして、最後に共通電
極パターン4を信号線の補強膜とする金属膜11を形成
するときに同時に形成する。半導体膜6は、数■の電圧
を印加して行なう欠陥検査の時などには高い抵抗値を持
っているが、静電気によって数100〜数kVの高電圧
が信号線に加わった場合では十分低抵抗となって静電気
による電流を共通電極パターン4に流すことができる。
FIG. 4 shows a second embodiment of the present invention. Figure 4 is a structural diagram of the same part as the A section in Figure 1, and Figure 5 is a structural diagram of the same part as A section in Figure 1.
It is a schematic sectional view taken along c-c' section in the figure. Figures 4 and 5
The structure of the second embodiment will be explained with reference to the drawings. When forming the input terminal 2 of the signal line on the glass substrate 10, a metal film pattern 3 for shorting the signal line is also formed at the same time. Next, when forming a switching element, a semiconductor film 6 is formed on the metal film pattern 3 at the same time. Finally, the common electrode pattern 4 is formed simultaneously with the formation of the metal film 11 that serves as a reinforcing film for the signal line. The semiconductor film 6 has a high resistance value when performing a defect inspection by applying a voltage of several square meters, but it has a sufficiently low resistance value when a high voltage of several hundred to several kilovolts is applied to the signal line due to static electricity. It acts as a resistor and allows current to flow through the common electrode pattern 4 due to static electricity.

このように構成することでフォトマスクの枚数を増やす
ことなく静電気による絶縁膜破壊の防止対策を行うこと
ができる。また、第4図のd部で示す信号線と金属膜パ
ターン3の接続部分は検査終了後レーザ光線などで切断
しゃすいように補強金属Dullを形成していない。
With this configuration, it is possible to take measures to prevent insulation film breakdown due to static electricity without increasing the number of photomasks. Moreover, the reinforcing metal Dull is not formed at the connecting portion between the signal line and the metal film pattern 3, which is shown in section d in FIG. 4, so that it can be easily cut with a laser beam or the like after the inspection is completed.

次に第1の実施例、第2の実施例による欠陥検査方法に
ついて説明する。信号線の断線検査は、走査信号線、映
像信号線とも片側の端子は接続されていないので、金属
膜パターン3と入力端子2プローブ針を接続し、近抗値
を測定することで検査することができる。隣合う信号線
どうしのショート欠陥検査は信号線が1本おきに金属膜
パターン3に接続されているため金属膜パターン3にプ
ローブ針を接続し、抵抗値を測定することで2つのブロ
ックについてショート欠陥検査を行うことができる。ま
た、走査信号線と映像信号線間のショート欠陥検査は、
各々の金属膜パターン3は絶縁膜5または半導体膜6を
介して接続しているので電気的に絶縁されており走査信
号線側の金属膜パターンと映像信号線側の金属膜パター
ンにプローブ針を接続し、抵抗値を測定することで当該
ブロックについてショート欠陥検査を行うことができる
Next, defect inspection methods according to the first embodiment and the second embodiment will be explained. To test for disconnection of the signal line, the terminals on one side of both the scanning signal line and the video signal line are not connected, so connect the metal film pattern 3 and the input terminal 2 probe needle and measure the near resistance value. Can be done. Short-circuit defects between adjacent signal lines can be detected by connecting a probe needle to the metal film pattern 3 and measuring the resistance value, since every other signal line is connected to the metal film pattern 3. Can perform defect inspection. In addition, short defect inspection between scanning signal line and video signal line is
Each metal film pattern 3 is electrically insulated because it is connected via an insulating film 5 or a semiconductor film 6, and a probe needle is inserted between the metal film pattern on the scanning signal line side and the metal film pattern on the video signal line side. By connecting and measuring the resistance value, short defect inspection can be performed on the block.

発明の効果 以上の説明のように本発明は、アクティブマトリ・ンク
ス基板のスイッチング素子の走査信号線および映像信号
線を各信号線群毎に信号線端で1本おきにガラス基板上
に形成した金属膜で接続し、かつ、走査信号線と映像信
号線の入力端子の外側に形成した金属膜のパターンと絶
縁膜または半導体膜を介して接続することで、静電気に
よる絶縁膜破壊の保護を行うと共に、走査信号線、映像
信号線の断線欠陥検査やショート欠陥検査を行うことが
可能であるというすぐれた効果を有する。
Effects of the Invention As explained above, in the present invention, the scanning signal lines and the video signal lines of the switching elements of the active matrix substrate are formed on the glass substrate at every other signal line end of each signal line group. By connecting with a metal film and connecting via an insulating film or semiconductor film to the metal film pattern formed on the outside of the input terminals of the scanning signal line and video signal line, protection against breakdown of the insulating film due to static electricity is achieved. In addition, it has an excellent effect in that it is possible to inspect for disconnection defects and short defects in scanning signal lines and video signal lines.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例におけるアクティブマトリッ
クス基板の構成図、第2図は第1図のA部の構造図、第
3図は第2図のa−a’部における略断面図、第4回は
第2の実施例の構造図、第5図は第4図のc−c’部に
おける略断面図、第6図は従来のアクティブマトリック
ス基板の構成を示す構成図である。 1・・・・・・薄膜トランジスタ、2・・・・・・入力
端子、3・・・・・・金属膜パターン、4・・・・・・
共通電極パターン、5・・・・・・絶縁膜、6・・・・
・・半導体膜、XI−Xm・・・・・・・走査信号線、
Y1〜Yn・旧・・映像信号線。 代理人の氏名 弁理士 粟野重孝 はか1名第1図 第 図 第 第 図 図 ?、1/ 第 図 第 図
FIG. 1 is a configuration diagram of an active matrix substrate according to an embodiment of the present invention, FIG. 2 is a structural diagram of section A in FIG. 1, and FIG. 3 is a schematic sectional view taken along section a-a' in FIG. The fourth part is a structural diagram of the second embodiment, FIG. 5 is a schematic sectional view taken along line cc' in FIG. 4, and FIG. 6 is a configuration diagram showing the configuration of a conventional active matrix substrate. 1... Thin film transistor, 2... Input terminal, 3... Metal film pattern, 4...
Common electrode pattern, 5...Insulating film, 6...
...Semiconductor film, XI-Xm...Scanning signal line,
Y1~Yn/Old...Video signal line. Name of agent: Patent attorney Shigetaka Awano (1 person) , 1/ Figure Figure

Claims (6)

【特許請求の範囲】[Claims] (1)ガラス基板上にスイッチング素子をマトリックス
状に配置したアクティブマトリックス基板であって、前
記スイッチング素子の走査信号線および映像信号線を各
信号線群毎に信号線端で1本おきに前記ガラス基板上に
形成した第1の金属膜で接続し、前記走査信号線と映像
信号線の入力端子の外側に形成した第2の金属膜のパタ
ーンの一部分が絶縁膜を介して前記第1の金属膜と重な
るように構成したことを特徴とするアクティブマトリッ
クス基板。
(1) An active matrix substrate in which switching elements are arranged in a matrix on a glass substrate, wherein scanning signal lines and video signal lines of the switching elements are connected to the glass substrate at every other signal line end for each signal line group. A part of the pattern of a second metal film formed on the outside of the input terminals of the scanning signal line and the video signal line is connected to the first metal film formed on the substrate through an insulating film. An active matrix substrate characterized by being configured to overlap with a film.
(2)信号線の入力端子の外側に形成した第2の金属膜
のパターンは、前記信号線のパターン幅より十分太くし
て共通電極としたことを特徴とする請求項(1)記載の
アクティブマトリックス基板。
(2) The active according to claim 1, wherein the second metal film pattern formed outside the input terminal of the signal line is sufficiently thicker than the pattern width of the signal line to serve as a common electrode. matrix substrate.
(3)スイッチング素子が二端子素子、あるいは、薄膜
トランジスタで構成されていることを特徴とする請求項
(1)記載のアクティブマトリックス基板。
(3) The active matrix substrate according to claim (1), wherein the switching element is composed of a two-terminal element or a thin film transistor.
(4)ガラス基板上にスイッチング素子をマトリックス
状に配置したアクティブマトリックス基板であって、前
記スイッチング素子の走査信号線および映像信号線を各
信号線群毎に信号線端で1本おきに前記ガラス基板上に
形成した第1の金属膜で接続し、前記走査信号線と映像
信号線の入力端子の外側に形成した第2の金属膜のパタ
ーンの一部分が半導体膜を介して前記第1の金属膜と接
続したことを特徴とするアクティブマトリックス基板。
(4) An active matrix substrate in which switching elements are arranged in a matrix on a glass substrate, wherein scanning signal lines and video signal lines of the switching elements are connected to the glass substrate at every other signal line end for each signal line group. A part of the pattern of a second metal film formed on the outside of the input terminals of the scanning signal line and the video signal line is connected to the first metal film formed on the substrate through the semiconductor film. An active matrix substrate characterized by being connected to a membrane.
(5)信号線の入力端子の外側に形成した第2の金属膜
のパターンは、前記信号線のパターン幅より十分太くし
て共通電極としたことを特徴とする請求項(4)記載の
アクティブマトリックス基板。
(5) The active device according to claim 4, wherein the second metal film pattern formed outside the input terminal of the signal line is sufficiently thicker than the pattern width of the signal line to serve as a common electrode. matrix substrate.
(6)スイッチング素子が二端子素子、あるいは、薄膜
トランジスタで構成されていることを特徴とする請求項
(4)記載のアクティブマトリックス基板。
(6) The active matrix substrate according to claim (4), wherein the switching element is composed of a two-terminal element or a thin film transistor.
JP63220938A 1988-09-02 1988-09-02 Active matrix substrate Pending JPH0268522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63220938A JPH0268522A (en) 1988-09-02 1988-09-02 Active matrix substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63220938A JPH0268522A (en) 1988-09-02 1988-09-02 Active matrix substrate

Publications (1)

Publication Number Publication Date
JPH0268522A true JPH0268522A (en) 1990-03-08

Family

ID=16758911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63220938A Pending JPH0268522A (en) 1988-09-02 1988-09-02 Active matrix substrate

Country Status (1)

Country Link
JP (1) JPH0268522A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7619696B2 (en) 2006-09-28 2009-11-17 Epson Imaging Devices Corporation Liquid crystal display panel
CN105404065A (en) * 2015-12-04 2016-03-16 深圳市华星光电技术有限公司 Film transistor array structure
CN107817634A (en) * 2016-09-13 2018-03-20 乐金显示有限公司 Thin film transistor base plate and the display device for including it

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5991479A (en) * 1982-11-17 1984-05-26 セイコーエプソン株式会社 Active matrix substrate
JPS61213881A (en) * 1985-03-19 1986-09-22 株式会社東芝 Manufacture of electrode for switch matrix type element
JPH0259727A (en) * 1988-08-25 1990-02-28 Matsushita Electric Ind Co Ltd Active matrix substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5991479A (en) * 1982-11-17 1984-05-26 セイコーエプソン株式会社 Active matrix substrate
JPS61213881A (en) * 1985-03-19 1986-09-22 株式会社東芝 Manufacture of electrode for switch matrix type element
JPH0259727A (en) * 1988-08-25 1990-02-28 Matsushita Electric Ind Co Ltd Active matrix substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7619696B2 (en) 2006-09-28 2009-11-17 Epson Imaging Devices Corporation Liquid crystal display panel
CN105404065A (en) * 2015-12-04 2016-03-16 深圳市华星光电技术有限公司 Film transistor array structure
CN107817634A (en) * 2016-09-13 2018-03-20 乐金显示有限公司 Thin film transistor base plate and the display device for including it

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