JPH0266946A - Intrinsic gettering method - Google Patents
Intrinsic gettering methodInfo
- Publication number
- JPH0266946A JPH0266946A JP21876488A JP21876488A JPH0266946A JP H0266946 A JPH0266946 A JP H0266946A JP 21876488 A JP21876488 A JP 21876488A JP 21876488 A JP21876488 A JP 21876488A JP H0266946 A JPH0266946 A JP H0266946A
- Authority
- JP
- Japan
- Prior art keywords
- oxygen
- region
- substrate
- silicon nitride
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005247 gettering Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000001301 oxygen Substances 0.000 claims abstract description 21
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 16
- 230000000694 effects Effects 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 abstract 3
- 238000001556 precipitation Methods 0.000 description 8
- 239000000356 contaminant Substances 0.000 description 7
- 230000002950 deficient Effects 0.000 description 4
- 239000002244 precipitate Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、熱処理により半導体基板内部に酸化物を析出
させ、その結果性ずる酸素析出欠陥に汚染不純物を集め
るイントリンシック・ゲッタリング方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an intrinsic gettering method in which an oxide is precipitated inside a semiconductor substrate by heat treatment, and contaminant impurities are thereby collected in the oxygen precipitated defects.
例えば徳山・橋本編著ｒＭＯ３ＬｓＩ製造技術」（昭和
６０年１日経マグロウヒル社発行）５７〜５９ページに
記載されているように、従来のイントリンシック・ゲッ
タリング方法は高温（２１１００℃）で半導体基板表面
付近の酸素を外方拡散し、次いで低温（〜６００℃）で
酸素析出の核を形成し、最後に中温（〜１０００℃）で
その核を成長させる。この際、表面付近の無欠陥゛領域
いわゆるデヌーデッド・ゾーンは全面にわたりほぼ一様
にある深さまで形成される。この表面に素子を作成する
と通常より欠陥が極端に少ないことと、基板内部領域に
形成された析出欠陥が、表面の汚染不純物や微小欠陥を
取り込んでくれることとにより、素子特性は良好なもの
が得られる。このため、従来よりアナログ素子や電荷保
持素子に多くイントリンシック・ゲッタリング方法が適
用されている。For example, as described in "rMO3LsI Manufacturing Technology" edited by Tokuyama and Hashimoto (Published by Nikkei McGraw-Hill, Inc., 1985), the conventional intrinsic gettering method uses high temperature (21100°C) near the semiconductor substrate surface. of oxygen outdiffused, then nucleating oxygen precipitates at low temperatures (~600°C), and finally growing the nuclei at intermediate temperatures (~1000°C). At this time, a defect-free region near the surface, so-called denuded zone, is formed almost uniformly over the entire surface to a certain depth. When a device is fabricated on this surface, there are far fewer defects than usual, and the precipitated defects formed in the internal region of the substrate incorporate contaminant impurities and minute defects from the surface, resulting in good device characteristics. can get. For this reason, the intrinsic gettering method has conventionally been applied to many analog devices and charge retention devices.
従来のイントリンシック・ゲッタリング方決では、酸素
の析出核は半導体基板の厚さ方向の中央部に形成される
。従って汚染不純物や微小欠陥の取り込みは基板の厚さ
方向の中央部に存在する析出核によって行われる。もし
、この析出核の存在する領域の体積を増大させれば、そ
れだけゲッタリング効果が向上することは明らかである
。In the conventional intrinsic gettering method, oxygen precipitation nuclei are formed at the center of the semiconductor substrate in the thickness direction. Therefore, contaminating impurities and minute defects are taken in by the precipitation nuclei present in the center of the substrate in the thickness direction. It is clear that if the volume of the region where these precipitation nuclei exist is increased, the gettering effect will be improved accordingly.
本発明の課題は、汚染不純物や微小欠陥の取り込みを行
う酸素析出核存在領域を増加させてゲッタリング効果を
向上させ、しかも素子の作成に支障を及ぼさないイント
リンシック・ゲッタリング方法を提供することにある。An object of the present invention is to provide an intrinsic gettering method that improves the gettering effect by increasing the area where oxygen precipitated nuclei exist that take in contaminant impurities and minute defects, and that does not interfere with the fabrication of devices. It is in.
上記のＵＲ題の解決のために、本発明のイントリンシッ
ク・ゲッタリング方法は、素子作成領域である半導体基
板表面部の酸素を外方へ拡散させる熱処理を行う際に、
素子相互間の分割部類域を酸素を通さない物質で被覆す
るものとする。In order to solve the above-mentioned UR problem, the intrinsic gettering method of the present invention includes the following steps:
The divided areas between the elements shall be covered with a substance that does not allow oxygen to pass through.
素子の作成に利用されない素子相互間の分割部類域を酸
素を通さない物質で被覆して酸素外方拡散のための熱処
理を行えば、半導体基板の分割部類域には酸素が残存し
、その後の低温や中温の熱処理によりその領域にも酸素
析出欠陥が生じ、素子作成領域から汚染不純物や微小欠
陥を取り込む。If the divided regions between elements that are not used for device fabrication are coated with a substance that does not allow oxygen to pass through, and heat treatment is performed for oxygen outward diffusion, oxygen will remain in the divided regions of the semiconductor substrate, which will prevent subsequent Oxygen precipitation defects are also generated in that region due to heat treatment at low or medium temperatures, and contaminant impurities and minute defects are taken in from the device fabrication region.
第１図ｆａｔ〜ｆｃ）に本発明の一実施例のイントリン
シック・ゲッタリング方法の工程を順次示す、先ず、第
１図ｔａ＋に示すように、後工程でシリコン基板１を素
子に分割するためにスクライビングを行う幅１５０−の
スクライビング予定領域２の表面上に、公知のＣＶＤ技
術とフォトリソグラフィ技術を用いて幅５０−の帯状シ
リコン窒化膜３を形成する。ここで１１００℃、２時間
の窒素中での熱処理を施すと、シリコン窒化膜３の無い
ｗＩ域は表面の酸素が外方拡散され、第１図（ｂｌに示
すように表面から２０−以上の深さまで酸素の欠乏層４
が生ずる。Figures 1 (fat to fc) sequentially show the steps of an intrinsic gettering method according to an embodiment of the present invention. First, as shown in Figure 1 (ta+), the silicon substrate 1 is divided into elements in the subsequent process. A band-shaped silicon nitride film 3 having a width of 50 mm is formed on the surface of a region 2 to be scribed with a width of 150 mm using known CVD and photolithography techniques. Here, when heat treatment is performed in nitrogen at 1100°C for 2 hours, oxygen on the surface is diffused outward in the wI region where there is no silicon nitride film 3, and as shown in Fig. Oxygen-deficient layer at depth 4
occurs.
このあと、シリコン窒化膜３を公知のエツチングにより
除去し、その後通常の素子製造プロセスにて加熱工程を
施すか、低温熱処理と中温熱処理をするか、いずれにし
ろ何らかの析出処理を施すとシリコン基板１中の酸素欠
乏層４以外の部分１１に酸素は析出し、その酸素析出核
に基板内の汚染不純物や微小欠陥が取り込まれる （第
１図［Ｃ１）、このとき、酸素欠乏層は欠陥のないデヌ
ーデッド・ゾーン５になり、スクライビングされるかま
たはその影響を受ける領域２以外のデヌーデフド・ゾー
ン５に素子が作成される。After this, the silicon nitride film 3 is removed by known etching, and then a heating process is performed in a normal device manufacturing process, or low-temperature heat treatment and medium-temperature heat treatment are performed. Oxygen precipitates in the part 11 other than the oxygen-deficient layer 4 in the substrate 1, and contaminant impurities and minute defects in the substrate are taken into the oxygen-precipitated nuclei (Fig. 1 [C1). At this time, the oxygen-deficient layer denuded zone 5 and elements are created in the denuded zone 5 other than the area 2 that is scribed or affected by it.
第１図（Ｃ１の状態を従来の方法でデヌーデッド・ゾー
ン５を形成し、第２図の状態と比較すると、本発明の実
施例ではスクライプライン予定領域２の下の析出欠陥層
１１の突出部の体積分、すなわち数十分の−ないし数百
分の−だけゲッタリング能力が増加する。さらに、析出
欠陥層１１が素子作成領域であるデヌーデッド・ゾーン
５の側方に近接しているため、シリコン基板１の内部ま
で拡散してこないような汚染不純物でも取り込むことが
できる効果がある。この効果は、ＩＣの微細化の進展に
伴い、熱処理の低温化、短時間化が進むと重要になって
くる。Comparing the state shown in FIG. 1 (C1) with the state shown in FIG. The gettering ability increases by the volume of , that is, tens of minutes to hundreds of minutes.Furthermore, since the precipitation defect layer 11 is close to the side of the denuded zone 5, which is the device fabrication region, It has the effect of being able to incorporate even contaminant impurities that do not diffuse into the interior of the silicon substrate 1.This effect becomes important as heat treatment becomes lower in temperature and shorter in time as ICs become smaller. It's coming.
本発明によれば、イントリンシック・ゲッタリングの析
出欠陥層を半導体基板の厚さ方向の中央部のみでなく、
素子の作成されない基板分割部類域にも形成することに
より、析出欠陥層の体積増大と素子作成領域への近接に
よってゲッタリング効果が向上する。この向上は、デヌ
ーデッド・ゾーンの深いほど、あるいは基板の分割数が
太き（分割部類域の占める面積の割合の大きいほど大き
い、さらにＩＣの微細化に伴い、工程中の熱処理の低温
化、短時間化が進むことにより、表面付近にとどまる汚
染不純物の多い場合に本発明は極めて有効である。According to the present invention, the precipitation defect layer of intrinsic gettering is formed not only in the central part of the semiconductor substrate in the thickness direction;
By forming the layer also in the divided substrate area where no element is formed, the gettering effect is improved by increasing the volume of the precipitation defect layer and bringing it closer to the element forming area. This improvement increases as the depth of the denuded zone increases, or as the number of divisions in the board increases (as the area occupied by the division area increases).Furthermore, with the miniaturization of ICs, the heat treatment during the process is lowered in temperature and shorter. The present invention is extremely effective when a large amount of contaminant impurities remain near the surface as the time progresses.
第１図（ａ）〜ｆｃｌは本発明の一実施例のイントリン
シック・ゲッタリング方法の工程を順次示す断面図、第
２図は従来のイントリンシック・ゲッタリング方法を示
す断面図である。
１：シリコン基板、２：スクライプライン予定領域、−
３＝シリコン窒化膜、４：酸素欠乏層、５：デヌーデッ
ド・ゾーン、１１：析出欠陥層。FIGS. 1(a) to fcl are cross-sectional views sequentially showing the steps of an intrinsic gettering method according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a conventional intrinsic gettering method. 1: Silicon substrate, 2: Scripe line planned area, -
3 = silicon nitride film, 4: oxygen-deficient layer, 5: denuded zone, 11: precipitation defect layer.
Claims (1)
方へ拡散させる熱処理を行う際に、素子相互間の分割部
領域を酸素を通さない物質で被覆することを特徴とする
イントリンシック・ゲッタリング方法。(1) Intrinsic technology, characterized in that when heat treatment is performed to diffuse oxygen outward from the surface area of the semiconductor substrate, which is the element fabrication area, the dividing area between the elements is covered with a substance that does not allow oxygen to pass through. Gettering method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21876488A JPH0266946A (en) | 1988-09-01 | 1988-09-01 | Intrinsic gettering method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21876488A JPH0266946A (en) | 1988-09-01 | 1988-09-01 | Intrinsic gettering method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0266946A true JPH0266946A (en) | 1990-03-07 |
Family
ID=16725032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21876488A Pending JPH0266946A (en) | 1988-09-01 | 1988-09-01 | Intrinsic gettering method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0266946A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008034849A (en) * | 2006-07-27 | 2008-02-14 | Siltronic Ag | Single crystal semiconductor wafer having region with reduced defects, and manufacturing method thereof |
-
1988
- 1988-09-01 JP JP21876488A patent/JPH0266946A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008034849A (en) * | 2006-07-27 | 2008-02-14 | Siltronic Ag | Single crystal semiconductor wafer having region with reduced defects, and manufacturing method thereof |
| US8088219B2 (en) | 2006-07-27 | 2012-01-03 | Siltronic Ag | Monocrystalline semiconductor wafer comprising defect-reduced regions and method for producing it |
| US8216361B2 (en) | 2006-07-27 | 2012-07-10 | Siltronic Ag | Monocrystalline semiconductor wafer comprising defect-reduced regions and method for producing it |
| JP2012134516A (en) * | 2006-07-27 | 2012-07-12 | Siltronic Ag | Manufacturing method of single crystal semiconductor wafer |
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