JPH01298726A - Manufacture of semiconductor wafer and semiconductor device using the semiconductor wafer - Google Patents
Manufacture of semiconductor wafer and semiconductor device using the semiconductor waferInfo
- Publication number
- JPH01298726A JPH01298726A JP12840588A JP12840588A JPH01298726A JP H01298726 A JPH01298726 A JP H01298726A JP 12840588 A JP12840588 A JP 12840588A JP 12840588 A JP12840588 A JP 12840588A JP H01298726 A JPH01298726 A JP H01298726A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- region
- insulating film
- semiconductor wafer
- defective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000000137 annealing Methods 0.000 claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000001301 oxygen Substances 0.000 claims abstract description 15
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 15
- 239000013078 crystal Substances 0.000 claims abstract description 13
- 230000007547 defect Effects 0.000 abstract description 21
- 238000005247 gettering Methods 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 239000002244 precipitate Substances 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 43
- 239000010410 layer Substances 0.000 description 14
- 230000000694 effects Effects 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007730 finishing process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体ウェハの製造技術およびその半導体ウ
ェハを用いた半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor wafer manufacturing technique and a semiconductor device using the semiconductor wafer.
半導体ウェハ（以下、ウェハという）の内部に生じた酸
素析出欠陥を利用して汚染不純物を素子活性領域以外の
箇所に集め、その悪影響の除去を図ることを目的とする
イントリンシック・ゲッタリング（ｉｎｔｒｉｎｓｉｃ
Ｇｅｔｔｅｒｉｎｇ； 以下、ＩＧという）技術が
、ウェハ上に形成される集積回路の特性や歩留りを向上
させるための不可欠の技術になっている。Intrinsic gettering is a method that uses oxygen precipitation defects that occur inside a semiconductor wafer (hereinafter referred to as a wafer) to collect contaminant impurities in areas other than the device active region and remove their negative effects.
BACKGROUND ART Gettering (hereinafter referred to as IG) technology has become an essential technology for improving the characteristics and yield of integrated circuits formed on wafers.
上記ＩＧのプロセスは、例えば特開昭５５−９６６４１
号公報や特開昭５６−８０１３９号公報に記載があるよ
うに、■ウェハの表面近傍に無欠陥領域（デヌーデッド
・ゾーン；ｄｅｎｕｄｅｄ ｚｏｎｅ）を形成するため
の高温アニール（約１０５０〜１２００℃）、■ウェハ
の内部に欠陥核を形成するための低温アニール（約６０
゛０〜８００℃）、■ウェハ内部の微小欠陥を上記欠陥
核の周囲に集中させて高密度欠陥領域を形成するだめの
中温アニール（約１０００℃前後）からなり、通常、ア
ニールを高温−低温−中温の順序で行うプロセス（特開
昭５６−８０１３９号）と、低温−高温−中温の順序で
行うプロセス（特開昭５５−９６６４１号公報）とが採
用されている。The above IG process is described in, for example, Japanese Patent Application Laid-Open No. 55-96641.
As described in Japanese Patent Publication No. 56-80139, (1) high-temperature annealing (approximately 1050 to 1200°C) to form a defect-free region (denuded zone) near the surface of the wafer; ■Low temperature annealing (approximately 60
(0 to 800°C), (2) Medium temperature annealing (around 1000°C) to concentrate micro defects inside the wafer around the defect cores to form a high-density defect region. - A process performed in the order of medium temperature (Japanese Patent Application Laid-Open No. 56-80139) and a process performed in the order of low temperature-high temperature-medium temperature (Japanese Patent Application Laid-Open No. 55-96641) are adopted.
また、上記ＩＧは、プロセス導入前の段階であらかじめ
行う場合と、プロセス中の熱処理工程を利用して行う場
合とがあるが、いずれの場合においても、チョクラルス
キー法（ＣＺ法）による結晶育成時にドープされる酸素
濃度が、例えば９． ＯＸ １０” 〜１． Ｉ Ｘ
１０”原子／ｃｄ（日本電子工業振興協会換算係数、以
下同様）程度の高酸素濃度シリコン単結晶ウェハを使用
するのが通常である。In addition, the above IG may be performed in advance at a stage before introducing the process, or may be performed using a heat treatment step during the process, but in either case, crystal growth using the Czochralski method (CZ method) is performed. Sometimes the concentration of oxygen doped is, for example, 9. OX 10" ~ 1.I
It is usual to use a silicon single crystal wafer with a high oxygen concentration of about 10'' atoms/cd (Japan Electronics Industry Promotion Association conversion factor, hereinafter the same).
本発明者の検討によれば、高酸素濃度シリコン単結晶ウ
ェハを用いて行われる従来のＩＣ技術には、下記のよう
な問題がある。According to studies by the present inventors, conventional IC technology using high oxygen concentration silicon single crystal wafers has the following problems.
まず、アニールを高温−低温−中温の順序で行うＩＧプ
ロセスでは、ウェハ表面に無欠陥領域を形成する高温ア
ニールを行った後に内部欠陥核を形成する低温アニール
を行うため、欠陥核が発生し難いという欠点があり、長
時間の低温アニールを行わなければならない。First, in the IG process, in which annealing is performed in the order of high temperature, low temperature, and medium temperature, defect nuclei are unlikely to occur because high temperature annealing is performed to form a defect-free area on the wafer surface, and then low temperature annealing is performed to form internal defect nuclei. This has the disadvantage of requiring long-term low-temperature annealing.
待に、近年は、プロセスの低温指向が進展しているため
、高温アニールをプロセス中に行う場合には、アニール
時間が不足し、後の中温プロセスの際に内部欠陥がウェ
ハの表面に浮き上がってくる虞れがある。In recent years, processes have become increasingly low-temperature-oriented, so if high-temperature annealing is performed during the process, the annealing time is insufficient, and internal defects may rise to the surface of the wafer during the subsequent medium-temperature process. There is a risk that this may occur.
一方、アニールを低温−高温−中温の順序で行うＩＧプ
ロセスでは、内部欠陥核を形成する低温アニールを行っ
た後に無欠陥領域を形成する高温アニールを行うため、
低温アニール時間を短縮できるという利点がある反面、
無欠陥領域内すなわち素子活性領域内に微小欠陥が残留
し易いという欠点がある。On the other hand, in the IG process where annealing is performed in the order of low temperature - high temperature - medium temperature, low temperature annealing is performed to form internal defect nuclei, and then high temperature annealing is performed to form defect-free regions.
Although it has the advantage of shortening low-temperature annealing time,
There is a drawback that micro defects tend to remain in the defect-free region, that is, in the element active region.
また、高温アニールをプロセス中に行う場合には、前記
した理由により、後の中温プロセスの際に内部欠陥がウ
ェハの表面に浮き上がってくる虞れがある。Furthermore, if high temperature annealing is performed during the process, there is a risk that internal defects will rise to the surface of the wafer during the subsequent medium temperature process for the reasons described above.
本発明は、上記した問題点に着目してなされたものであ
り、その目的は、高品質の無欠陥領域を有するシリコン
単結晶ウェハの製造方法およびそのウェハを用いた半導
体装置を提供することにある。The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a method for manufacturing a silicon single crystal wafer having a high-quality defect-free area and a semiconductor device using the wafer. be.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、チョクラルスキー法によって育成された高酸
素濃度シリコン単結晶からなるウェハに低温アニール処
理を施した後、その表面にシリコンエピタキシャル層を
形成する方法である。That is, this is a method in which a wafer made of high oxygen concentration silicon single crystal grown by the Czochralski method is subjected to low-temperature annealing treatment, and then a silicon epitaxial layer is formed on the surface of the wafer.
シリコンエピタキシャル層の格子間酸素濃度は、チョク
ラルスキー法によって得られるシリコン単結晶の格子間
酸素濃度よりも約−桁低いため、１０００℃程度の中温
処理を施してもエピタキシャル層中に微小欠陥が発生す
ることはない。The interstitial oxygen concentration in the silicon epitaxial layer is about an order of magnitude lower than the interstitial oxygen concentration in the silicon single crystal obtained by the Czochralski method, so even if medium temperature treatment of about 1000°C is performed, micro defects will not occur in the epitaxial layer. It will never occur.
すなわち、このエピタキシャル湿を無欠陥領域として利
用できるため、無欠陥領域の形成を目的とする高温アニ
ールを欠くか、または高温アニール時間が短い場合でも
、高品質の無欠陥領域を有するウェハが得られる。In other words, since this epitaxial moisture can be used as a defect-free area, a wafer with a high-quality defect-free area can be obtained even if high-temperature annealing for the purpose of forming a defect-free area is omitted or the high-temperature annealing time is short. .
また、約６００〜８００℃の低温アニールを施した高酸
素濃度シリコン単結晶ウェハは、その後中温アニールを
施すことによって、内部欠陥核に酸素が析出して欠陥核
の成長が起こるため、ウェハ全体がゲッタリング作用を
持つようになる。In addition, high oxygen concentration silicon single crystal wafers that have been annealed at a low temperature of about 600 to 800°C are then subjected to medium temperature annealing, which causes oxygen to precipitate into internal defect nuclei and cause the defect nuclei to grow. It has a gettering effect.
従って、低温アニールを施した後、その表面にエピタキ
シャル層を形成したウェハは、無欠陥領域の形成を目的
とする高温アニールを省略することができることから、
内部欠陥の成長が容易になるため、欠陥核形成のための
低温アニールも短時間で済む。Therefore, for wafers on which an epitaxial layer is formed on the surface after low-temperature annealing, high-temperature annealing for the purpose of forming defect-free regions can be omitted.
Since growth of internal defects is facilitated, low-temperature annealing for defect nucleation can be done in a short time.
第１図（ａ）〜（６）は、本発明の一実施例である半導
体ウェハを用いた半導体装置の製造工程を示す半導体ウ
ェハの要部断面図である。FIGS. 1(a) to 1(6) are cross-sectional views of essential parts of a semiconductor wafer showing the manufacturing process of a semiconductor device using a semiconductor wafer according to an embodiment of the present invention.
まず、チョクラルスキー法によって、例えば初期格子間
酸素濃度＝１０ＸｌＯ”原子／ｃｒｌ（日本電子工業振
興協会換算係数）、抵抗率＝約１００・Ｃｍのシリコン
単結晶インゴットを引き上げ、これを面方位が（１００
）となるようにスライスしてウェハを作成する。First, by the Czochralski method, for example, a silicon single crystal ingot with an initial interstitial oxygen concentration = 10XlO'' atoms/crl (Japan Electronics Industry Promotion Association conversion coefficient) and a resistivity = approximately 100 cm is pulled, and this is (100
) to create wafers.
次に、上記ウェハの表面をラッピングした後、例えば７
００℃の窒素雰囲気中で３時間低温アニールを施して内
部全体に欠陥核を形成する。Next, after lapping the surface of the wafer, for example,
Low-temperature annealing is performed for 3 hours in a nitrogen atmosphere at 00° C. to form defect nuclei throughout the interior.
次に、ポリッシングを行って、ウェハの表面を鏡面仕上
げした後、ＣＶＤ法によってウェハの表面に、例えば膜
厚＝約１０μｍ１抵抗率＝約１０Ω・ａｍのｐ形シリコ
ンエピタキシャル層を形成し、このエピタキシャル層を
素子活性領域に用いてその表面に所望する集積回路を形
成する。Next, after performing polishing to give the surface of the wafer a mirror finish, a p-type silicon epitaxial layer with a film thickness of approximately 10 μm and a resistivity of approximately 10 Ω・am, for example, is formed on the surface of the wafer using the CVD method. The layer is used as a device active region to form the desired integrated circuit on its surface.
まず、第１図（ａ）に示すように、ウェハ１の表面に形
成されたエピタキシャル層２の主面に熱酸化法で薄い絶
縁膜３を形成し、その表面にＣＶＤ法によって被着した
５ｉｓＮ４膜４をエツチングして能動領域にのみ５ｉｓ
Ｎ＜膜４を残した後、エピタキシャル層２０表面から、
例えばホウ素（Ｂ）イオンを打ち込んでチャネルストッ
パ領域５を形成し、次いでウェハ１を、例えば１０００
℃で５時間スチーム酸化してフィールド絶縁膜６を形成
する。First, as shown in FIG. 1(a), a thin insulating film 3 is formed by thermal oxidation on the main surface of an epitaxial layer 2 formed on the surface of a wafer 1, and 5isN4 is deposited on the surface by CVD. Etching the membrane 4 and adding 5is only to the active area
N<After leaving the film 4, from the surface of the epitaxial layer 20,
For example, boron (B) ions are implanted to form the channel stopper region 5, and then the wafer 1 is
A field insulating film 6 is formed by steam oxidation at .degree. C. for 5 hours.
上記スチーム酸化の際、ウェハｌの内部においては欠陥
核に格子間酸素が析出し、Ｓ ｉ Ｏ，析出物や積層欠
陥などのゲッタリング源となる内部欠陥が成長する。During the steam oxidation, interstitial oxygen precipitates at defect nuclei inside the wafer 1, and internal defects that become gettering sources such as SiO, precipitates, and stacking faults grow.
次に、能動領域の絶縁膜３とＳｌ＊Ｎｓ膜４とを除去し
て第一ゲート絶縁膜７を形成した後、ウェハ１の表面に
被着した、例えばポリシリコンからなる第一の導電層を
パターニングしてキャパシタ電極８を形成し、次いで、
第一ゲート絶縁膜７を除去した後、ウェハ１を熱酸化し
てトランジスタ形成領域には第二ゲート絶縁膜９を、ま
たキャパシタ電極８０表面には絶縁膜ｌＯをそれぞれ形
成する（第１図（ｂ））。Next, after removing the active region insulating film 3 and the Sl*Ns film 4 to form a first gate insulating film 7, a first conductive layer made of polysilicon, for example, is deposited on the surface of the wafer 1. is patterned to form a capacitor electrode 8, and then
After removing the first gate insulating film 7, the wafer 1 is thermally oxidized to form a second gate insulating film 9 in the transistor formation region and an insulating film 10 on the surface of the capacitor electrode 80 (see FIG. 1). b)).
次に、ウェハ１の表面に被着した、例えばポリシリコン
とタングステンシリサイド（ＷＳｉ、）との二層からな
る第二の導電層をパターニングして第二ゲート絶縁膜９
０表面にゲート電極１１を形成した後、ウェハ１の表面
にヒ素（Ａｓ）などのｎ形不純物イオンを打ち込んでゲ
ート電極１１の両側に自己整合的にソース・ドレイン領
域１２を形成し、次いでウェハｌの表面に、例えばリン
ケイ酸ガラス（ＰＳＧ）やホウ素リンケイ酸ガラス（Ｂ
Ｐ Ｓ Ｇ）からなる層間絶縁膜１３を被着する（第
１図（Ｃ））。Next, a second conductive layer consisting of two layers of, for example, polysilicon and tungsten silicide (WSi) adhered to the surface of the wafer 1 is patterned to form a second gate insulating film 9.
After forming a gate electrode 11 on the surface of the wafer 1, n-type impurity ions such as arsenic (As) are implanted into the surface of the wafer 1 to form source/drain regions 12 in a self-aligned manner on both sides of the gate electrode 11. For example, phosphosilicate glass (PSG) or boron phosphosilicate glass (B
An interlayer insulating film 13 made of PSG) is deposited (FIG. 1(C)).
次に、ソース・ドレイン領域１２の上方領域を孔開けし
てコンタクトホール１４を形成した後、ウェハ１の表面
に被着したＡｌ膜をパターニングしてＡＩ！配線１５を
形成し、次いでウェハ１の表面をパッシベーション膜１
６で被覆した後、その所定箇所を孔開けして電極バッド
１７を形成することにより、ＭＯ３Ｏ３セメモリ素子成
する（第１図（６））。Next, after forming a contact hole 14 in the upper region of the source/drain region 12, the Al film deposited on the surface of the wafer 1 is patterned to form an AI! After forming the wiring 15, the surface of the wafer 1 is coated with a passivation film 1.
6, and then holes are formed at predetermined locations to form electrode pads 17, thereby forming an MO3O3 memory element (FIG. 1 (6)).
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.
前記実施例では、ラフピング工程後に低温アニ ｌ−ル
を行ったが、これに限るものではなく、例えばポリッシ
ングによる鏡面仕上げ工程の後、ウェハプロセス導入前
に低温アニールを行ってもよい。In the above embodiment, low-temperature annealing was performed after the roughing process, but the present invention is not limited to this. For example, low-temperature annealing may be performed after a mirror finishing process by polishing and before introducing a wafer process.
さらに、ＭＯ３形半導体装置のみならず、バイポーラ形
半導体装置など、シリコン単結晶からなるウェハを用い
た各種半導体装置に適用することができる。Furthermore, the present invention can be applied not only to MO3 type semiconductor devices but also to various semiconductor devices using a wafer made of silicon single crystal, such as bipolar type semiconductor devices.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、チョクラルスキー法によって育成された高酸
素濃度シリコン単結晶からなるウェハに低温アニール処
理を施した後、その表面にシリコンエピタキシャル層を
形成することにより、高品質の無欠陥領域と欠陥核成長
領域とを有するウェハが得られるため、このウェハ上に
形成される集積回路およびそれを用いた半導体装置の信
頼性が向上する。In other words, a wafer made of high oxygen concentration silicon single crystal grown by the Czochralski method is subjected to low-temperature annealing treatment, and then a silicon epitaxial layer is formed on the surface, resulting in high-quality defect-free areas and defect nucleus growth. Since a wafer having a region is obtained, the reliability of an integrated circuit formed on this wafer and a semiconductor device using the same is improved.
第１図（ａ）〜（ｄ）は、本発明の一実施例である半導
体ウェハを用いた半導体装置の製造工程を示す半導体ウ
ェハの要部断面図である。
１・・・シリコン単結晶ウェハ、２・・・エピタキシャ
ル層、３．１０・・・絶縁膜、４・・・５１３Ｎ４膜、
５・・・チャネルストッパ領域、６・・・フィールド絶
縁膜、７・・・第一ゲート絶縁膜、８・・・キャパシタ
電極、９・・・第二ゲート絶縁膜、１１・・・ゲート電
極、１２・・・ソース・ドレイン領域、１３・・・層間
絶縁膜、１４・・・コンタクトホール、１５・・・Ａｌ
配線、１６・・・パッシベーション膜、１７・・・電極
パッド。
第１図
１、シリコン曽佐品りシへ
２ 工と０９キンてル層FIGS. 1(a) to 1(d) are sectional views of essential parts of a semiconductor wafer, showing the manufacturing process of a semiconductor device using a semiconductor wafer according to an embodiment of the present invention. 1... Silicon single crystal wafer, 2... Epitaxial layer, 3.10... Insulating film, 4... 513N4 film,
5... Channel stopper region, 6... Field insulating film, 7... First gate insulating film, 8... Capacitor electrode, 9... Second gate insulating film, 11... Gate electrode, 12... Source/drain region, 13... Interlayer insulating film, 14... Contact hole, 15... Al
Wiring, 16... Passivation film, 17... Electrode pad. Fig. 1 1, Silicon Sosagina Rishihe 2 engineering and 09 Kinteru layer
Claims (1)
シリコン単結晶からなる半導体ウェハに低温アニール処
理を施した後、前記半導体ウェハの表面にシリコンエピ
タキシャル層を形成することを特徴とする半導体ウェハ
の製造方法。 ２、請求項１記載の製造方法によって得られた半導体ウ
ェハ上に所定の集積回路を形成した半導体装置。[Claims] 1. A semiconductor wafer made of high oxygen concentration silicon single crystal grown by the Czochralski method is subjected to low-temperature annealing treatment, and then a silicon epitaxial layer is formed on the surface of the semiconductor wafer. A method for manufacturing a semiconductor wafer. 2. A semiconductor device in which a predetermined integrated circuit is formed on a semiconductor wafer obtained by the manufacturing method according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12840588A JPH01298726A (en) | 1988-05-27 | 1988-05-27 | Manufacture of semiconductor wafer and semiconductor device using the semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12840588A JPH01298726A (en) | 1988-05-27 | 1988-05-27 | Manufacture of semiconductor wafer and semiconductor device using the semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01298726A true JPH01298726A (en) | 1989-12-01 |
Family
ID=14983974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12840588A Pending JPH01298726A (en) | 1988-05-27 | 1988-05-27 | Manufacture of semiconductor wafer and semiconductor device using the semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01298726A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5444001A (en) * | 1992-12-25 | 1995-08-22 | Nec Corporation | Method of manufacturing a semiconductor device readily capable of removing contaminants from a silicon substrate |
| WO1998025299A1 (en) * | 1996-12-03 | 1998-06-11 | Sumitomo Metal Industries., Ltd. | Method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device |
| JP2002076006A (en) * | 2000-08-31 | 2002-03-15 | Mitsubishi Materials Silicon Corp | Method of manufacturing epitaxial wafer and epitaxial wafer manufactured by the method |
| JP2004224694A (en) * | 1998-10-14 | 2004-08-12 | Memc Electron Materials Inc | Epitaxial silicon wafer not substantially having crystal growth transfer defect |
| KR100622622B1 (en) * | 1998-05-22 | 2006-09-11 | 신에쯔 한도타이 가부시키가이샤 | A method for producing an epitaxial silicon single crystal wafer and the epitaxial silicon single crystal wafer |
-
1988
- 1988-05-27 JP JP12840588A patent/JPH01298726A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5444001A (en) * | 1992-12-25 | 1995-08-22 | Nec Corporation | Method of manufacturing a semiconductor device readily capable of removing contaminants from a silicon substrate |
| WO1998025299A1 (en) * | 1996-12-03 | 1998-06-11 | Sumitomo Metal Industries., Ltd. | Method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device |
| EP0954018A1 (en) * | 1996-12-03 | 1999-11-03 | Sumitomo Metal Industries Limited | Method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device |
| US6277193B1 (en) | 1996-12-03 | 2001-08-21 | Sumitomo Metal Industries, Ltd. | Method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device |
| KR100319413B1 (en) * | 1996-12-03 | 2002-01-05 | 고지마 마타오 | Method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device |
| EP0954018A4 (en) * | 1996-12-03 | 2006-07-19 | Sumitomo Mitsubishi Silicon | Method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device |
| KR100622622B1 (en) * | 1998-05-22 | 2006-09-11 | 신에쯔 한도타이 가부시키가이샤 | A method for producing an epitaxial silicon single crystal wafer and the epitaxial silicon single crystal wafer |
| JP2004224694A (en) * | 1998-10-14 | 2004-08-12 | Memc Electron Materials Inc | Epitaxial silicon wafer not substantially having crystal growth transfer defect |
| JP2002076006A (en) * | 2000-08-31 | 2002-03-15 | Mitsubishi Materials Silicon Corp | Method of manufacturing epitaxial wafer and epitaxial wafer manufactured by the method |
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