JPH0263160A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPH0263160A JPH0263160A JP63214226A JP21422688A JPH0263160A JP H0263160 A JPH0263160 A JP H0263160A JP 63214226 A JP63214226 A JP 63214226A JP 21422688 A JP21422688 A JP 21422688A JP H0263160 A JPH0263160 A JP H0263160A
- Authority
- JP
- Japan
- Prior art keywords
- word selection
- selection line
- gate
- oxide film
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 13
- 230000000694 effects Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- -1 tungsten (W) Chemical compound 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
- H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体記憶装置に関し、特に１トランジスタ型
ダイナミックメモリセルに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a one-transistor type dynamic memory cell.
［従来の技術］
従来、１トランジスタ型ダイナミックメモリセルは、第
２図に示すように８１半導体基板２０１に於てフィール
ド酸化膜２０２に囲まれたアクティブ領域表面にゲート
絶縁膜２０８を介してセルプレートと称する多結晶Ｓ１
第１ゲート２０４が形成され、この第１ケート２０４の
上に絶縁膜２０５を介して転送部となる第２ゲート２０
６が形成されて、その一部がゲート絶縁膜２０３上に延
在し、第２ゲート２０６の形成されないゲート絶縁膜２
０８下の半導体表面に基板と異なる導電型の不純物導入
層２０７がデータ線として形成されたセル構造を有し、
上記セルプレート２０４下を蓄積容量部とし、これに対
して転送部（ＭＯＳＦＥＴ）を介してデータの書き込み
、読み出しを行うようになっている。また集積度の向上
のため蓄積容量部を半導体基板上の開孔部に形成する溝
型メモリセルもある。[Prior Art] Conventionally, as shown in FIG. 2, a one-transistor type dynamic memory cell has a cell plate formed on the surface of an active region surrounded by a field oxide film 202 in a semiconductor substrate 201 via a gate insulating film 208. A polycrystalline S1 called
A first gate 204 is formed on the first gate 204, and a second gate 20 serving as a transfer section is formed on the first gate 204 with an insulating film 205 interposed therebetween.
6 is formed, a part of which extends over the gate insulating film 203, and the gate insulating film 2 where the second gate 206 is not formed.
It has a cell structure in which an impurity-introduced layer 207 of a conductivity type different from that of the substrate is formed as a data line on the semiconductor surface below 08,
The area below the cell plate 204 is used as a storage capacitor section, to which data is written and read via a transfer section (MOSFET). There is also a trench type memory cell in which a storage capacitor portion is formed in an opening on a semiconductor substrate in order to improve the degree of integration.
［発明が解決しようとする問題点］
上述した従来の１トランジスタ型ダイナミックメモリセ
ルは、蓄積容量部と転送用ＭＯ３ＦＥＴが同一半導体基
板表面上に形成されるため、１ビット当りの占有面積を
小さくできないという欠点があった。[Problems to be Solved by the Invention] In the conventional one-transistor type dynamic memory cell described above, the storage capacitor section and the transfer MO3FET are formed on the same semiconductor substrate surface, so the area occupied per bit cannot be reduced. There was a drawback.
［発明の従来技術に対する相違点］
上述した従来の１トランジスタ型ダイナミックメモリセ
ルに対して、本発明は蓄積容量部上に転送用ＭＯ５ＦＥ
Ｔを形成したという相違点を有する。[Differences between the invention and the prior art] In contrast to the conventional one-transistor type dynamic memory cell described above, the present invention has a transfer MO5FE on the storage capacitor section.
The difference is that a T is formed.
［問題点を解決するための手段］
本発明の半導体記憶装置は、１トランジスタ型ダイナミ
ックメモリセルにおいて、第１の導電型を有する半導体
基板内に形成された第２の導電型を有する電荷蓄積領域
と、該半導体基板上に絶縁膜を介して形成された語選択
線と、語選択線上に形成されビット線を有し、該電荷蓄
積領域とビット線が語選択線の開孔部に語選択線とゲー
ト酸化膜を介して形成された第１の導電型を有する半導
体で接続されていることを特徴とする。[Means for Solving the Problems] A semiconductor memory device of the present invention includes a charge storage region having a second conductivity type formed in a semiconductor substrate having a first conductivity type in a one-transistor type dynamic memory cell. and a word selection line formed on the semiconductor substrate via an insulating film, and a bit line formed on the word selection line, and the charge storage region and the bit line are connected to the word selection line in the opening of the word selection line. It is characterized in that it is connected by a semiconductor having a first conductivity type formed through a line and a gate oxide film.
すなわち、本発明の１トランジスタをダイナミックメモ
リセルは、半導体基板表面に形成された蓄積容量部と、
半導体基板上にフィールド絶縁膜を介して形成された語
選択線と、語選択線より上層にゲー）Ｒ化膜を介して形
成されたビット線を有し、データ転送用ＭＯ５ＦＥＴが
語選択に開孔された内部に形成された半導体と語選択線
により形成されることを特徴としている。That is, a dynamic memory cell using one transistor of the present invention includes a storage capacitor formed on the surface of a semiconductor substrate,
It has a word selection line formed on the semiconductor substrate through a field insulating film, and a bit line formed above the word selection line through a G-R film, and the MO5FET for data transfer is opened for word selection. It is characterized by being formed by a semiconductor formed inside the hole and a word selection line.
［実施例］
次に本発明について図面に示した実施例を参照して説明
する。[Examples] Next, the present invention will be described with reference to embodiments shown in the drawings.
ここで実施例はすべてＰ型半導体基板を用いた場合を例
にとり説明するが、Ｎ型半導体を用いた場合も同様の構
造を形成することにより同様な効果を得ることができる
。Here, all of the embodiments will be described using a P-type semiconductor substrate as an example, but similar effects can be obtained by forming a similar structure even when an N-type semiconductor is used.
第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
１０１はＰ型半導体基板、１０２は基板上に形成された
Ｎ型半導体領域、１０３は基板上に成長されたフィール
ド酸化膜、１０４はフィールド酸化膜に形成された語選
択線、１０５は前記語選択線上及び語選択線間孔部内に
形成されたＰ型半導体領域、１０６は語選択線とＰ型半
導体領域の間に形成されたゲート酸化膜、１０７はＰ型
半導体領域の表面に形成されたＮ型半導体領域である。101 is a P-type semiconductor substrate, 102 is an N-type semiconductor region formed on the substrate, 103 is a field oxide film grown on the substrate, 104 is a word selection line formed on the field oxide film, and 105 is the word selection line. 106 is a gate oxide film formed between the word selection line and the P-type semiconductor region; 107 is an N-type semiconductor region formed on the surface of the P-type semiconductor region; type semiconductor region.
ここでビット線となる１０７はＮ型半導体のかわりにタ
ングステン（Ｗ）、モリブデン（Ｍｏ）、 チタニウム
（Ｔｉ）などの金属の硅化物（シリサイド）を用いるこ
ともてきる。本実施例において、Ｐ型基板１０１上に形
成されたＮ型半導体領域１０２が蓄積容量部となり、こ
れをソースとし、語選択線１０４をゲートとし、ビット
線１０７をドレインとするＭＯＳＦＥＴを形成する。こ
のＭＯＳＦＥＴを転送ゲートとし、蓄積容量部１０２に
データの読み出し、書込みを行う。Here, the bit line 107 may be made of metal silicide (silicide) such as tungsten (W), molybdenum (Mo), or titanium (Ti) instead of the N-type semiconductor. In this embodiment, an N-type semiconductor region 102 formed on a P-type substrate 101 becomes a storage capacitance section, and a MOSFET is formed using this as a source, a word selection line 104 as a gate, and a bit line 107 as a drain. This MOSFET is used as a transfer gate to read and write data into the storage capacitor section 102.
第３図は本発明の第２実施例の縦断面図である。FIG. 3 is a longitudinal sectional view of a second embodiment of the invention.
本実施例は蓄積容量部３０２上に第１のゲート絶縁膜３
０８を介してセルプレートを形成する容量対極３０４を
形成して、その上に絶縁膜３０９を介して語選択線３０
６を形成している。ここで電荷転送用のＭＯＳＦＥＴは
ビット線３０７をドレイン、蓄積容量部３０２をソース
、語選択線３０６をゲートとして形成される。この実施
例ではゲート酸化膜３０８を容量絶縁膜として使用する
ため単位面積当りの容量値を大きくとれる利点かある。In this embodiment, a first gate insulating film 3 is formed on a storage capacitor section 302.
A capacitive counter electrode 304 forming a cell plate is formed through the electrode 08, and a word selection line 30 is formed thereon through an insulating film 309.
6 is formed. Here, the MOSFET for charge transfer is formed with the bit line 307 as the drain, the storage capacitor section 302 as the source, and the word selection line 306 as the gate. In this embodiment, since the gate oxide film 308 is used as a capacitor insulating film, there is an advantage that the capacitance value per unit area can be increased.
第４図は本発明の第３実施例の縦断面図である。FIG. 4 is a longitudinal sectional view of a third embodiment of the present invention.
本実施例において、蓄積容量部は半導体基板４０１上の
開孔部内に第１のゲート酸化膜４０８を介して形成され
る。本実施例においては、蓄積容量は基板上の開孔部の
主に側壁部に形成されるため、開孔部の深さを十分とる
ことによりメモリセル面積は蓄積容量値の制限を受けな
くなるという利点がある。In this embodiment, the storage capacitor section is formed in an opening on the semiconductor substrate 401 with a first gate oxide film 408 interposed therebetween. In this example, the storage capacitor is formed mainly on the side wall of the opening on the substrate, so by making the opening sufficiently deep, the memory cell area is no longer limited by the storage capacitance value. There are advantages.
［発明の効果］
以上説明したように本発明は、ｌトランジスタ型ダイナ
ミックメモリセルにおいてデータ転送用ＭＯＳＦＥＴを
語選択線の開孔部内に形成することにより、メモリセル
の面積を蓄積容量部が占有する面積に収めることができ
る効果がある。[Effects of the Invention] As explained above, the present invention forms a data transfer MOSFET in the opening of a word selection line in an l-transistor type dynamic memory cell, so that the storage capacitance section occupies the area of the memory cell. It has the effect of being able to fit within the area.
例えば２層１ｍルールで設計されたダイナミックメモリ
に於て、従来例では約６０μｍ２の面積が必要だったも
のが本発明の第２実施例を適用することにより約３５μ
ｍ２に縮小できる。For example, in a dynamic memory designed according to the 2-layer 1m rule, the area required in the conventional example is approximately 60 μm2, but by applying the second embodiment of the present invention, the area is approximately 35 μm2.
It can be reduced to m2.
第１図は本発明の第１実施例の縦断面図、第２図は従来
の１トランジスタ型ダイナミックメモリセルの縦断面図
、第３図は本発明の第２実施例の縦断面図、第４図は本
発明の第３実施例の縦断面図である。
１０１・・・・・・・・・・・・・・半導体基板、１０
２・・・・・・・・・・ｎ″層（蓄積容量部）、１０３
・・・・・・・・・・・フィールド酸化膜、１０４・・
・・・・・・・・・・・・・語選択線、１０５・ ・・
・ ・・・ ・・・・ ・ ・ ・・Ｐ＋領域、１０
６・・・・・・・・・・・・・ゲート酸化膜、１０７・
・・・・・・・・・・＋１”層（ビット線）、２０１・
・・・・・・・・・・・・・半導体基板、２０２・・・
・・・・・・・・フィールド酸化膜、２０３・・・・・
・・・・・・・・ゲート酸化膜、２０４・・・・・・第
１ゲート（セルプレート）、２０５・・・・・・・・・
・・・・・・・絶縁膜、２０６・・Φ・・・・・・・・
・・・第２ゲート、２０７・・・・・・・・・・・ｎ“
層（ビット線）、３０１・・・・・・・・・・・・・・
半導体基板、３０２φ・・・・・・・・・・・・・・・
ｎ＋層、３０３・・・・・・・・・・・フィールド酸化
膜、３０４・・・・・・第１ゲート（セルプレート）、
３０５・・・・・・・・・・・・・ゲート酸化膜、３０
６・・・・・・・・第２ゲート（語選択線）、３０７・
・・・・・・・・・・ｎ０層（ビット線）、３０８・・
・・・・・・・・・・・ゲート酸化膜、３０９・・・・
・・・・・・・・・・・・絶縁膜、３１０・・・・・・
・・・・・・・・・ ・Ｐ＋領域、４０１・・・・・・
・・・・・・・・半導体基板、４０２・・・・・・・・
・ｎ９領域（蓄積容量部）、４０３・・・・・・・・・
・・フィールド酸化膜、４０４・・・・・・・・・・・
・・・・語選択線、４０５・・・・・・・・ ・ ・・
・・・・Ｐ＋領域、４０６・・・・・・・・・・・・
・ゲート酸化膜、４０７・・・・・・・・・・ｎ＋層（
ビット線）、４０８・ ・・ ・・ ・・・・ ・・
・ ・ゲート酸化膜。
第１１！１
特許出願人 日本電気アイジ−マイコンシステム株式会
社1 is a vertical cross-sectional view of a first embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of a conventional one-transistor type dynamic memory cell, and FIG. 3 is a vertical cross-sectional view of a second embodiment of the present invention. FIG. 4 is a longitudinal sectional view of a third embodiment of the present invention. 101... Semiconductor substrate, 10
2......n'' layer (storage capacitor section), 103
......Field oxide film, 104...
・・・・・・・・・・・・Word selection line, 105...
・ ・ ・ ・ ・ ・ ・ P+ area, 10
6・・・・・・・・・・・・Gate oxide film, 107・
......+1" layer (bit line), 201.
...... Semiconductor substrate, 202...
......Field oxide film, 203...
......Gate oxide film, 204...First gate (cell plate), 205...
......Insulating film, 206...Φ...
・・・Second gate, 207・・・・・・・・・・・・n“
Layer (bit line), 301...
Semiconductor substrate, 302φ・・・・・・・・・・・・
n+ layer, 303...Field oxide film, 304...first gate (cell plate),
305......Gate oxide film, 30
6... Second gate (word selection line), 307.
・・・・・・・・・n0 layer (bit line), 308...
......Gate oxide film, 309...
......Insulating film, 310...
...... ・P+ area, 401...
......Semiconductor substrate, 402...
・n9 area (storage capacitor), 403...
...Field oxide film, 404...
・・・・Word selection line, 405・・・・・・・ ・ ・・
・・・・P+ area, 406・・・・・・・・・・・・
・Gate oxide film, 407......n+ layer (
bit line), 408・・・・・・・・・
・・Gate oxide film. No. 11!1 Patent applicant: NEC IG Microcomputer System Co., Ltd.
Claims (1)
第１の導電型を有する半導体基板内に形成された第２の
導電型を有する電荷蓄積領域と、該半導体基板上に絶縁
膜を介して形成された語選択線と、語選択線上に形成さ
れビット線を有し、該電荷蓄積領域とビット線が語選択
線の開口部に語選択線とゲート酸化膜を介して形成され
た第１の導電型を有する半導体で接続されていることを
特徴とする半導体記憶装置。In a one-transistor type dynamic memory cell,
A charge storage region having a second conductivity type formed in a semiconductor substrate having a first conductivity type, a word selection line formed on the semiconductor substrate via an insulating film, and a charge storage region formed on the word selection line. A bit line is provided, and the charge storage region and the bit line are connected to the opening of the word selection line by a semiconductor having a first conductivity type formed through the word selection line and a gate oxide film. Semiconductor storage device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63214226A JPH0263160A (en) | 1988-08-29 | 1988-08-29 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63214226A JPH0263160A (en) | 1988-08-29 | 1988-08-29 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0263160A true JPH0263160A (en) | 1990-03-02 |
Family
ID=16652286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63214226A Pending JPH0263160A (en) | 1988-08-29 | 1988-08-29 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0263160A (en) |
-
1988
- 1988-08-29 JP JP63214226A patent/JPH0263160A/en active Pending
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