JPH026228B2 - - Google Patents
Info
- Publication number
- JPH026228B2 JPH026228B2 JP56098715A JP9871581A JPH026228B2 JP H026228 B2 JPH026228 B2 JP H026228B2 JP 56098715 A JP56098715 A JP 56098715A JP 9871581 A JP9871581 A JP 9871581A JP H026228 B2 JPH026228 B2 JP H026228B2
- Authority
- JP
- Japan
- Prior art keywords
- switch
- phototransistor
- photodiode
- gate
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 12
- 238000003384 imaging method Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910008065 Si-SiO Inorganic materials 0.000 description 1
- 229910006405 Si—SiO Inorganic materials 0.000 description 1
- 238000005513 bias potential Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14679—Junction field effect transistor [JFET] imagers; static induction transistor [SIT] imagers
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】
本発明は、低消費電力で高速動作の特性を有
し、かつ絵素の高集積化が容易となり、占有面積
の小さなスイツチ素子で構成された固体撮像装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device that has characteristics of low power consumption and high-speed operation, facilitates high integration of picture elements, and is configured with switch elements that occupy a small area. be.
従来のＸ―Ｙアドレス型二次元固体撮像装置
は、第１図に示すごとく全体として１のような回
路構成からなつている。各絵素の一部を構成する
光電変換部のフオトダイオードあるいはMOSの
ダイオード２は、Ｘスキヤナー３とＹスキヤナー
４によつてアドレス選択される。すなわち、Ｘ信
号及びＹ信号のAND信号により光電変換電流の
経路を形成し最終的に光電変換電流は負荷抵抗５
に流れその電流変化あるいは電圧変化として外部
回路に取り出される。このような回路形式では各
絵素に対応してそれぞれスイツチ６が付加されて
おり、そのスイツチは通常MOS型素子から成つ
ている。 A conventional XY address type two-dimensional solid-state imaging device has a circuit configuration as shown in FIG. 1 as a whole. A photodiode or MOS diode 2 of a photoelectric conversion section constituting a part of each picture element is address-selected by an X scanner 3 and a Y scanner 4. That is, the path of the photoelectric conversion current is formed by the AND signal of the X signal and the Y signal, and the photoelectric conversion current finally passes through the load resistance 5.
and is taken out to an external circuit as a current change or voltage change. In this type of circuit, a switch 6 is added corresponding to each picture element, and the switch is usually composed of a MOS type element.
マトリツクスエレメントに使われるスイツチ６
に対する要求条件としてはサンプリング速度が速
く、かつ占有面積の小さい事が重要となるが、
MOSスイツチの場合、高速性に問題があつた。
しかもゲート・ドレイン間のストレーキヤパシタ
ンスが信号に混入しＳ／Ｎ比を低下させる欠点が
あり、又Si―SiO2界面等の表面現象を利用して
いるため、電気特性の安定性及び信頼性に対する
対策も必要であつた。一方、ゲート酸化膜厚の変
動やチヤネルの比抵抗分布のばらつきに起因する
画素出力の不均一性も撮像特性の性能を劣化させ
る大きな要因となつており、これらのばらつきを
押えたスイツチが望まれていた。 Switch 6 used in matrix elements
The important requirements for this are a fast sampling rate and a small occupied area.
In the case of MOS switches, there was a problem with high speed.
Moreover, it has the disadvantage that the stray capacitance between the gate and drain mixes into the signal and reduces the S/N ratio.Also, since surface phenomena such as the Si-SiO 2 interface are used, the electrical characteristics are stable and reliable. Measures regarding gender were also necessary. On the other hand, non-uniformity in pixel output due to variations in gate oxide film thickness and variations in channel resistivity distribution is also a major factor in degrading the performance of imaging characteristics, and a switch that suppresses these variations is desired. was.
本発明は、従来の素子構成におけるスイツチに
比して、スイツチング速度が速くバルク接合のた
め表面状態に対して安定でかつ電気特性の変動の
小さなスイツチの新たな構成及び駆動法の採用に
より、高速度動作と高密度画素を容易に実現し得
る固体撮像装置を提供するものである。 The present invention achieves high performance by adopting a new configuration and driving method for the switch, which has a faster switching speed than switches with conventional element configurations, is stable with respect to surface conditions due to bulk bonding, and has small fluctuations in electrical characteristics. The present invention provides a solid-state imaging device that can easily realize high-speed operation and high-density pixels.
以下図面を用いて本発明を詳細に説明する。 The present invention will be explained in detail below using the drawings.
先ず、本発明に用いられる絵素エレメントとス
イツチからなるユニツトの構成例を、第２図Ａの
斜視図及び第２図Ｂの平面図及び第２図Ｃの駆動
パルスについて説明する。このユニツトの回路構
成は光電変換部とそのスイツチ部及びそのスイツ
チをアドレス制御するAND論理部とからなり、
全体として７で示される。ユニツト７は基板８
（例えばｎ形半導体）と基板８とは逆の導電形の
半導体層９（例えばｐ形半導体）で構成されたフ
オトダイオード及び半導体層９をソースとし１０
をドレインとし基板８をゲートとするパンチスル
ー動作をする接合形トランジスタスイツチを有
し、さらにそのスイツチを駆動するためのＸ―Ｙ
アドレス用AND論理スイツチが付加されている。
このAND論理スイツチはソース１１、ドレイン
１２、表面側ゲート１３、基板側ゲート８及びチ
ヤネル層１４（p-層）の電極群と半導体層で構
成されている。なお、この論理スイツチのソー
ス・ゲート，ゲート・ドレインの各接合以外の側
面端部は第２図Ａ，Ｂに示すごとく絶縁層１５と
接している。 First, an example of the structure of a unit consisting of a pixel element and a switch used in the present invention will be described with reference to a perspective view in FIG. 2A, a plan view in FIG. 2B, and a drive pulse in FIG. 2C. The circuit configuration of this unit consists of a photoelectric conversion section, its switch section, and an AND logic section that controls the address of the switch.
The overall number is indicated by 7 . Unit 7 is board 8
(for example, an n-type semiconductor) and a semiconductor layer 9 of a conductivity type opposite to that of the substrate 8 (for example, a p-type semiconductor).
It has a junction type transistor switch that performs punch-through operation with 8 as the drain and the substrate 8 as the gate, and an X-Y transistor for driving the switch.
An AND logic switch for address is added.
This AND logic switch is composed of a source 11, a drain 12, a front side gate 13, a substrate side gate 8, a channel layer 14 (p - layer) electrode group, and a semiconductor layer. Note that side edges of this logic switch other than the source/gate and gate/drain junctions are in contact with the insulating layer 15 as shown in FIGS. 2A and 2B.
本装置の動作原理は以下の通りである。一定の
正極性バイアス電圧＋Ｖが電源１６によりオーミ
ツク電極１７を介して基板８に印加されており、
光照射下ではフローテイング電極９と基板８の接
合部に光電荷が蓄積される。ある、一定周期でゲ
ート８とドレイン１０間の電圧によりドレイン１
０から伸ばされた空乏層で、ドレイン１０とソー
ス９の間を導通させてフオトダイオードの電位を
リセツトすると共に、その際流れるリセツト電流
（ドレイン電流）を読み取る。この時のリセツト
電流は光誘起電荷量に比例し、かつ、パンチスル
ートランジスタで増幅された光電変換信号として
検出される。この蓄積読み取り方式は高感度撮像
に適している。 The operating principle of this device is as follows. A constant positive bias voltage +V is applied to the substrate 8 via the ohmic electrode 17 by the power supply 16,
Under light irradiation, photocharges are accumulated at the junction between the floating electrode 9 and the substrate 8. Due to the voltage between the gate 8 and the drain 10 at a certain period, the drain 1
The depletion layer extended from 0 conducts between the drain 10 and the source 9 to reset the potential of the photodiode and read the reset current (drain current) flowing at that time. The reset current at this time is proportional to the amount of photo-induced charge and is detected as a photoelectric conversion signal amplified by the punch-through transistor. This accumulation/reading method is suitable for high-sensitivity imaging.
チヤネル領域１４の空乏層の拡がりの大きさ
は、ユニツト７のスイツチの出力信号で制御され
る。つまり、第２図Ｃに示す駆動パルスのＸ信号
１８を表面ゲート１３に、Ｙ信号１９をドレイン
１２に、そして基板ゲート８には一定バイアス電
圧２０が印加された場合、各ゲート及びドレイン
との協同動作によりソース１１とドレイン１２の
電極間のON―OFFが制御されたANDゲートが
実現出来、画素アドレス用スイツチが形成された
ことになる。各駆動パルスのレベルの関係でゲー
ト電流を阻止する必要のある場合には、２１の
PN接合ダイオード又はシヨツトキ―バリアダイ
オードの如き電流阻止ダイオードをゲートに直列
に挿入することもできる。 The extent of the expansion of the depletion layer in the channel region 14 is controlled by the output signal of the switch of the unit 7 . In other words, when the X signal 18 of the driving pulse shown in FIG. Through cooperative operation, an AND gate with controlled ON/OFF between the source 11 and drain 12 electrodes was realized, and a pixel address switch was formed. If it is necessary to block the gate current due to the level of each drive pulse, 21
A current blocking diode such as a PN junction diode or a shot key barrier diode can also be inserted in series with the gate.
第２図ではユニツト７のドレイン１０とソース
１１とを独立に形成したが、第３図の半導体層２
８に示すごとくこれらを複合化して形成する事も
可能である。 In FIG. 2, the drain 10 and source 11 of the unit 7 are formed independently, but in FIG.
It is also possible to form a composite of these as shown in 8.
第４図に本画素を用いた二次元撮像装置の実施
例を示す。第４図のスイツチ２２はＹ列の画素信
号を選択切り換える働きをするが、単位画素で用
いたAND論理用マトリツクススイツチを用いる
か又は、電極９，８，１０を組み合わせたトラン
ジスタのパンチスルー動作によるスイツチでも実
現出来る。 FIG. 4 shows an embodiment of a two-dimensional imaging device using this pixel. The switch 22 in FIG. 4 functions to select and switch the pixel signals of the Y column, but it can be done by using the AND logic matrix switch used in the unit pixel, or by using a punch-through operation of a transistor combining electrodes 9, 8, and 10. This can also be achieved with a switch.
以上、光電変換部にフオトダイオードを用いた
場合の例について示したが、次にこれをフオトト
ランジスタで置換した場合について述べる。第５
図がその実施例の断面図であるが、各電極がそれ
ぞれコレクタ電極１７、ベース２３、エミツタ２
４から成るフオトトランジスタ２５と、それをア
ドレス選択するマトリツクススイツチ２６から成
る。ここで２６はパンチスルー動作でゲートの開
閉を行なうが、第２図で述べた形のAND論理ス
イツチでも良い。フオトトランジスタのベースを
フローテイングにして動作させた場合には蓄積モ
ードとなるが、ベース電極２７に一定バイアスを
印加した条件では非蓄積モードで用いることがで
きる。 An example in which a photodiode is used in the photoelectric conversion section has been described above, but next, a case in which this is replaced with a phototransistor will be described. Fifth
The figure is a sectional view of the embodiment, and each electrode is a collector electrode 17, a base 23, and an emitter 2.
It consists of a phototransistor 25 consisting of four phototransistors and a matrix switch 26 for selecting an address thereof. Here, 26 opens and closes the gate by punch-through operation, but it may also be an AND logic switch of the type described in FIG. When operated with the base of the phototransistor floating, it is in the accumulation mode, but under the condition that a constant bias is applied to the base electrode 27, it can be used in the non-accumulation mode.
本発明は、上記のような二次元撮像装置以外
に、分光器の検出部の如き一次元の対象物にも適
用可能である。 The present invention is applicable not only to the two-dimensional imaging device described above but also to one-dimensional objects such as the detection section of a spectrometer.
以上説明したように、本発明によれば、空乏層
の大きさを制御する事により、例えばマトリツク
ススイツチのAND論理とフオトダイオードやフ
オトトランジスタのセツト，リセツトが容易に実
現出来、しかも回路構成が単純化される。パンチ
スルー状態ではドリフト電流が支配的であるので
高速動作に有利となる他、蓄積モードではアドレ
ス選択したマトリツクススイツチのみしか電流が
流れないため画素数に無関係に低消費電力駆動が
出来る。又、MOS構造と異なつて接合構造のた
めに界面状態に対して安定であり、しかも、絶縁
ゲートが不要なため素子特性の不均一性の大きな
要因となるゲート酸化膜厚の変動にも全く無関係
である。ゲート・ドレイン間のオーバーラツプ電
極がなくストレイキヤパシタンスも少ない事から
スパイクノイズも少さく出来、Ｓ／Ｎを大きく出
来る。 As explained above, according to the present invention, by controlling the size of the depletion layer, for example, the AND logic of a matrix switch and the setting and resetting of a photodiode or phototransistor can be easily realized, and the circuit configuration can be easily realized. Simplified. In the punch-through state, the drift current is dominant, which is advantageous for high-speed operation, and in the accumulation mode, current flows only through the matrix switch whose address is selected, so low power consumption driving is possible regardless of the number of pixels. Also, unlike a MOS structure, it is stable against interface conditions due to its junction structure, and since it does not require an insulated gate, it is completely unaffected by variations in gate oxide film thickness, which is a major factor in the non-uniformity of device characteristics. It is. Since there is no overlapping electrode between the gate and drain and there is little stray capacitance, spike noise can be reduced and the S/N ratio can be increased.
なお、以上の実施例ではｎ形半導体基板を例に
示したがｐ形基板とそれに対応する電極層を用い
ても得られる効果は同様に大きい。又、以上の如
き実施例の横形構造電界効果トランジスタ以外に
縦形構造においても、本発明を実施出来る事は明
らかである。 In the above embodiments, an n-type semiconductor substrate was used as an example, but the same effect can be obtained by using a p-type substrate and a corresponding electrode layer. Furthermore, it is clear that the present invention can be practiced not only in the horizontal structure field effect transistor of the above-described embodiments but also in a vertical structure.
第１図は従来のＸ―Ｙアドレス形二次元イメー
ジセンサの構造概略を示すブロツクを含む回路
図、第２図Ａ，Ｂ，Ｃはフオトダイオードとスイ
ツチを組合せた本発明に用いる素子ユニツト例を
示す斜視図、平面図及び駆動パルスタイミングチ
ヤート、第３図Ａ，Ｂはフオトダイオードとスイ
ツチを複合対した本発明に用いる素子ユニツト例
を示す斜視図及び平面図、第４図は本発明の実施
例を示す平面構造図、第５図はフオトトランジス
タとスイツチを組合せた本発明に用いる素子ユニ
ツト例を示す断面図である。
１……二次元センサ、２……フオトダイオー
ド、３……Ｘ方向スキヤナー、４……Ｙ方向スキ
ヤナー、５……負荷抵抗、６……スイツチ、７…
…フオトダイオード及びスイツチ類から成るユニ
ツト、８……基板（ｎ形）及び基板ゲート、９…
…フオトダイオードの一部を形成する半導体層
（ｐ形）ソース、１０……ドレイン、１１……ソ
ース、１２……ドレイン、１３……表面側ゲー
ト、１４……チヤネル層（p-）、１５……絶縁
層、１６……基板に対するバイアス電源、１７…
…オーミツク電極層、１８……Ｘ―スキヤナーの
パルス、１９……Ｙ−スキヤナーのパルス、２０
……基板バイアス電位、２１……電流阻止ダイオ
ード、２２……Ｙライン選択用スイツチ、２３…
…フオトトランジスタのベース層、２４……フオ
トトランジスタのエミツタ層、２５……フオトト
ランジスタ、２６……マトリツクススイツチ、２
７……ベース電極、２８……半導体層。
Fig. 1 is a circuit diagram including blocks showing the general structure of a conventional XY address type two-dimensional image sensor, and Fig. 2 A, B, and C show an example of an element unit used in the present invention that combines a photodiode and a switch. FIGS. 3A and 3B are a perspective view and a plan view showing an example of an element unit used in the present invention that combines a photodiode and a switch, and FIG. 4 is a diagram showing an implementation of the present invention. FIG. 5 is a cross-sectional view showing an example of an element unit used in the present invention, which combines a phototransistor and a switch. 1 ...Two-dimensional sensor, 2...Photodiode, 3...X direction scanner, 4...Y direction scanner, 5...Load resistance, 6...Switch, 7 ...
...Unit consisting of photodiodes and switches, 8...Substrate (n type) and substrate gate, 9...
...Semiconductor layer (p-type) forming a part of photodiode source, 10...Drain, 11...Source, 12...Drain, 13...Front side gate, 14...Channel layer (p - ), 15 ...Insulating layer, 16... Bias power supply for substrate, 17...
...Ohmic electrode layer, 18...Pulse of X-scanner, 19...Pulse of Y-scanner, 20
...Substrate bias potential, 21... Current blocking diode, 22... Y line selection switch, 23...
... Base layer of phototransistor, 24 ... Emitter layer of phototransistor, 25 ... Phototransistor, 26 ... Matrix switch, 2
7...Base electrode, 28...Semiconductor layer.
Claims (1)
と、該フオトダイオード又はフオトトランジスタ
を周期的にリセツトするスイツチと、該リセツト
する信号を発生する論理素子とのユニツトを半導
体基板上に単位画素に対応させて複数個具備し、
該スイツチはパンチスルー動作をする接合型電界
効果トランジスタよりなり、前記論理素子のゲー
トとドレインに加えられたアドレス信号で制御さ
れる論理機能により画素を選択する如く形成し、
前記リセツト時に前記フオトダイオード又はフオ
トトランジスタの電流を読取るように構成したこ
とを特徴とする固体撮像装置。 ２ 前記ゲートへのアドレス信号はシヨツトキー
バリアダイオード又はPN接合ダイオードを介し
て印加されることを特徴とする特許請求の範囲第
１項記載の固体撮像装置。[Claims] 1. A unit consisting of a photodiode or phototransistor, a switch that periodically resets the photodiode or phototransistor, and a logic element that generates a signal for resetting the photodiode or phototransistor is provided on a semiconductor substrate corresponding to a unit pixel. Let's have multiple pieces,
The switch is composed of a junction field effect transistor having a punch-through operation, and is formed to select a pixel by a logic function controlled by an address signal applied to the gate and drain of the logic element,
A solid-state imaging device characterized in that it is configured to read the current of the photodiode or phototransistor at the time of the reset. 2. The solid-state imaging device according to claim 1, wherein the address signal to the gate is applied via a Schottky barrier diode or a PN junction diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56098715A JPS57212878A (en) | 1981-06-25 | 1981-06-25 | Solid-state image pickup device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56098715A JPS57212878A (en) | 1981-06-25 | 1981-06-25 | Solid-state image pickup device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57212878A JPS57212878A (en) | 1982-12-27 |
| JPH026228B2 true JPH026228B2 (en) | 1990-02-08 |
Family
ID=14227210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56098715A Granted JPS57212878A (en) | 1981-06-25 | 1981-06-25 | Solid-state image pickup device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57212878A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6058782A (en) * | 1983-09-09 | 1985-04-04 | Olympus Optical Co Ltd | Solid-state image pickup device |
| JPH01191979A (en) * | 1988-01-27 | 1989-08-02 | Hitachi Ltd | Picture processor |
| US6469289B1 (en) * | 2000-01-21 | 2002-10-22 | Symagery Microsystems Inc. | Ambient light detection technique for an imaging array |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5116966U (en) * | 1974-07-26 | 1976-02-06 |
-
1981
- 1981-06-25 JP JP56098715A patent/JPS57212878A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5116966U (en) * | 1974-07-26 | 1976-02-06 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57212878A (en) | 1982-12-27 |
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