JPH0258594B2 - - Google Patents
Info
- Publication number
- JPH0258594B2 JPH0258594B2 JP56082131A JP8213181A JPH0258594B2 JP H0258594 B2 JPH0258594 B2 JP H0258594B2 JP 56082131 A JP56082131 A JP 56082131A JP 8213181 A JP8213181 A JP 8213181A JP H0258594 B2 JPH0258594 B2 JP H0258594B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- circuit
- test
- signal
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000004044 response Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 102100037460 E3 ubiquitin-protein ligase Topors Human genes 0.000 description 2
- 101000662670 Homo sapiens E3 ubiquitin-protein ligase Topors Proteins 0.000 description 2
- 101000772173 Homo sapiens Tubby-related protein 1 Proteins 0.000 description 1
- 101000610557 Homo sapiens U4/U6 small nuclear ribonucleoprotein Prp31 Proteins 0.000 description 1
- 101150006306 Rhoq gene Proteins 0.000 description 1
- 101000677914 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) 40S ribosomal protein S5 Proteins 0.000 description 1
- 101001109965 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) 60S ribosomal protein L7-A Proteins 0.000 description 1
- 101001109960 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) 60S ribosomal protein L7-B Proteins 0.000 description 1
- 102100029293 Tubby-related protein 1 Human genes 0.000 description 1
- 102100040118 U4/U6 small nuclear ribonucleoprotein Prp31 Human genes 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Description
【発明の詳細な説明】
本発明は集積回路のテスト回路に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuit test circuits.
従来、テスト回路には多くの端子を必要として
いた。第１Ａ図に示す従来例により、従来のテス
ト回路の説明を行う。端子Ｔ１１〜Ｔ１３はテス
ト状態を設定するための端子であり、端子Ｔ１４
はテスト時の入力信号を入力する入力端子であ
る。Rp１１〜Rp１４は、前記端子Ｔ１１〜Ｔ１
４をプルダウンする抵抗である。Ｉ１１〜Ｉ１３
はインバータである。ナンドゲートNA１０〜１
７は、前記端子Ｔ１１〜Ｔ１３の状態により前記
入力端子Ｔ１４の信号を集積回路内の各部へ振り
分けるためのゲートである。Tc１０〜Tc１７は
それぞれナンドゲートNA１０〜NA１７の出力
信号であり前記集積回路の各部のテスト信号とな
る。第１Ｂ図に前記端子Ｔ１１〜Ｔ１３の信号に
より生じるテスト信号を示す。以上のように、前
記集積回路内の８ケ所にテスト信号を送るため
に、テスト状態を設定するための端子が３個、入
力信号を入力するための端子が１個必要であり、
合計４個の端子が必要であつた。 Traditionally, test circuits required many terminals. A conventional test circuit will be explained using a conventional example shown in FIG. 1A. Terminals T11 to T13 are terminals for setting test conditions, and terminal T14
is an input terminal for inputting an input signal during testing. Rp11 to Rp14 are the terminals T11 to T1
This is a resistor that pulls down 4. I11-I13
is an inverter. Nand Gate NA10~1
Reference numeral 7 denotes a gate for distributing the signal of the input terminal T14 to each part in the integrated circuit according to the states of the terminals T11 to T13. Tc10 to Tc17 are output signals of NAND gates NA10 to NA17, respectively, and serve as test signals for each part of the integrated circuit. FIG. 1B shows the test signals generated by the signals at the terminals T11-T13. As described above, in order to send test signals to eight locations within the integrated circuit, three terminals are required to set the test state, and one terminal is required to input the input signal.
A total of four terminals were required.
本発明は上記の欠点を除去するためなされたも
のであり、少ない端子により、より多くのテスト
状態を設定できる回路を提供することを目的とし
たものである。 The present invention was made in order to eliminate the above-mentioned drawbacks, and it is an object of the present invention to provide a circuit that can set more test states with fewer terminals.
本発明の実施例を第２Ａ図および第２Ｂ図に基
づいて説明する。端子Ｔ３１はテスト状態を設定
するための端子であり、Ｔ−タイプフリツプフロ
ツプＦ３１の入力へ接続される。端子Ｔ３２は、
前記端子Ｔ３１と前記フリツプフロツプＦ３１に
よりテスト信号の入力端子、あるいは、集積回路
内の信号の出力端子となる。スイツチSW１は、
前記端子Ｔ３１に接続された信号ａにより制御さ
れ、前記信号ａが“１”のとき導通状態となり、
信号ｂが前記端子３２に出力され、前記信号ａが
“０”のときは、非導通状態となり前記信号ｂは
前記端子Ｔ３２には出力されない。TS１とTS２
は前記集積回路内のテスト時に出力すべき信号で
あり、前記フリツプ・フロツプＦ３１の出力が、
“０”のとき、前記信号TS１が、“１”のときは
前記信号TS２がアンドオアゲートＡ３１を通
り前記信号ｂとなる。ナンドゲートNA３０と
NA３１は、前記端子Ｔ３１が“０”となり、前
記端子Ｔ３２が入力端子として設定されたとき前
記端子３２の入力信号を前記集積回路内の各部へ
テスト信号として振り分けるためのゲートであ
る。TC３０とTC３１は前記ナンドゲートNA３
０と３１の出力信号である。Ｉ３１，３２はイン
バータ。RP３１，３２はそれぞれ前記端子Ｔ３
１，３２のプルダウン抵抗である。第２Ｂ図に前
記端子Ｔ３１とフリツプ・フロツプＦ３１の内容
により、前記端子Ｔ３２が入力端子として機能す
るか、出力端子として機能するか、又、前記端子
Ｔ３２が入力端子として機能した場合の前記集積
回路内に生じるテスト信号、又、前記端子Ｔ３２
が出力端子と機能した場合の出力信号を示す。 An embodiment of the present invention will be described based on FIGS. 2A and 2B. Terminal T31 is a terminal for setting a test state, and is connected to the input of T-type flip-flop F31. Terminal T32 is
The terminal T31 and the flip-flop F31 serve as an input terminal for test signals or an output terminal for signals within the integrated circuit. Switch SW1 is
It is controlled by a signal a connected to the terminal T31, and becomes conductive when the signal a is "1",
When the signal b is output to the terminal 32 and the signal a is "0", a non-conducting state is established and the signal b is not output to the terminal T32. TS1 and TS2
is a signal to be output when testing the integrated circuit, and the output of the flip-flop F31 is
When the signal TS1 is "0", the signal TS2 passes through the AND-OR gate A31 and becomes the signal b when it is "1". Nand Gate NA30
NA31 is a gate for distributing the input signal of the terminal 32 as a test signal to each part in the integrated circuit when the terminal T31 becomes "0" and the terminal T32 is set as an input terminal. TC30 and TC31 are the NAND gate NA3
0 and 31 output signals. I31 and 32 are inverters. RP31 and RP32 are respectively connected to the terminal T3.
This is a 1.32 pull-down resistor. FIG. 2B shows whether the terminal T32 functions as an input terminal or an output terminal depending on the contents of the terminal T31 and the flip-flop F31, and the integrated circuit when the terminal T32 functions as an input terminal. Also, the test signal generated within the terminal T32
shows the output signal when it functions as an output terminal.
以上のように、本発明は、外部から信号を入力
する第１の入力端子への入力信号に応答して記憶
内容が変化するテスト状態記憶回路と、テスト状
態記憶回路の記憶内容に応じてテスト信号を選択
するテスト信号選択回路と、テスト状態記憶回路
の記憶内容に応じて出力信号を選択する出力信号
選択回路と、第１の入力端子に入力される入力信
号に応じて制御されるスイツチ回路を有する構成
とすることにより、少ない入力端子の数で多くの
テスト状態をもつことが可能となる。 As described above, the present invention provides a test state memory circuit whose memory content changes in response to an input signal to a first input terminal that inputs a signal from the outside, and a test state memory circuit that changes memory content in response to an input signal to a first input terminal that inputs a signal from the outside. A test signal selection circuit that selects a signal, an output signal selection circuit that selects an output signal according to the memory contents of a test state storage circuit, and a switch circuit that is controlled according to an input signal input to a first input terminal. By adopting a configuration having the following, it is possible to have a large number of test states with a small number of input terminals.
さらに、上記のスイツチ回路の動作により第２
の入力端子に集積回路内部の出力信号を出力する
ことが可能となるので、１つの端子を入力および
出力と切り換えて使用でき、集積回路の端子数の
削減が可能となり、集積回路の小型化やこれを用
いる機器全体の小型化に結びつくという効果があ
る。 Furthermore, due to the operation of the switch circuit described above, the second
Since it is possible to output the output signal inside the integrated circuit to the input terminal of the integrated circuit, one terminal can be used for switching between input and output, making it possible to reduce the number of terminals on the integrated circuit, and making it possible to miniaturize the integrated circuit. This has the effect of reducing the size of the entire device that uses it.
第１Ａ図は従来のテスト回路であり、第１Ｂ図
は第１Ａ図回路の入出力関係を示す図である。第
２Ａ図は本発明によるテスト回路の実施例を示す
回路図、第２Ｂ図は本発明によるテスト回路の入
出力関係を示す説明図である。
Ｔ１１〜Ｔ１４，Ｔ３１，Ｔ３２……集積回路
の端子、NA１０〜NA１７，NA３０，NA３１
……ナンドゲート、Ｉ１１〜Ｉ１３，Ｉ３１，Ｉ
３２……インバータ、AO３１……アンドオアゲ
ート、RP１１〜RP１４，RP３１，RP３２……
プルダウン抵抗、Ｆ３１……Ｔ−タイプフリツプ
フロツプ、SW１……半導体スイツチ。
FIG. 1A shows a conventional test circuit, and FIG. 1B is a diagram showing the input/output relationship of the circuit shown in FIG. 1A. FIG. 2A is a circuit diagram showing an embodiment of the test circuit according to the present invention, and FIG. 2B is an explanatory diagram showing the input/output relationship of the test circuit according to the present invention. T11-T14, T31, T32...Terminals of integrated circuit, NA10-NA17, NA30, NA31
...Nand Gate, I11-I13, I31, I
32...Inverter, AO31...And-or gate, RP11 to RP14, RP31, RP32...
Pull-down resistor, F31...T-type flip-flop, SW1...semiconductor switch.
Claims (1)
する集積回路のテスト回路において、 前記複数の入力端子のうちの第１の入力端子か
ら順次入力される入力信号に応答して記憶内容が
変化するテスト状態記憶回路と、 前記テスト状態記憶回路の記憶内容に応じてテ
スト信号を選択するテスト信号選択回路と、 前記テスト状態記憶回路の記憶内容に応じて出
力信号を選択する出力信号選択回路と、 前記第１の入力端子に入力される入力信号に応
じて制御されるスイツチ回路を有し、 前記複数の入力端子のうちの第２の入力端子に
集積回路内部の出力信号を出力することを特徴と
する集積回路のテスト回路。[Scope of Claims] 1. In a test circuit for an integrated circuit having a plurality of input terminals for inputting signals from the outside, in response to input signals sequentially input from a first input terminal among the plurality of input terminals. A test state memory circuit whose memory contents change; a test signal selection circuit which selects a test signal according to the memory contents of the test state memory circuit; and an output that selects an output signal according to the memory contents of the test state memory circuit. It has a signal selection circuit and a switch circuit controlled according to an input signal input to the first input terminal, and an output signal inside the integrated circuit is input to a second input terminal of the plurality of input terminals. An integrated circuit test circuit characterized by outputting an output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56082131A JPS57197480A (en) | 1981-05-29 | 1981-05-29 | Test circuit for integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56082131A JPS57197480A (en) | 1981-05-29 | 1981-05-29 | Test circuit for integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57197480A JPS57197480A (en) | 1982-12-03 |
| JPH0258594B2 true JPH0258594B2 (en) | 1990-12-10 |
Family
ID=13765852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56082131A Granted JPS57197480A (en) | 1981-05-29 | 1981-05-29 | Test circuit for integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57197480A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59188572A (en) * | 1983-04-11 | 1984-10-25 | Seiko Epson Corp | Semiconductor testing circuit |
| JPH0733179Y2 (en) * | 1985-01-18 | 1995-07-31 | 日本電気株式会社 | Reset circuit for digital circuit test |
| KR910006241B1 (en) * | 1988-12-14 | 1991-08-17 | 삼성전자 주식회사 | Mode select circuit test |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5268375A (en) * | 1975-12-05 | 1977-06-07 | Nec Corp | Integrated circuit unit |
-
1981
- 1981-05-29 JP JP56082131A patent/JPS57197480A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5268375A (en) * | 1975-12-05 | 1977-06-07 | Nec Corp | Integrated circuit unit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57197480A (en) | 1982-12-03 |
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