JPH025533A - Junction field-effect transistor and its manufacture - Google Patents
Junction field-effect transistor and its manufactureInfo
- Publication number
- JPH025533A JPH025533A JP15729388A JP15729388A JPH025533A JP H025533 A JPH025533 A JP H025533A JP 15729388 A JP15729388 A JP 15729388A JP 15729388 A JP15729388 A JP 15729388A JP H025533 A JPH025533 A JP H025533A
- Authority
- JP
- Japan
- Prior art keywords
- channel layer
- conductivity type
- channel
- region
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 238000000034 method Methods 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000000969 carrier Substances 0.000 claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 15
- 238000010884 ion-beam technique Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 8
- 230000000694 effects Effects 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 4
- 230000005684 electric field Effects 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 27
- 229910045601 alloy Inorganic materials 0.000 abstract description 12
- 239000000956 alloy Substances 0.000 abstract description 12
- 108091006146 Channels Proteins 0.000 description 78
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 24
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 8
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 5
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- 238000005275 alloying Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000006023 eutectic alloy Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は接合型電界効果トランジスタ及びその製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a junction field effect transistor and a method for manufacturing the same.
半導体デバイスの中でも化合物半導体、とりわけ砒化ガ
リウム（以下ＧａＡｓと記す）を利用した超高速ＬＳＩ
及びＩＣの開発は近年目覚しいものがあり、実用化のレ
ベルに近づきつつある。この化合物半導体超高速ＬＳＩ
及びＩＣに用いられている基本構成要素である電界効果
トランジスタ（以下ＦＥＴと記す）には、ＧａＡｓを直
接利用したものとして、金属・半導体接触ＦＥＴ （以
下ＭＥＳＦＥＴと記す）および接合型ＦＥＴ（以下Ｊ−
ＦＥＴと記す）などがある。前者のＭＥＳＦＥＴでは、
その性能を左右する相互コンダクタンスｇｍ向上の為に
は薄い高濃度のチャネルが必要どなるが、この際、ゲー
ト耐圧の劣化が大きな障害となる事が知られている。こ
れに対し、後者のＪ−ＦＥＴではゲート耐圧の点では有
利であるが、熱的安定性やゲート長の微細化の点でＭＥ
ＳＦＥＴに比べて問題があった。Among semiconductor devices, ultrahigh-speed LSIs that use compound semiconductors, especially gallium arsenide (hereinafter referred to as GaAs)
The development of ICs and ICs has been remarkable in recent years, and they are approaching the level of practical application. This compound semiconductor ultra-high-speed LSI
Field-effect transistors (hereinafter referred to as FETs), which are basic components used in ICs, include metal-semiconductor contact FETs (hereinafter referred to as MESFETs) and junction FETs (hereinafter referred to as JFETs), which directly utilize GaAs. −
FET), etc. In the former MESFET,
In order to improve the mutual conductance gm, which affects the performance, a thin, highly doped channel is required, but it is known that deterioration of the gate breakdown voltage is a major obstacle in this case. On the other hand, the latter type of J-FET has an advantage in terms of gate breakdown voltage, but it is not suitable for ME in terms of thermal stability and miniaturization of gate length.
There were problems compared to SFET.
又、これらのＧａＡｓを直接利用したＦＥＴの他に、砒
化アルミニウムガリウム（以下入ｌｉ ＧａＡｓと記す
）とＧａＡｓといったような異なる組成の半導体のへテ
ロ界面に生じる二次元電子ガスを利用しなＦＥＴも、そ
の極めて大きな移動度を利点として近年開発が急がれて
いるが、この二次元電子ガスＦＥＴにおいては、実効的
に利用できる担体の数が少なく、これを増加させようと
すると二次元電子ガス以外に電流の流れる通路が発生し
てｇｍの低下を引起す事が知られている。In addition to these FETs that directly utilize GaAs, there are also FETs that utilize two-dimensional electron gas generated at the hetero-interface of semiconductors with different compositions, such as aluminum gallium arsenide (hereinafter referred to as GaAs) and GaAs. , which has been rapidly developed in recent years to take advantage of its extremely high mobility.However, in this two-dimensional electron gas FET, the number of carriers that can be effectively used is small, and if an attempt is made to increase the number of carriers, two-dimensional electron gas In addition, it is known that a path through which current flows occurs, causing a decrease in gm.
最近の研究開発の動向としては、これらのＦＥＴの欠点
を克服し得る構造の新たなＦＥＴが数多く提案されてき
ている。As a recent trend in research and development, many new FETs with structures that can overcome the drawbacks of these FETs have been proposed.
Ｆ Ｅ Ｔの最も重要な特性は、周知のように、いかに
微弱なグーＩ−電圧の変化によって大きな電流を制御す
るかという点であり１、デバイスバラ、メータどしては
既１．こ述べてきフＱ ｇ ｍによって表わす事ができ
る。上述してき１．： Ｆ Ｅ Ｔはいずれの場合にも
グー・ト電圧の印加で形成さノする空乏層の拡がりによ
ってキャリアの流れを制御する構造となっているが、こ
の空乏層の拡がりはグーｌ−から導電層へ向かう一次元
的な方向のみで制御となっている。従って、さらに−層
効率良くキャリアの流れを制御する為には、空乏層の拡
がりを単にゲート・から導電層に向かう一次元的な方向
のみでなく、この方向とキャリアの流ｈ−る方向の両方
に垂直な方向でも生じるようにし、二次元的にキャリア
の流れを制御せしめられれば、デバイス特性、特にｇｍ
を飛躍的に向上し得る事が予想さｉｌ−る。As is well known, the most important characteristic of FET is how a large current can be controlled by a very weak change in I-voltage. This statement can be expressed by fQ g m. As mentioned above, 1. : In either case, the FET has a structure in which the flow of carriers is controlled by the expansion of a depletion layer formed by the application of a Gut voltage. It is controlled only in one-dimensional direction toward the layer. Therefore, in order to control the flow of carriers even more efficiently, it is necessary to control the expansion of the depletion layer not only in one-dimensional direction from the gate to the conductive layer, but also in the direction of this direction and the direction of carrier flow. If the carrier flow can be controlled two-dimensionally by making it occur in a direction perpendicular to both directions, device characteristics, especially gm
It is expected that this can be dramatically improved.
本発明の目的は、ソースからドＩ／インへ向かうキャリ
アの流れを制御する空乏層を、キャリアの走行方向に対
し垂直な平面で見た場合に、キャリアの流れるチャネル
層を完全に取囲む周囲から二次元的に拡がるようにし、
キャリアの流ズ上を制御する効率を高めた接合型電界効
果トランジスタ及びその製造方法を提供することにある
。An object of the present invention is to provide a depletion layer that controls the flow of carriers from the source to the doin/in, with a periphery that completely surrounds the channel layer through which carriers flow, when viewed in a plane perpendicular to the carrier traveling direction. Let it expand two-dimensionally from
An object of the present invention is to provide a junction field effect transistor with improved efficiency in controlling carrier flow and a method for manufacturing the same.
」二足目的を達成するなめに、本発明の接合型電界効果
トランジスタは、一導電型チャネル層と、該チャネル層
を挾み込むように、基板側と表面側の上下方向に配置さ
れた該チャネル、層と反対導電型の領域とを有１−５該
チャネル層を貫通し、両側に配置されｔ：該反対導電型
領域を接続するように形成され、ソース電極からド】ツ
イン電極へ電子の流れる方向と」−下方向の双方に対し
、垂直となる方向に並べられノ；二複数の該チャネル層
と反対導電型の島状領域をゲートとする事を特徴とする
。In order to achieve the two objectives, the junction field effect transistor of the present invention includes a channel layer of one conductivity type, and a channel layer disposed vertically on the substrate side and the front side so as to sandwich the channel layer. A channel, having a layer and a region of opposite conductivity type, passes through the channel layer and is disposed on both sides, and is formed to connect the opposite conductivity type regions, and conducts electrons from the source electrode to the twin electrode. The channel layer is characterized in that a plurality of island-like regions of opposite conductivity type to the channel layer are arranged in a direction perpendicular to both the flowing direction and the downward direction.
上記の一導電型のチャネル層を挟み込むように基板側と
表面側の上下方向に配置された該チャネル層と反対導電
型の領域とソース電極からドレイン電極へ電子の流れる
方向と上下方向の双方に対し、垂直となる方向に並べら
れた複数の該チャネル層ど反対導電型の島状領域の両方
、又はと゛ちらか一方が該チャネル層より大きなバ〉・
ドギャップの半導体で構成さｉする事が効果的である。Regions of the opposite conductivity type to the channel layer, which are arranged vertically on the substrate side and the front side so as to sandwich the channel layer of one conductivity type, and both in the direction in which electrons flow from the source electrode to the drain electrode and in the vertical direction. On the other hand, both or one of the plurality of island-like regions of the opposite conductivity type arranged in the vertical direction of the channel layer has a larger conductivity than the channel layer.
It is effective to use a double-gap semiconductor.
ま／、コ、上記の接合型電界効果トランジスタを発展さ
ｔ′Ｊ：、一導電型のチャネル層と該チャネル層を上下
方向より挟み込む該チャネル層と反対導電型領域とが＋
、上下方向複数層配置され、該チャネル層と反：対導電
型の島状領域がこれらの複数の反対導電型頭ｊ或を接続
するように形成されると効果的である。The above junction field effect transistor is developed by forming a channel layer of one conductivity type and a region of the opposite conductivity type sandwiching the channel layer from above and below.
It is effective if a plurality of layers are arranged in the vertical direction, and island-like regions of opposite conductivity type to the channel layer are formed so as to connect these plurality of opposite conductivity types.
さらに、一導電型チャネル層に対し、ソース電極及びド
レイン電極から良好なオーミックコンタク１゜かどね、
該チャネルを挟む反対導電型領域のキャリアがこれらの
電極に流れ込む事を団止し得る高濃度のチャネル層と同
一導電型層がソース電極及びドレイン電極の基板側に設
けるとよい。Furthermore, if there is good ohmic contact of 1° from the source electrode and drain electrode to the channel layer of one conductivity type,
It is preferable to provide a highly concentrated layer of the same conductivity type as the channel layer on the substrate side of the source electrode and the drain electrode, which can prevent carriers of opposite conductivity type regions sandwiching the channel from flowing into these electrodes.
次に、本発明の接合型電界効果トランジスタの製造方法
は、上記のグー１−となる島状領域をイオン注入によっ
て形成する事を特徴とする。Next, the method for manufacturing a junction field effect transistor according to the present invention is characterized in that the island-like region serving as the goo 1- is formed by ion implantation.
この際、イオン注入に集束イオンビームを用いると効果
的である。At this time, it is effective to use a focused ion beam for ion implantation.
また、ソース電極、ドレイン電極の基板側に設けられる
チャネル層ど同−導′韮型高濃度領域をイオン注入によ
って形成しても良い。Alternatively, a conductive, rectangular high concentration region may be formed in the channel layer provided on the substrate side of the source electrode and the drain electrode by ion implantation.
この際、イオン注入に集束イオンビームを用いると効果
的である。At this time, it is effective to use a focused ion beam for ion implantation.
以上のイオン注入を用いる製造方法におい°Ｃは、イオ
ン注入後に、短時間アニールプロセスを含む事が効果的
である。In the above manufacturing method using ion implantation, it is effective to include a short-time annealing process after the ion implantation.
さらに、本発明の接合型電界効果１−ランジスタの異な
る製造方法は、上記のグー）・となる島状領域を選択エ
ツチングと選択エピタキシャル法とによって形成する事
を特徴どする６
また、ソース電極１ ドレイン電極の基板側に設けられ
るチャネル層と同−漕、電型高濃度領域を選択エツチン
グとｉ片択エピタキシャル法によって形成しても効果的
である。Furthermore, a different manufacturing method of the junction field effect transistor of the present invention is characterized in that the island-shaped region having the above-mentioned shape is formed by selective etching and selective epitaxial method6. It is also effective to form the high concentration region of the electric type by selective etching and selective epitaxial method at the same time as the channel layer provided on the substrate side of the drain electrode.
最近、ｌ／ンシュらはアイ・イーイーイー・エレクトロ
ン・デバイシズ（ＩＥＥＩＥ ＥＩｅｅｔ、ｒｏｎ Ｄ
ｅｖｉｃｅｓ）ＥＤ−３４巻、２２３２頁、１９８７年
に半絶縁性ＧａＡｓ中にシリコンの集束イオンビームで
線状の導電層を形成した実験例とシミュレーションを報
告している。通常のＧａＡｓのＭＥＳＦＥＴに比べ、空
乏層が導電層領域の周囲から効果的に拡がる傾向がある
事をシミュレーションで示し、実際に作製したデバイス
でもその特性が向上する事を実証している。しかしなが
ら、彼らのＦＥＴの構造は半絶縁層の中に埋込まれた線
状の導電層を基板表面のショットキー電極で制御する構
造となっており、空乏層の二次元的な拡がりについてい
えば不完全である。Recently, IEEIE Electron Devices (IEEIE EIeet, ron D
In 1987, he reported an experimental example and simulation in which a linear conductive layer was formed in semi-insulating GaAs using a focused silicon ion beam. Compared to ordinary GaAs MESFETs, simulations have shown that the depletion layer tends to spread effectively from the periphery of the conductive layer region, and it has been demonstrated that the characteristics of the actually fabricated device are improved. However, the structure of their FET is such that a linear conductive layer embedded in a semi-insulating layer is controlled by a Schottky electrode on the substrate surface, and the two-dimensional expansion of the depletion layer is It is incomplete.
本発明によるＦＥＴのチャネルは、その構造の構成上、
表面側及び基板側の両側を該チャネルと反対導電型領域
で挟まれており、さらにこの方向と垂直な方向において
も一つのチャネルの両側にこのチャネルと反対導電型領
域を配置している。Due to its structure, the channel of the FET according to the present invention has the following characteristics:
The channel is sandwiched by regions of the opposite conductivity type on both sides of the front surface and the substrate, and furthermore, regions of the conductivity type opposite to the channel are arranged on both sides of one channel in a direction perpendicular to this direction.
このため、チャネルとしては線状のものが形成され、そ
の周囲を該チャネルと反対導電型の領域が取巻くように
ゲートとして配置される事になる。Therefore, a linear channel is formed, and a gate is arranged so that a region having a conductivity type opposite to that of the channel surrounds the channel.
このような構造のＦＥＴにおいては、チャネルを制御す
る空乏層の拡がりが完全に二次元的である為に、従来型
のＦＥＴと比べて、極めて効率が良くなる。さらに、こ
のチャネルを取巻く該チャネルと反対導電型の領域が、
該チャネルを構成る半導体よりも電子親和力が小さな半
導体で構成されている場合には、チャネルに対してポテ
ンシャルのバリアによる閉じ込め効果も加わるので、チ
ャネルの制御性はさらに効果的になる。又、このチャネ
ルを多層にする事により、制御可能な電流量を増加し得
る。さらに、ソース電極及びドレイン電極の基板側に設
けられた高濃度のチャネル層と同一導電型層により、チ
ャネル層を挟む反対導電型領域を介してチャネル層と反
対導電型のキャリアがソース・ドレイン間に漏れる事を
有効に阻止し得る。In an FET with such a structure, the depletion layer that controls the channel extends completely two-dimensionally, so the efficiency is extremely improved compared to a conventional FET. Furthermore, a region surrounding this channel and having a conductivity type opposite to that of the channel is
If the channel is made of a semiconductor having a smaller electron affinity than the semiconductor forming the channel, a confinement effect due to a potential barrier is added to the channel, so that controllability of the channel becomes even more effective. Furthermore, by forming this channel into multiple layers, the amount of current that can be controlled can be increased. Furthermore, due to the highly concentrated layer of the same conductivity type as the channel layer provided on the substrate side of the source and drain electrodes, carriers of the opposite conductivity type to the channel layer are transported between the source and drain via the opposite conductivity type region sandwiching the channel layer. This can effectively prevent leakage.
さらに、また本発明のＦＥＴを実現する製造方法として
、チャネルと反対導電型のゲートとなる島領域あるいは
ソース電極及びドレイン電極の基板側に設けられるチャ
ネルと同一導電型の高濃度層を形成するに当たり、イオ
ン注入法を用いる製造方法は、本発明の構造のＦＥＴを
実現する。簡便で、スループットの高い方法である。特
に、イオン注入法として集束イオンビームを用いる事に
より、マスクなしで注入を行う事ができるばかりでなく
、上記のチャネルと反対導電型の島状ゲート領域とチャ
ネルと同一導電型の高濃度層を一つのプロセスで形成す
る事が可能となり、工程の簡素化の点で極めて有利であ
る。Furthermore, as a manufacturing method for realizing the FET of the present invention, in forming a highly doped layer of the same conductivity type as the channel, which is provided on the substrate side of the source and drain electrodes or an island region serving as the gate of the opposite conductivity type to the channel. , a manufacturing method using an ion implantation method realizes an FET having the structure of the present invention. This is a simple and high-throughput method. In particular, by using a focused ion beam as the ion implantation method, it is not only possible to perform implantation without a mask, but also to form an island-like gate region of the opposite conductivity type to the channel and a high concentration layer of the same conductivity type as the channel. It can be formed in one process, which is extremely advantageous in terms of process simplification.
又、イオン注入を行なった場合、注入イオンの活性化の
為にアニール工程が必要となるが、このアニール工程に
短時間アニール法を用いる事により、本発明の構造のＦ
ＥＴにおけるチャネルとこれを挟む該チャネルと反対導
電型の領域との界面急峻性を損なう事なく又、注入イオ
ンが大きな熱拡散する事なく、注入イオンの活性化が実
現でき、デバイス特性の向上に有用である。Furthermore, when ion implantation is performed, an annealing process is required to activate the implanted ions, but by using a short-time annealing method for this annealing process, the F of the structure of the present invention can be improved.
The implanted ions can be activated without impairing the steepness of the interface between the channel in ET and the regions of the opposite conductivity type sandwiching the channel, and without significant thermal diffusion of the implanted ions, improving device characteristics. Useful.
又、上記の島状ゲート領域、およびソース電極とドレイ
ン電極の基板側に設ける高濃度層を選択エイッチングと
選択エピタキシャル法によって本発明の構造のＦＥＴを
実現する製造方法は、製造工程の簡素化という観点から
はイオン注入法には及ばないものの、イオン注入法に比
べ、島状ゲート領域の微細性、チャネルと島状ゲート領
域との界面の急峻性を向上させる事が可能であり、又、
ソース電極とドレイン電極の基板側に設ける高濃度領域
も島状ゲート領域により近接させて形成する事が可能と
なり、デバイス性能の向上が可能となる。Furthermore, the manufacturing method for realizing the FET having the structure of the present invention by selective etching and selective epitaxial method of the above-mentioned island-shaped gate region and the high concentration layer provided on the substrate side of the source and drain electrodes has the advantage of simplifying the manufacturing process. Although it is not as good as ion implantation from a viewpoint, compared to ion implantation, it is possible to improve the fineness of the island-shaped gate region and the steepness of the interface between the channel and the island-shaped gate region, and
The high concentration regions provided on the substrate side of the source and drain electrodes can also be formed closer to the island-shaped gate regions, making it possible to improve device performance.
次に、本発明の実施例について図面を参照して説明する
。第１図は本発明の四つの実施例のＦＥＴに共通する平
面図である。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view common to FETs of four embodiments of the present invention.
〔実施例１〕
第２図（ａ）、（ｂ）は本発明の第１の実施例の断面図
であり、第１図のＡ−Ａ’線及びＢ−Ｂ′線断面図であ
る。[Embodiment 1] FIGS. 2(a) and 2(b) are sectional views of a first embodiment of the present invention, and are sectional views taken along the lines AA' and BB' in FIG.
本実施例の接合型ＦＥＴは、高抵抗のＧａＡｓエピタキ
シャル基板１上に順次積層されるチャネルと反対導電型
の第１のＧａＡｓ又はｋｅ ｘＧａｔ−ｘＡｓ領域２ａ
、チャネル層３、チャネルと反対導′々；型の第２のＧ
ａＡｓ又はＡｊ？ ｘＧａｌ−、Ａｓ領域２ｂとチャネ
ルと反対導電型領域２ａ、２ｂと共にチャネルを流れる
キャリアを制御する、チャネルと反対導電型の複数の島
状領域４と、ター１−．ソースおよびドレインの各電極
６，７．Ｓと、各々のアロイ領域５．９．１０とを含ん
で構成されている。The junction FET of this example has a first GaAs or ke x Gat-x As region 2a of a conductivity type opposite to that of the channel, which is sequentially laminated on a high-resistance GaAs epitaxial substrate 1.
, channel layer 3, channel and opposite conductors; second G of type
aAs or Aj? xGal-, As region 2b, and regions 2a and 2b of conductivity type opposite to the channel, a plurality of island regions 4 of conductivity type opposite to that of the channel, which control carriers flowing through the channel, and Tar1-. Source and drain electrodes 6, 7. S and each alloy region 5.9.10.
かかる構造の接合型ＦＥＴは次の手法で容易に製造する
事ができる。ここでは簡歩のため、１’）型チャネル層
をもつＦＥＴについて詳細に説明する。A junction FET having such a structure can be easily manufactured by the following method. Here, for the sake of brevity, a FET having a type 1' channel layer will be explained in detail.
半絶縁性ＧａＡｓ−１−にバッファ層を１μｍ堆積した
ＧａＡｓエピタキシャル基板１上に、濃度２Ｘ１０１８
／ｃｍ３、厚さｌｏｏｎｍのｐ型ＧａＡｓ層２ａ、濃度
１ Ｘ １０ ”／ ｃｍ’ 、厚さ７０ｎｍのｎ型チ
ャネル層３、再び同一条件のｐ型ＧａＡｓＪ１２ ｂを
ＭＢＥ法により堆積する。これらのエピタキシャル層の
堆積は有機金属を用いたＣＶＤ法（ＭＯＣＶＤ法）を用
いてもよい。On a GaAs epitaxial substrate 1 on which a 1 μm thick buffer layer was deposited on semi-insulating GaAs-1-, a concentration of 2×1018
/cm3, a p-type GaAs layer 2a with a thickness of loonm, an n-type channel layer 3 with a concentration of 1 x 10''/cm' and a thickness of 70 nm, and a p-type GaAs J12b under the same conditions again by the MBE method. The layer may be deposited using a CVD method using an organic metal (MOCVD method).
又、ｐ型Ｊｔａ２ａ、、２ｂに電子親、和力の小さな生
導体、例えばＡｇ ｘＧａｌ−ＸＡＳを用いる事により
、チャネル層３へのキャリアの閉じ込めがより強くなり
、本発明の効果は増大する。この際、保ＡＭとして最上
層にｐ型ＧａＡｓＪｌを堆積するとよい。ｐ型層堆積の
条件は同一で行なう。各層の堆積終了後、第１図に示す
島状領域４を形成するために、Ｂｅ＋を集束イオンビー
ムにより１００ｋｅＶ、ｌｘｌ、 ０ ”／ ｃｓ ２
の条件で、第２図に示した様に、基板側のｐ型層までを
貫通ずるように注入し、この後、７００ｎｍの厚さのＳ
ｉ３Ｎ４膜を表面に被着後２９００℃、２秒の短時間ラ
ンプアニールを行なう。この短時間アニールは作用の項
でも述べたように、チャネルＭ３と、＝れを挟むρ壁領
域２ａ、２ｂとの界面急峻性を損なわないようにづ゛る
為と、注入したＢｅ＋拡散を制御する為である。Further, by using a raw conductor with electron affinity and small sum force, such as Ag x Gal-XAS, for the p-type Jta 2a, 2b, carrier confinement in the channel layer 3 becomes stronger, and the effects of the present invention are enhanced. At this time, it is preferable to deposit p-type GaAsJl on the top layer as an AM protection layer. The p-type layer was deposited under the same conditions. After the deposition of each layer, Be+ was irradiated with a focused ion beam at 100 keV, lxl, 0''/cs 2 in order to form the island region 4 shown in FIG.
Under these conditions, as shown in Figure 2, implantation was performed so as to penetrate through to the p-type layer on the substrate side, and then a 700 nm thick S layer was implanted.
After depositing the i3N4 film on the surface, lamp annealing is performed for a short time at 2900° C. for 2 seconds. As mentioned in the operation section, this short-time annealing is performed in order not to impair the steepness of the interface between the channel M3 and the ρ wall regions 2a and 2b that sandwich it, and to control the diffusion of the implanted Be+. It is for the purpose of
本実施例では、イオン注入に集束イオンビームを用いた
が、当然の事ながら、通常のイオン注入法を用いてもよ
い。その際、選択注入を行なう為にマスクの形成が必要
Ｇこなるのは言−）までもない。In this embodiment, a focused ion beam was used for ion implantation, but it goes without saying that a normal ion implantation method may be used. Needless to say, it is necessary to form a mask in order to perform selective implantation.
又、ｐ型層形成のためのイオン種としてＢｅ’を用いて
いるが、Ｍｇ 、 Ｚｎなどを用いてもよい。Furthermore, although Be' is used as the ion species for forming the p-type layer, Mg, Zn, etc. may also be used.
以上の注入イオンの活性化の後、被着したＳｉ３Ｎ、４
膜を除去し、第１図に示すソース・ドレイン領域にｎ型
のオーミック金属Ｎｔ／ＡｕＧｅを２００ｎｍの厚さに
被着し、４５０°Ｃにスパイクアロイ化処理を行ない、
ｎ型チャネルとのオーミック接触を取り、次に、第１図
に示したゲート電極領域にｐ型のオーミック金属である
Ａｕ２ｎを７００ｎｍの厚さに被着（−１４２０℃のス
パイクアロイ化処理を行ない、第２図（ａ、）、（ｂ）
に示１−たような表面の１］型層２ ｂのみに対してオ
ーミック接触をとる。After the above activation of the implanted ions, the deposited Si3N,4
The film was removed, and an n-type ohmic metal Nt/AuGe was deposited to a thickness of 200 nm on the source/drain regions shown in FIG. 1, and spike alloying was performed at 450°C.
After making ohmic contact with the n-type channel, next, Au2n, which is a p-type ohmic metal, is deposited to a thickness of 700 nm on the gate electrode region shown in Fig. 1 (spike alloying treatment is performed at -1420°C). , Figure 2 (a,), (b)
Ohmic contact is made only with the 1] type layer 2b on the surface as shown in 1-.
最後に、電極取出し用のパッドをＡ ｕ ／ Ｔ ｉで
形成ｊ２て本実施例の接合型のＦＥＴが完成する。Finally, a pad for taking out the electrode is formed using A u /Ti j2 to complete the junction type FET of this example.
１：の島状領域４の形成方法としで、イオン注入法の他
に選択エツチング、選択エピタキシャル成長による方法
もあり、この方法でもＦＥＴを試作した。この島状領域
４以外は全く同じプロセスである。チャネル層３とこれ
を挟むｐ型層２ａ。In addition to the ion implantation method, selective etching and selective epitaxial growth are also available as a method for forming the island-like region 4 in Example 1. FETs were also prototyped using these methods. The process is exactly the same except for this island-like region 4. A channel layer 3 and a p-type layer 2a sandwiching the channel layer 3.
２ｂを形成した後、ＳｉＯ□膜を被着し、レジスＩ・を
マスクに島状領域４に対し、ＣＦ４を用いた反応性イオ
ンエツチング（以下ＲＩＥと記す）で窓あけを行う。こ
の際のレジスト露光には電子ビームを用いた。この後、
５ｉ０２をマスクに、第２図に示したように、ＧａＡｓ
をＲＩＥで工・ソチングし、さ八に、この５ｉ０２をマ
スクとしてエツチングを行なった領域に濃度３ Ｘ １
０ ”／ ｃｍ３のｐ型ＧａＡｓを選択成長して埋込ん
だ。ここで選択成長したのは、１］型のＧａＡｓである
が、ｐ型のＡｅＸＧａｌ−ＸＡｓを用いる事によって、
さらに特性の向トが期待できる５、このプロセスによっ
て、直径的０．２μｍの微小でかつ急峻な界面を有する
島状領域が実現できた。この後のプロセスは上述したイ
オン注入の場合と同様である。After forming 2b, a SiO□ film is deposited, and a window is opened in the island region 4 using the resist I as a mask by reactive ion etching (hereinafter referred to as RIE) using CF4. An electron beam was used for resist exposure at this time. After this,
5i02 as a mask, as shown in Figure 2, GaAs
Then, using this 5i02 as a mask, the etched area was etched with a density of 3 x 1.
0''/cm3 of p-type GaAs was selectively grown and embedded.The selectively grown here was 1]-type GaAs, but by using p-type AeXGal-XAs,
Further improvements in properties can be expected5. Through this process, island-like regions with a diameter of 0.2 μm and having steep interfaces were realized. The subsequent process is similar to the ion implantation described above.
以上、説明したのはｎ型チャネル層を看するＩ’ＥＴの
例であるが、ｐ型チャネル層を有するＦＥＴもほぼ同様
に製造できる。この場合、ｎ型となる島状領域４へは、
例えばＳｉ＋イオンを用いる必要があり、又、ソース電
極７、及びドレイン電極８には＾ｕＺｎを、ゲート電極
６にはＮｉ／ＡｕＧｅを用いる必要がある。What has been described above is an example of an I'ET having an n-type channel layer, but an FET having a p-type channel layer can also be manufactured in substantially the same manner. In this case, to the island-like region 4 which becomes n-type,
For example, it is necessary to use Si+ ions, it is necessary to use ^Zn for the source electrode 7 and the drain electrode 8, and it is necessary to use Ni/AuGe for the gate electrode 6.
〔実施例２〕
第３図（ａ）、（ｂ）は本発明の第２の実施例の断面図
であり、第１図のＡ−Ａ’線及びＢ−Ｂ′線断面図であ
る。[Embodiment 2] FIGS. 3(a) and 3(b) are sectional views of a second embodiment of the present invention, and are sectional views taken along the lines AA' and BB' in FIG.
第２の実施例の接合型ＦＥＴは、高抵抗のＧａＡｓエピ
タキシャル基板１の上に順次積層される一導電型のチャ
ネル層３ａ〜３ｃと、このチャネル層の各層ごとにこれ
を挟むように設けられＧａＡｓまたはｋｅ ｘＧａｌ−
ＸＡｓから成る反対導電型領域２ａ〜２ｄと、この反対
導電型領域２ａ〜２ｄと共にチャネル層を流れるキャリ
アを制御する複数の反対導電型島状領域４と、ゲート、
ソース及びドレインの各電極６，７．８と、各々のアロ
イ領域５゜９．１０とを含んで構成されている。The junction FET of the second embodiment includes channel layers 3a to 3c of one conductivity type that are successively laminated on a high-resistance GaAs epitaxial substrate 1, and each of the channel layers is provided to sandwich the channel layers 3a to 3c. GaAs or ke xGal-
Opposite conductivity type regions 2a to 2d made of XAs, a plurality of opposite conductivity type island regions 4 that control carriers flowing through the channel layer together with the opposite conductivity type regions 2a to 2d, a gate,
It includes source and drain electrodes 6, 7.8, and alloy regions 5.9.10.
このような構造の接合型ＦＥＴは、次の手法で容易に製
造する事ができる。ここでは簡単のため、実施例１と同
様にｎ型チャネル層をもつＦＥＴについて説明する。A junction FET having such a structure can be easily manufactured by the following method. Here, for the sake of simplicity, a FET having an n-type channel layer as in the first embodiment will be described.
半絶縁性ＧａＡｓ基板にバッファ層を１μｍの厚さに堆
積しなＧａＡｓエピタキシャル基板１の上に濃度３ Ｘ
１０１８／ｃｍ３のｐ型ＧａＡｓで厚さ約７０ｎｍの
反対導電型層２ａ〜２ｄと厚さ７０ｎｍのｎ型チャネル
層３ａ〜３ｃとを交互に第３図（ａ）。A buffer layer is deposited to a thickness of 1 μm on a semi-insulating GaAs substrate.
In FIG. 3(a), layers 2a to 2d of opposite conductivity type, each made of p-type GaAs with a density of 1018/cm3, and having a thickness of about 70 nm and n-type channel layers 3a to 3c, each having a thickness of 70 nm, are alternately formed.
（ｂ）に示したように堆積する。第３図では、チャネル
層は３層にとどめているが、さらに多数層を重ねても良
い。またｐ型層にＡｊ’ ＸＧａ１−ＸＡＳ層を用いて
も良いことについては実施例１と同様である。It is deposited as shown in (b). Although the number of channel layers is limited to three in FIG. 3, more layers may be stacked. Further, as in Example 1, the Aj'XGa1-XAS layer may be used as the p-type layer.
各層の堆積終了後、第１図で示された島状領域４を形成
するため、Ｂｅ＋を集束イオンビームにより１５０ ｋ
ｅＶ、Ｉ Ｘ １０ ”／ ｃｍ２の条件で、第３図に
示すように、基板側のｐ型層まで貫通するように注入す
る。この後のプロセスは実施例１と同様であるが、ソー
ス電極、ドレイン電極のアロイ領域９，１０が基板側の
ｐ型層にまで達するようにオーム性金属Ｎｉ／ＡｕＧｅ
を３００ ｎｍの厚さに被着する。After the deposition of each layer, Be+ was heated at 150 k by a focused ion beam to form the island-like regions 4 shown in FIG.
eV, I x 10''/cm2, as shown in Figure 3, the implantation is carried out to penetrate to the p-type layer on the substrate side.The subsequent process is the same as in Example 1, except that the source electrode , ohmic metal Ni/AuGe is formed so that the alloy regions 9 and 10 of the drain electrode reach the p-type layer on the substrate side.
is deposited to a thickness of 300 nm.
本実施例のように、多重にチャネル層を積層した場合に
は、スルーブツトの点を除いて、イオン注入法よりは選
択エツチングと選択エピタキシャルのプロセスの方が微
細性、界面急峻性の点でより有利となる。この方法によ
るＦＥＴも試作した。試作方法は実施例１と同様である
。又、ｐ型チャネル層を有する本実施例のＦＥＴも同様
であり、その際の留意点は実施例１と同様である。When multiple channel layers are laminated as in this example, the selective etching and selective epitaxial processes are better than the ion implantation method in terms of fineness and interface steepness, except for throughput. It will be advantageous. A prototype FET was also manufactured using this method. The trial production method was the same as in Example 1. Further, the FET of this embodiment having a p-type channel layer is also the same, and the points to be noted at that time are the same as those of the first embodiment.
〔実施例３〕
第４図は本発明の第３の実施例の断面図であり、第１図
のＢ−Ｂ’線断面図である。第１図のＡ−Ａ’線断面図
は第２図（ａ）と同じである。[Embodiment 3] FIG. 4 is a sectional view of a third embodiment of the present invention, and is a sectional view taken along the line BB' in FIG. The sectional view taken along the line AA' in FIG. 1 is the same as that in FIG. 2(a).
本実施例の接合型ＦＥＴは、高抵抗のＧａＡｓエピタキ
シャル基板ｌ上に順次積層され、ＧａＡｓ又はｋｅ ｘ
Ｇａｌ−ＸＡｓで作られるチャネル層３と反対導電型領
域チャネル層３と、このチャネル層３反対導電型でのＧ
ａＡｓ又はＡｆｆ ｘＧａｌ−、Ａｓで作られる反対導
電型領域２ａ、２ｂと、この反対導電型領域２ａ、２ｂ
と共にチャネルを流れるキャリアを制御する複数の反対
導電型島状領域４と、ソースおよびドレイン領域の基板
側に形成されるチャネルと同一導電型高濃度層１２と、
ゲート、ソースおよびドレインの各電極６，７．８と各
々のアロイ領域５，９．１０とを含んで構成される。The junction FET of this example is stacked sequentially on a high-resistance GaAs epitaxial substrate l.
Channel layer 3 made of Gal-XAs and opposite conductivity type channel layer 3, and G in the opposite conductivity type of channel layer 3
Opposite conductivity type regions 2a, 2b made of aAs or Aff xGal-, As, and these opposite conductivity type regions 2a, 2b
a plurality of island regions 4 of opposite conductivity type for controlling carriers flowing through the channel; and a high concentration layer 12 of the same conductivity type as the channel formed on the substrate side of the source and drain regions.
It is configured to include gate, source, and drain electrodes 6, 7.8, and alloy regions 5, 9.10, respectively.
このような構造の接合型ＦＥＴは、次の手法で容易に製
造する事ができる。本実施例でも簡単のためｎ型チャネ
ルを有するＦＥＴにつき説明する。ｎ型チャネル層３と
、これを挟むｐ型層２ａ、２ｂの形成、島状領域４の形
成については実施例１と同様である。A junction FET having such a structure can be easily manufactured by the following method. In this embodiment as well, for the sake of simplicity, an FET having an n-type channel will be explained. The formation of the n-type channel layer 3, the p-type layers 2a and 2b sandwiching it, and the formation of the island region 4 are the same as in Example 1.
本実施例では、この後のプロセスとして、オーム性電極
を形成する前に、チャネル層と同一導電型の高濃度層１
２を、第４図に示すように、ソース電極及びドレイン電
極の基板側に設ける事が特長である。In this example, as a subsequent process, a high concentration layer 1 of the same conductivity type as the channel layer is formed before forming the ohmic electrode.
2 is provided on the substrate side of the source electrode and drain electrode, as shown in FIG.
この形成方法として、イオン注入、特にＡｕ−５ｉ−Ｂ
ｅの共晶合金をイオン源とした集束イオンビームによっ
て島状領域４をＢｅ＋で形成するのと同時に、Ｓ ｉ
＋ ４を２６０ ｋｅＶ、Ｉ Ｘ １０１４／ ｃｍ２
の条件ご注入する方法が簡便である。短時間アニールは
このプロセスの後に行なう。この高濃度層１，２がある
ために、オーミック金属を厚く被着して、深くまで合金
化する必要はない。従って、本実施例では、 Ｎｉ／Ａ
ｕＧｅを１． ＯＯｎ ｍの厚さに被着し、４５０℃で
スパイクアロイした６ｐ型層へのオーミック金属は実施
例１と同一である。又、イオン注入ではなく、選択エツ
チング、選択エピタキシャル法を用いる事でもこの高濃
度層１．２を実現する事ができる。濃度１． Ｘ １０
”／ ｃｍ３のＩｎ型層を島状領域４を形成した後に
選択エツチング、選択エピタキシャル法を用いて第４図
に示した様に形成する。具体的なプロセスは実施例１と
同様である。As a method for forming this, ion implantation, especially Au-5i-B
At the same time, the island region 4 is formed of Be+ by a focused ion beam using the eutectic alloy of Si as an ion source.
+4 to 260 keV, I x 1014/cm2
The method of injection is simple. A short anneal follows this process. Because of the presence of the high concentration layers 1 and 2, there is no need to deposit the ohmic metal thickly and alloy it deeply. Therefore, in this example, Ni/A
uGe 1. The ohmic metal to the 6p type layer deposited to a thickness of OOn m and spike-alloyed at 450° C. is the same as in Example 1. Moreover, this high concentration layer 1.2 can also be realized by using selective etching or selective epitaxial method instead of ion implantation. Concentration 1. X 10
After forming the island-like region 4, an In type layer having a thickness of 1 cm3 is formed as shown in FIG. 4 by selective etching and selective epitaxial method.
第４図では、島状領域４と高濃度層］１、離して形成し
であるが、パリスティックな輸送現象を引出せるように
、島状領域４に極めて近接ｌ〜で高濃度層１−２を形成
してもよい。In FIG. 4, the island-like region 4 and the high-concentration layer [1] are formed separately, but in order to bring out the pallitic transport phenomenon, the high-concentration layer 1-1 is formed very close to the island-like region 4. 2 may be formed.
ヌ、ｐ型チャネル層を有する本実力ＩＣ例のＦＥＴも同
様であり、その際の留意点は実施例１と同様である。The same applies to the FET of this practical IC example having a p-type channel layer, and the points to be noted in this case are the same as in the first embodiment.
〔実施例４〕
第５図は本発明の第４の実施例の断面図であり、第１図
のＢ−Ｂ’線断面図である８第１図のＡ−Ａ′線断面図
は第３図（ａ）と同じである。[Embodiment 4] FIG. 5 is a sectional view of a fourth embodiment of the present invention, and is a sectional view taken along the line BB' in FIG. This is the same as in Figure 3(a).
本実施例の接合型ＦＥＴは、高抵抗のＧａＡｓエピタキ
シャル基板１の上に順次積層される複数のチャネル層３
ど、このチャネル層と反対導電型のＧａＡｓ又はＡｇ
ｘＧａｌ−、Ａｓで作られる反対導電型領域２ａ−２４
と、反対導電型領域２８〜２ｄと共にチャネル層を流れ
るキャリアを制御する複数の反対導電型の島状領域４と
、ゲートおよびドレイン領域の基板側に形成されるチャ
ネルと同一導電型高濃度層１］、と、ゲート１ソースお
よびドレインの各電極６，７．８と各々のアロイ領域５
，９゜１．０とを含んで構成される。The junction FET of this embodiment has a plurality of channel layers 3 sequentially stacked on a high-resistance GaAs epitaxial substrate 1.
GaAs or Ag of the opposite conductivity type to this channel layer.
Opposite conductivity type region 2a-24 made of xGal-, As
, a plurality of island-like regions 4 of opposite conductivity type that control carriers flowing through the channel layer together with regions 28 to 2d of opposite conductivity type, and a high concentration layer 1 of the same conductivity type as the channel formed on the substrate side of the gate and drain regions. ], each gate 1 source and drain electrode 6, 7.8, and each alloy region 5
, 9°1.0.
このような構造の接合型ＦＥＴは、次の手法で容易に製
造する事ができる。他の実施例同様、１１型チヤネルを
有するＦＥＴにつき説明する。A junction FET having such a structure can be easily manufactured by the following method. As with the other embodiments, an FET having an 11-type channel will be described.
複数の積層されるｎ型チャネル３とこれを挟むｐ型層２
ａ、２ｂをこれまでの実施例と同じ方法により堆積しｉ
Ｑ後に、Ａｕ−５ｉ−Ｒｅの共晶合金をイオン源とした
集束イオンビームによって島状領域４をＢｅ＋で形成す
るのと同時に、Ｓｉ”＋を３００ｋｅＶ、Ｉ Ｘ １０
１４／ ｃｍ２の条件で注入し、短時間アニールを経て
第５図に示すようなチャネルと同一導電型の高濃度層１
−２を形成する。他に、選択エツチング、選択エピタキ
シャル法によっても形成１−な。深い領域まで均一に高
濃度層】、２を形成するにはこの方法の方が有利である
。又、微細性、Ｗ面急峻性の点でも有利である。具体的
なプロセスは実施例１と同様である。A plurality of laminated n-type channels 3 and a p-type layer 2 sandwiching them
a and 2b were deposited by the same method as in the previous examples.
After Q, the island region 4 is formed with Be+ by a focused ion beam using a eutectic alloy of Au-5i-Re as an ion source, and at the same time, Si"+ is heated at 300 keV and I x 10
After implantation under the condition of 14/cm2 and short-time annealing, a high concentration layer 1 of the same conductivity type as the channel as shown in Fig. 5 is formed.
-2 is formed. In addition, selective etching and selective epitaxial methods may also be used. This method is more advantageous in forming the highly concentrated layer [2] evenly in a deep region. It is also advantageous in terms of fineness and W surface steepness. The specific process is the same as in Example 1.
実施例３と同様に、パリスティックな輸送現象を引出せ
るように、島状領域４に極めて近接して高濃度層１２を
形成してもよい。この後、ゲート、ソース、ドＩ／イン
の各電極の形成方法については実施例３と同一である。As in Example 3, the high concentration layer 12 may be formed very close to the island region 4 so as to bring out the pallitic transport phenomenon. Thereafter, the method of forming the gate, source, and do/in electrodes is the same as in Example 3.
又、ｐ型チャネルを有するＦＥＴについてもこれまでの
実施例と同様である。Further, the FET having a p-type channel is also the same as in the previous embodiments.
これまで述べてきた四つの実施例は化合物半導体を用い
ているが、本発明の接合型電界効果トランジスタは化合
物半導体のみに限られるものではない事は言うまでもな
い。Although the four embodiments described so far use compound semiconductors, it goes without saying that the junction field effect transistor of the present invention is not limited to compound semiconductors.
以上詳細に説明したように、本発明によれば、チャネル
中のキャリアの流れをチャネルの周囲に配した反対導電
型領域から２次元的に拡がる空乏層により効果的に制御
する事ができるので、従来のＦＥＴでは達し得なかった
性能の向上を達成することができる。また、極めて容易
なプロセスでこれを製造することができるので、低雑音
用及びパワー用の単体素子から超高速のデジタルＬ Ｓ
Ｉの基本素子に至るまで広い応用分野に実施する事が
可能である。As explained in detail above, according to the present invention, the flow of carriers in the channel can be effectively controlled by the depletion layer that extends two-dimensionally from the opposite conductivity type region arranged around the channel. Performance improvements that could not be achieved with conventional FETs can be achieved. In addition, since it can be manufactured using an extremely easy process, it can be manufactured from single elements for low noise and power to ultra-high-speed digital LS.
It is possible to implement it in a wide range of application fields up to the basic elements of I.
第１図は本発明の四つの実施例のＦＥＴに共通する平面
図、第２図＜ａ）、（ｂ）は本発明の第１の実施例の直
角二方向における断面図、第３図（ａ）、（ｂ）は本発
明の第２の実施例の直角二方向における断面図、第４図
及び第５図はそれぞれ本発明の第３及び第４の実施例の
断面図である。
１・・・ＧａＡｓエピタキシャル基板、２ａ〜２ｄ・・
・反対導電型領域、３，３ａ〜３ｃ・・・チャネル層、
４・・・反対導電型島状領域、５・・・ゲート電極アロ
イ領域、６・・・ゲート電極、７・・・ソース電極、８
・・・ドレイン電極、９・・・ソース電極アロイ領域、
１０・・・ドレイン領域アロイ領域、１２・・・高濃度
層。
代理人 弁理士 内 原 晋
（Ｑ）
第
？
図
１、−ぬ
第
（ｂ）
第 ５ ン―FIG. 1 is a plan view common to the FETs of the four embodiments of the present invention, FIGS. a) and (b) are cross-sectional views taken in two orthogonal directions of the second embodiment of the present invention, and FIGS. 4 and 5 are cross-sectional views of the third and fourth embodiments of the present invention, respectively. 1...GaAs epitaxial substrate, 2a to 2d...
・Opposite conductivity type region, 3, 3a to 3c...channel layer,
4... Island region of opposite conductivity type, 5... Gate electrode alloy region, 6... Gate electrode, 7... Source electrode, 8
...Drain electrode, 9...Source electrode alloy region,
10... Drain region alloy region, 12... High concentration layer. Agent Patent Attorney Susumu Uchihara (Q) No. Figure 1, No. (b) No. 5
Claims (11)
ように、基板側と表面側の上下方向に配置された該チャ
ネル層と反対導電型の領域とを有し、該チャネル層を貫
通し上下方向に配置された該反対導電型領域を接続する
ように形成され、ソース電極からドレイン電極へ電子の
流れる方向と上下方向の双方に対し、垂直となる方向に
並べられた複数の該チャネル層と反対導電型の島状領域
をゲートとする事を特徴とする接合型電界効果トランジ
スタ。(1) It has a channel layer of one conductivity type and a region of the opposite conductivity type disposed vertically on the substrate side and the surface side so as to sandwich the channel layer, and has a region that penetrates the channel layer. A plurality of channel layers formed to connect the opposite conductivity type regions arranged in the vertical direction and arranged in a direction perpendicular to both the vertical direction and the direction in which electrons flow from the source electrode to the drain electrode. A junction field effect transistor characterized by having an island-shaped region of the opposite conductivity type as a gate.
表面側の上下方向に配置された該チャネル層と反対導電
型の領域とソース電極からドレイン電極へ電子の流れる
方向と上下方向の双方に対し、垂直となる方向に並べら
れた複数の該チャネル層と反対導電型の島状領域の両方
、又はどちらか一方が該チャネル層より大きなバンドギ
ャップの半導体で構成される特許請求の範囲第１項記載
の接合型電界効果トランジスタ。(2) Regions of the opposite conductivity type to the channel layer arranged vertically on the substrate side and the surface side so as to sandwich the channel layer of one conductivity type, and both in the direction in which electrons flow from the source electrode to the drain electrode and in the vertical direction. A plurality of island-like regions of opposite conductivity type arranged in a direction perpendicular to the channel layer, or either one of them, is made of a semiconductor having a larger bandgap than the channel layer. The junction field effect transistor according to item 1.
より挟み込む該チャネル層と反対導電型領域とが上下方
向に複数層配置され、該チャネル層と反対導電型の島状
領域がこれらの複数の反対導電型領域を接続するように
形成された特許請求の範囲第１項および第２項記載の接
合型電界効果トランジスタ。(3) A channel layer of one conductivity type and a plurality of regions of the opposite conductivity type sandwiching the channel layer from above and below are arranged in a plurality of layers in the vertical direction, and an island-shaped region of the opposite conductivity type to the channel layer is arranged between these channels. A junction field effect transistor according to claims 1 and 2, which is formed so as to connect a plurality of regions of opposite conductivity type.
イン電極から良好なオーミックコンタクトがとれ、該チ
ャネルを挟む反対導電型領域のキャリアがこれらの電極
に流れ込む事を阻止し得る高濃度のチャネル層と同一導
電型層がソース電極及びドレイン電極の基板側に設けら
れている事を特徴とする特許請求の範囲第１項、第２項
及び第３項記載の接合型電界効果トランジスタ。(4) A highly concentrated channel layer that can make good ohmic contact from the source electrode and drain electrode to the channel layer of one conductivity type, and can prevent carriers from the opposite conductivity type region sandwiching the channel from flowing into these electrodes. A junction field effect transistor according to claims 1, 2, and 3, characterized in that a layer of the same conductivity type as the source electrode and the drain electrode is provided on the substrate side of the source electrode and the drain electrode.
ル層を上下方向より挟む該チャネル層と同一組成の半導
体、又は該チャネル層よりバンドギャップの大きな半導
体で構成される該チャネル層と反対の導電層を一組又は
複数組形成した後、ゲートとなる島状領域をイオン注入
によって形成する事を特徴とする特許請求の範囲第１項
、第２項、第３項及び第４項記載の接合型電界効果トラ
ンジスタの製造方法。(5) A channel layer of one conductivity type on a semiconductor substrate, and a semiconductor having the same composition as the channel layer sandwiching the channel layer from above and below, or a semiconductor having a larger band gap than the channel layer, which is opposite to the channel layer. Claims 1, 2, 3, and 4 are characterized in that after one or more sets of conductive layers are formed, an island-like region that becomes a gate is formed by ion implantation. A method for manufacturing a junction field effect transistor.
とする特許請求の範囲第５項記載の接合型電界効果トラ
ンジスタの製造方法。(6) A method for manufacturing a junction field effect transistor according to claim 5, characterized in that a focused ion beam is used for ion implantation.
ル層を上下方向より挟む該チャネル層と同一組成の半導
体、又は該チャネル層よりバンドギャップの大きな半導
体で構成される、該チャネル層と反対の導電層を一組又
は複数組形成した後、ソース電極、ドレイン電極の基板
側に設けられるチャネル層と同一導電型高濃度領域をイ
オン注入によって形成する事を特徴とする特許請求の範
囲第４項記載の接合型電界効果トランジスタの製造方法
。(7) A channel layer formed of one conductivity type channel layer on a semiconductor substrate and a semiconductor having the same composition as the channel layer sandwiching the channel layer from above and below, or a semiconductor having a larger band gap than the channel layer; Claim 1, characterized in that after forming one or more sets of opposite conductive layers, a high concentration region of the same conductivity type as the channel layer provided on the substrate side of the source electrode and drain electrode is formed by ion implantation. 4. A method for manufacturing a junction field effect transistor according to item 4.
とする特許請求の範囲第７項記載の接合型電界効果トラ
ンジスタの製造方法。(8) A method for manufacturing a junction field effect transistor according to claim 7, characterized in that a focused ion beam is used for ion implantation.
ル層を上下方向より挟む該チャネル層と同一組成の半導
体、又は該チャネル層よりバンドギャップの大きな半導
体で構成される該チャネル層と反対の導電層を一組又は
複数組形成した後、イオン注入後に短時間アニールプロ
セスを含む事を特徴とする特許請求の範囲第５項、第６
項、第７項及び第８項記載の接合型電界効果トランジス
タの製造方法。(9) A channel layer of one conductivity type on a semiconductor substrate, and a semiconductor having the same composition as the channel layer sandwiching the channel layer from above and below, or a semiconductor having a larger band gap than the channel layer, which is opposite to the channel layer. Claims 5 and 6 include a short-time annealing process after ion implantation after forming one or more sets of conductive layers.
9. A method for manufacturing a junction field effect transistor according to Items 7 and 8.
エピタキシャル法によって形成する事を特徴とする特許
請求の範囲第１項、第２項、第３項及び第４項記載の接
合型電界効果トランジスタの製造方法。(10) A junction field effect transistor according to claims 1, 2, 3, and 4, characterized in that the island-like region serving as a gate is formed by selective etching and selective epitaxial method. manufacturing method.
るチャネル層と同一導電型高濃度領域を選択エッチング
と選択エピタキシャル法によって形成する事を特徴とす
る特許請求の範囲第４項記載の接合型電界効果トランジ
スタの製造方法。(11) A junction type electric field according to claim 4, characterized in that a high concentration region of the same conductivity type as the channel layer provided on the substrate side of the source electrode and drain electrode is formed by selective etching and selective epitaxial method. Method of manufacturing effect transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15729388A JPH025533A (en) | 1988-06-24 | 1988-06-24 | Junction field-effect transistor and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15729388A JPH025533A (en) | 1988-06-24 | 1988-06-24 | Junction field-effect transistor and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH025533A true JPH025533A (en) | 1990-01-10 |
Family
ID=15646493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15729388A Pending JPH025533A (en) | 1988-06-24 | 1988-06-24 | Junction field-effect transistor and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH025533A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08227900A (en) * | 1995-02-21 | 1996-09-03 | Nec Corp | Semiconductor device |
| WO2003079455A1 (en) * | 2002-03-15 | 2003-09-25 | Sumitomo Electric Industries, Ltd. | Lateral junctiion field-effect transistor and its manufacturing method |
| WO2007094493A1 (en) * | 2006-02-14 | 2007-08-23 | National Institute Of Advanced Industrial Science And Technology | Photo field effect transistor and integrated photodetector using same |
| JP2020526921A (en) * | 2017-07-06 | 2020-08-31 | テレダイン・サイエンティフィック・アンド・イメージング・エルエルシーＴｅｌｅｄｙｎｅ Ｓｃｉｅｎｔｉｆｉｃ ＆ Ｉｍａｇｉｎｇ，ＬＬＣ | FET with embedded gate structure |
-
1988
- 1988-06-24 JP JP15729388A patent/JPH025533A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08227900A (en) * | 1995-02-21 | 1996-09-03 | Nec Corp | Semiconductor device |
| WO2003079455A1 (en) * | 2002-03-15 | 2003-09-25 | Sumitomo Electric Industries, Ltd. | Lateral junctiion field-effect transistor and its manufacturing method |
| CN100379029C (en) * | 2002-03-15 | 2008-04-02 | 住友电气工业株式会社 | Lateral junction field-effect transistor and its manufacturing method |
| US7420232B2 (en) | 2002-03-15 | 2008-09-02 | Sumitomo Electric Industries, Ltd. | Lateral junction field effect transistor and method of manufacturing the same |
| US7671388B2 (en) | 2002-03-15 | 2010-03-02 | Sumitomo Electric Industries, Ltd. | Lateral junction field effect transistor and method of manufacturing the same |
| US7671387B2 (en) | 2002-03-15 | 2010-03-02 | Sumitomo Electric Industries, Ltd. | Lateral junction field effect transistor and method of manufacturing the same |
| WO2007094493A1 (en) * | 2006-02-14 | 2007-08-23 | National Institute Of Advanced Industrial Science And Technology | Photo field effect transistor and integrated photodetector using same |
| GB2445313A (en) * | 2006-02-14 | 2008-07-02 | Nat Inst Of Advanced Ind Scien | Photo field effect transitor and intergrated photodetector using same |
| US7759698B2 (en) | 2006-02-14 | 2010-07-20 | National Institute Of Advanced Industrial Science And Technology | Photo-field effect transistor and integrated photodetector using the same |
| GB2445313B (en) * | 2006-02-14 | 2011-03-23 | Nat Inst Of Advanced Ind Scien | Photo field effect transistor and integrated photodetector using same |
| JP4963120B2 (en) * | 2006-02-14 | 2012-06-27 | 独立行政法人産業技術総合研究所 | Optical field effect transistor and integrated photo detector using the same |
| JP2020526921A (en) * | 2017-07-06 | 2020-08-31 | テレダイン・サイエンティフィック・アンド・イメージング・エルエルシーＴｅｌｅｄｙｎｅ Ｓｃｉｅｎｔｉｆｉｃ ＆ Ｉｍａｇｉｎｇ，ＬＬＣ | FET with embedded gate structure |
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